JP2014082287A - Semiconductor memory device, method for manufacturing the same, and mobile terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which is a mixed chip of a volatile storage device and a nonvolatile storage device having excellent low power consumption and downsizing performance and capable of being applied to compact information equipment such as a mobile terminal.SOLUTION: A semiconductor memory device comprises: a first substrate 1; a DRAM part formed on the first substrate 1 and including a DRAM memory cell array (a capacitative element 8, a memory cell transistor 4, and the like) and a DRAM peripheral circuit (a transistor 3 for a peripheral circuit and the like); and a ReRAM part including a ReRAM memory cell array (a resistance change element 18, a memory cell transistor 13, and the like) and a ReRAM peripheral circuit (a transistor 2 for a peripheral circuit and the like). The ReRAM memory cell array is formed in a higher layer than the DRAM part. The DRAM peripheral circuit and the ReRAM peripheral circuit are regions on the first substrate 1, and formed in a region more peripheral than the DRAM memory cell array.

Description

  The present invention relates to a semiconductor memory device in which a variable resistance nonvolatile memory device whose resistance value is changed by application of a voltage pulse and a volatile memory device having a capacitor element, a manufacturing method thereof, and the like.

  In recent years, with the advancement of digital technology, electronic devices such as portable information devices and information home appliances have become more sophisticated, and there is a great demand for high-speed operation and low power consumption for these devices. In addition to these requirements, devices such as mobile phones and tablets, which are mobile terminals, are also required to support mobile applications such as weight reduction, thickness reduction, and size reduction. In particular, the market for smartphones (multi-function mobile phones) that perform large-capacity data communication has expanded explosively, and is replacing the feature phone. Smartphones are equipped with a large number of voice interfaces, position sensors, acceleration sensors, tilt sensors, proximity sensors, etc. to support various download applications, and large batteries are also installed for these devices. Therefore, it is difficult to reduce the size compared to feature phones.

  In addition, with the increase in functionality of these electronic devices, miniaturization and speeding up of semiconductor elements used are rapidly progressing. A smartphone includes an application system LSI that controls a large number of applications, a communication system LSI that processes data communication, and a memory chip that stores data linked to these system LSIs. In addition to the low power consumption performance, there is a great demand for these system LSIs and memories to reduce the size of the chip.

  As an example of downsizing of this chip, PCRAM (Phase-change Memory), which is a nonvolatile storage memory excellent in consistency with DRAM (Dynamic Random Access Memory), is used, and the exclusive area is not complicated. There has been proposed a semiconductor memory device that suppresses the increase in the memory speed and has a high access speed (see, for example, Patent Document 1). In this configuration, a part of the bit line of the DRAM and a part of the bit line of the PCRAM are configured by a common conductive layer, a sense amplifier is connected between the two, the memory device is simplified, and a small area chip is embedded. Chips are realized with fewer process steps.

JP 2006-295130 A

  However, in the above-described conventional semiconductor memory device, PCRAM and DRAM are mixedly mounted. However, since only a part of the bit line is shared, the area reduction is insufficient. In addition, by sharing the bit line, the circuit operation is restricted, and it becomes difficult to operate each memory under the optimum operation condition. Further, the combination of PCRAM and DRAM is still insufficient in terms of reducing power consumption.

  SUMMARY OF THE INVENTION The present invention solves the above-described problem, and is a mixed chip of a volatile memory device and a nonvolatile memory device, which is excellent in low power consumption and miniaturization performance and can be applied to small information devices such as mobile terminals. An object of the present invention is to provide a semiconductor memory device and a manufacturing method thereof.

  In order to achieve the above object, one embodiment of a semiconductor memory device according to the present invention includes a first substrate, a DRAM memory cell array formed on the first substrate and having a plurality of capacitor elements, and the DRAM. A DRAM section including a DRAM peripheral circuit which is a peripheral circuit for the memory cell array, a ReRAM memory cell array having a plurality of resistance change elements, and a ReRAM section including a ReRAM peripheral circuit which is a peripheral circuit for the ReRAM memory cell array. The ReRAM memory cell array is formed in an upper layer than the DRAM portion, and the DRAM peripheral circuit and the ReRAM peripheral circuit are regions on the first substrate and in a peripheral region from the DRAM memory cell array. Is formed.

  In order to achieve the above object, one mode of a mobile terminal according to the present invention is a mobile terminal equipped with the semiconductor memory device.

  In order to achieve the above object, one embodiment of a method of manufacturing a semiconductor memory device according to the present invention includes a step of forming a peripheral circuit transistor of a DRAM portion in a first region on a substrate, and a first step on the substrate. A step of forming a memory cell transistor of the DRAM portion in the second region, a step of forming a peripheral circuit transistor of the ReRAM portion in the third region on the substrate, and a peripheral circuit of the DRAM portion above the first region. A step of forming a wiring for use, a step of forming a capacitor element and a wiring of the DRAM portion above the second region, and a portion of the ReRAM portion above the second region and the capacitor element and wiring of the DRAM portion. Forming a memory cell and a wiring; and forming a peripheral circuit wiring of the ReRAM portion above the third region.

  According to the present invention, a semiconductor memory device which is a mixed chip of a volatile memory device and a nonvolatile memory device, which is excellent in low power consumption and miniaturization performance and can be applied to a small information device such as a mobile terminal, and a manufacturing method thereof Is realized.

Configuration diagram of major semiconductor integrated circuits used in mobile terminals Image of the package of a mobile terminal equipped with a conventional semiconductor memory device Image of package of mobile terminal equipped with semiconductor memory device of the present invention Sectional drawing which shows the structural example of the semiconductor memory device in Embodiment 1 of this invention. Plan view showing a configuration example of the semiconductor memory device Sectional drawing which shows the manufacturing method of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 5A) of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 5B) of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 5C) of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 5D) of the principal part of the same semiconductor memory device Sectional drawing which shows the structural example of the semiconductor memory device in Embodiment 2 of this invention. Plan view showing a configuration example of the semiconductor memory device Sectional drawing which shows the manufacturing method of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 7A) of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 7B) of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 7C) of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 7D) of the principal part of the same semiconductor memory device The figure which shows the variation of the layout of the semiconductor memory device of this invention

  The semiconductor memory device and the manufacturing method thereof according to the present invention relate to a structure in which a DRAM excellent in high-speed operation and a ReRAM excellent in low power consumption and non-volatility are integrated on a substrate to form a single chip. By disposing the main memory cell array of ReRAM above the DRAM, the chip area can be greatly reduced. This is because the DRAM and ReRAM are integrated three-dimensionally without affecting the characteristics of the DRAM because a high heat treatment temperature is not required when forming the variable resistance layer of the variable resistance element that is the core of the ReRAM. Because you can. Further, by forming the DRAM peripheral circuit and the ReRAM peripheral circuit independently on the substrate, each can be operated in an optimum state as in the case of a single chip. In particular, these can greatly contribute to the reduction in size, weight and thickness of mobile terminals.

  In other words, in order to achieve the above object, one embodiment of a semiconductor memory device according to the present invention includes a first substrate, a DRAM memory cell array formed on the first substrate, and having a plurality of capacitor elements, and A DRAM section including a DRAM peripheral circuit which is a peripheral circuit for the DRAM memory cell array, a ReRAM memory cell array having a plurality of resistance change elements, and a ReRAM section including a ReRAM peripheral circuit which is a peripheral circuit for the ReRAM memory cell array; The ReRAM memory cell array is formed in an upper layer than the DRAM portion, and the DRAM peripheral circuit and the ReRAM peripheral circuit are regions on the first substrate, and are located at the periphery of the DRAM memory cell array. Formed in the region.

  As a result, the ReRAM memory cell array, which is the main area of the ReRAM portion, is formed in an upper layer than the DRAM portion, so that the size is significantly larger than a package in which the DRAM portion and the ReRAM portion are arranged on the wiring substrate. A reduced package non-volatile storage device is realized.

  That is, as in the case where ReRAM and DRAM are formed independently, a semiconductor memory device that takes advantage of the low power consumption and non-volatility of ReRAM and the high speed of DRAM can be realized. Further, by arranging the ReRAM memory cell array, which is the main area, above the DRAM part (upper layer), the area can be significantly reduced.

  Therefore, a mixed chip of a volatile storage device and a nonvolatile storage device, which is excellent in low power consumption and downsizing performance and applicable to small information devices such as mobile terminals, is realized.

  Here, the ReRAM memory cell array may be formed at least above the DRAM memory cell array. For example, the ReRAM memory cell array may be formed above the DRAM memory cell array and above the DRAM peripheral circuit. As a result, the package size of the nonvolatile memory device is reduced by the area of the ReRAM memory cell array.

  The ReRAM peripheral circuit may be formed in a region on the first substrate and in a peripheral region with respect to the DRAM peripheral circuit. As a result, the ReRAM peripheral circuit is formed on the first substrate 1 with few crystal defects, so that a reliable ReRAM peripheral circuit that operates stably is formed.

  The ReRAM memory cell array further includes a plurality of memory cell transistors formed on the second substrate in addition to the plurality of resistance change elements. The second substrate is formed above the DRAM portion. You may have. As a result, a plurality of memory cell transistors constituting the ReRAM memory cell array are formed on the second substrate formed above the DRAM portion, so that a 1T1R (one transistor and one resistance change element) type ReRAM memory cell is provided. A semiconductor memory device is realized.

  The ReRAM memory cell array may be a cross-point type memory cell array having a plurality of current control elements in addition to the plurality of resistance change elements. Thereby, since the ReRAM memory cell array has a plurality of current control elements in addition to a plurality of resistance change elements, a semiconductor memory device including a cross-point type memory cell array is realized.

  Furthermore, a first wiring layer, a second wiring layer, and a third wiring layer are provided above the first substrate in order from the side closer to the first substrate. The wiring layer and the second wiring layer may be formed in the DRAM portion, and the third wiring layer may be a lowermost wiring layer of the ReRAM memory cell array. Thereby, a semiconductor memory device having a multilayer wiring layer is realized.

  In order to achieve the above object, one mode of the mobile terminal according to the present invention may be a mobile terminal equipped with the semiconductor memory device. As a result, a mobile terminal including a mixed chip of a volatile storage device and a nonvolatile storage device, which is excellent in low power consumption and downsizing performance, is realized.

  In order to achieve the above object, a method of manufacturing a semiconductor memory device according to the present invention includes a step of forming a peripheral circuit transistor of a DRAM portion in a first region on a substrate, and a step of forming a second region on the substrate. A step of forming a memory cell transistor of the DRAM portion, a step of forming a peripheral circuit transistor of the ReRAM portion in the third region on the substrate, and a peripheral circuit wiring of the DRAM portion above the first region. A step of forming, a step of forming a capacitor element and a wiring of a DRAM portion above the second region, a memory cell of a ReRAM portion and a capacitor element and a wiring of the DRAM portion above the second region and Forming a wiring; and forming a peripheral circuit wiring of the ReRAM portion above the third region. As a result, a method for manufacturing a semiconductor memory device, which is a mixed chip of a volatile memory device and a nonvolatile memory device, which is excellent in low power consumption and miniaturization performance and can be applied to a small information device such as a mobile terminal is realized. Is done.

  Here, the step of forming the memory cell and the wiring of the ReRAM portion includes a step of forming a second substrate, a step of forming a memory cell transistor of the ReRAM portion on the second substrate, Forming a variable resistance element of the ReRAM portion. As a result, a plurality of memory cell transistors constituting the ReRAM memory cell array are formed on the second substrate formed above the DRAM portion, so that a semiconductor memory device including 1T1R type ReRAM memory cells is manufactured.

  In the step of forming the memory cell and the wiring in the ReRAM portion, a memory cell including a resistance change element and a current control element may be formed. Thus, since the ReRAM memory cell array has a plurality of current control elements in addition to a plurality of resistance change elements, a semiconductor memory device including a cross-point type memory cell array is manufactured.

(Knowledge that became the basis of the present invention)
FIG. 1 shows a configuration of a main semiconductor integrated circuit used in a small information device such as a mobile terminal. As shown in this figure, semiconductor integrated circuits for such applications are broadly divided into application system LSI systems that control applications and communication system LSI systems that process data communications. The system LSI system for applications is a high-performance processor, a DRAM (for example, a storage capacity of 0.5 GB), which is a volatile storage device capable of high-speed processing, and a large memory for storing moving images. It is composed of a NAND flash memory (for example, a storage capacity of 16 GB) which is a non-volatile storage device with a capacity. On the other hand, the communication system LSI system includes a baseband processor corresponding to wireless communication, a DRAM (for example, a storage capacity of 16 MB) which is a volatile storage device having a relatively small storage capacity capable of high-speed processing, a random It is composed of a NOR flash memory (for example, a storage capacity of 16 MB), which is a non-volatile storage device that can handle access. These chips are packaged by POP (Package on Package) or SIP (System in Package) in view of the necessity of high-speed operation and yield loss.

  FIG. 2 shows a typical package example of a conventional communication system LSI system. FIG. 2A shows a single wiring between a baseband processor (package shown on the left side) and a DRAM and NOR flash packaged with memory and a POP package (package shown on the right side). A plan view (upper view) and a front view (lower view) of what is integrated on the substrate are shown. Thus, by stacking the memories (DRAM and NOR flash) with the POP package, it is possible to secure a larger mounting area when the device is mounted. Also, since each package can be tested individually, yield loss can be reduced. The wiring between the memories can be shortened, and the influence of reflection and noise can be minimized.

  FIG. 2B shows a plan view (upper view) and a front view (lower view) of a baseband processor in which DRAM and NOR flash are packaged by SIP integrated on a wiring board. ing. Since the entire system is housed in one package, the mounting area when mounting the device can be drastically reduced.

  However, the conventional packages shown in FIGS. 2A and 2B have the following problems in common with both. That is, although the area can be reduced by stacking chips, it is inevitable that the thickness increases. Moreover, although the wiring delay is suppressed by the connection on the wiring board, the wiring delay in the wire wiring due to the mounting still remains. In mobile terminals, this thinning and downsizing and the wiring delay accompanying the increase in the amount of data communication are becoming a problem.

  Accordingly, the inventors have devised a semiconductor memory device suitable for small information devices such as mobile terminals. FIG. 3 shows an image of a package of a mobile terminal in which the semiconductor memory device of the present invention is mounted. A baseband processor, DRAM, and ReRAM (Resistance Random Access Memory) are formed together in the manufacturing process of the previous process. Specifically, an embedded DRAM process is used for the baseband processor and DRAM configured with SOC, and instead of NOR flash, high-speed operation is possible with low power consumption in terms of devices, and thermal budget in terms of processes. ReRAM, which is a variable resistance nonvolatile memory device (a collection of variable resistance elements) that can be integrated in a wiring process while suppressing the above described, is used. With the above configuration, stack technology such as POP and SIP becomes unnecessary, and a thin package with a small area can be realized.

  Hereinafter, embodiments of a semiconductor memory device of the present invention will be described with reference to the drawings. Note that each of the embodiments described below shows a specific example of the present invention. The numerical values, shapes, materials, constituent elements, arrangement positions and connecting forms of the constituent elements, steps, order of steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept are described as optional constituent elements.

(Embodiment 1)
The semiconductor memory device according to the first embodiment of the present invention includes a first substrate, a DRAM memory cell array formed on the first substrate and having a plurality of capacitive elements, and a peripheral circuit for the DRAM memory cell array. A DRAM unit including a DRAM peripheral circuit, a ReRAM memory cell array having a plurality of resistance change elements, and a ReRAM unit including a ReRAM peripheral circuit that is a peripheral circuit for the ReRAM memory cell array. The DRAM peripheral circuit and the ReRAM peripheral circuit are formed on a region on the first substrate and in a peripheral region with respect to the DRAM memory cell array. Furthermore, the semiconductor memory device according to the present embodiment includes a second substrate formed above the DRAM portion, and the ReRAM memory cell array is formed on the second substrate in addition to the plurality of resistance change elements. It has a plurality of memory cell transistors. That is, in this embodiment, the ReRAM memory cell is a so-called 1T1R type.

  With the above configuration, it is possible to realize a semiconductor memory device that takes advantage of the low power consumption and non-volatility of ReRAM and the high speed of DRAM as in the case where ReRAM and DRAM are formed independently. Further, by arranging the ReRAM memory cell array, which is the main area, above the DRAM part (upper layer), the area can be significantly reduced.

  A specific example of the structure of the semiconductor memory device in this embodiment will be described below with reference to FIGS. 4A and 4B. FIG. 4A is a cross-sectional view showing a configuration example of the semiconductor memory device 1000 according to the first embodiment of the present invention. FIG. 4B is a plan view thereof.

  The semiconductor memory device 1000 has three areas on the first substrate 1, a DRAM memory cell array area 101, a DRAM peripheral circuit area 102, and a ReRAM peripheral circuit area 202. Further, the ReRAM memory cell array region 201 is disposed above the DRAM portion (in the present embodiment, above the DRAM memory cell array region 101 and the DRAM peripheral circuit region 102). That is, in this embodiment, the ReRAM memory cell array region 201 is located above the DRAM memory cell array region 101 and above the DRAM peripheral circuit region 102. In addition, the ReRAM peripheral circuit region 202 is located on the first substrate 1 and at the periphery of the DRAM peripheral circuit region 102. In FIG. 4B, when the semiconductor memory device 1000 is viewed from above, the DRAM memory cell array region 101 is inside the smaller dotted frame. The DRAM peripheral circuit region 102 is outside the smaller dotted frame and inside the larger dotted frame. The ReRAM memory cell array region 201 is inside the smaller solid line frame (that is, the region including the DRAM memory cell array region 101 and the DRAM peripheral circuit region 102). The ReRAM peripheral circuit area 202 is outside the smaller solid line frame and inside the larger solid line frame.

  Here, the DRAM memory cell array region 101 is a region for forming a DRAM memory cell array having a plurality of capacitive elements. The DRAM peripheral circuit region 102 is a region for forming a DRAM peripheral circuit which is a peripheral circuit for a DRAM memory cell array. The ReRAM memory cell array region 201 is a region for forming a ReRAM memory cell array having a plurality of resistance change elements. The ReRAM peripheral circuit area 202 is an area for forming a ReRAM peripheral circuit that is a peripheral circuit for the ReRAM memory cell array. Note that the DRAM memory cell array region 101 and the DRAM peripheral circuit region 102 mean a space above the first substrate 1 and below the second substrate 12 in the stacking direction. Further, the ReRAM memory cell array region 201 means a space above the second substrate 12 in the stacking direction. A circuit including the DRAM memory cell array and the DRAM peripheral circuit is referred to as a DRAM section, and a circuit including the ReRAM memory cell array and the ReRAM peripheral circuit is referred to as a ReRAM section.

  Here, the DRAM memory cell array is a collection of DRAM memory cells. The ReRAM memory cell array is a group of non-volatile memory elements (resistance change elements) whose resistance value changes with application of a voltage pulse.

  The peripheral circuit for the DRAM memory cell array is a circuit related to the DRAM memory cell array, a selection circuit (address / decode circuit) for selecting a DRAM memory cell from the DRAM memory cell array, and driving the selected DRAM memory cell. It includes at least one of a drive circuit, a write circuit to the DRAM memory cell array, a read circuit from the DRAM memory cell array, a control circuit that controls writing and reading, and a power supply circuit that supplies power for writing and reading.

  The peripheral circuit for the ReRAM memory cell array is a circuit related to the ReRAM memory cell array, a selection circuit (address / decode circuit) for selecting a ReRAM memory cell from the ReRAM memory cell array, and driving the selected ReRAM memory cell. At least one of a drive circuit, a write circuit to the ReRAM memory cell array, a read circuit from the ReRAM memory cell array, a control circuit that controls writing and reading, and a power supply circuit that supplies power for writing and reading is included.

  As shown in FIG. 4A, a DRAM memory cell transistor 4 is formed on the first substrate 1 in the DRAM memory cell array region 101, and a DRAM peripheral circuit region is formed on the first substrate 1 in the DRAM peripheral circuit region 102. On the first substrate 1 in the ReRAM peripheral circuit area 202, the transistor 3 for the ReRAM peripheral circuit is formed. In this figure, a portion in the semiconductor memory device 1000 where no circuit components and wiring are formed above the first substrate 1 (white portion in the figure) is an interlayer insulating layer. The same applies to other sectional views.

  In an interlayer insulating layer covering the various transistors (memory cell transistor 4, peripheral circuit transistor 3, peripheral circuit transistor 2), a first contact connected to the main electrode of each transistor on the first substrate 1 is provided. A plug 5 is formed, and a first wiring (first wiring layer) 6 connected to the plug 5 is formed on the first contact plug 5. In the DRAM memory cell array region 101, in addition to the first wiring 6 functioning as a bit line, a second A contact plug 7 is formed on the first contact plug 5, and a capacitor element 8 is formed thereon. Is done.

  The capacitive element 8 includes a lower electrode, a capacitive insulating film, and an upper electrode. Here, as the structure of the capacitive element 8, a planar type is exemplified here, but a concave type may be used. A 2B contact plug 9 is formed on the capacitive element 8.

  On the other hand, in the DRAM peripheral circuit region 102 and the ReRAM peripheral circuit region 202, a 2C contact plug 10 connected to the first wiring 6 is formed in an interlayer insulating layer covering the first wiring 6. Further, a second wiring (second wiring layer) 11 connected to the second B contact plug 9 and the second C contact plug 10 is formed on the second B contact plug 9 and the second C contact plug 10. With the above-described components, the DRAM portion is completed as a device.

  A second substrate 12 made of, for example, silicon is formed at least partially above the DRAM memory cell array region 101 and the DRAM peripheral circuit region 102 (that is, above the DRAM portion). A ReRAM memory cell transistor 13 is formed on the second substrate 12. In the interlayer insulating layer covering the ReRAM memory cell transistor 13, a 3A contact plug 14 connected to the main electrode of the ReRAM memory cell transistor 13 on the second substrate 12 is formed. In a region where the substrate 12 is not formed, a 3B contact plug 15 connected to the second wiring 11 is formed. A third wiring (third wiring layer) 16 is formed on the 3A contact plug 14 and the 3B contact plug 15. In the ReRAM memory cell array region 201, a 4A contact plug 17 is formed on the 3A contact plug 14 in addition to the 3rd wiring 16 functioning as a bit line, and a resistance change element 18 is formed thereon. It is formed.

  The resistance change element 18 includes a lower electrode, a resistance change layer, and an upper electrode. In addition, although the planar structure was illustrated here as a structure of the resistance change element 18, it may be a hole type. A 4B contact plug 19 is formed on the variable resistance element 18.

  On the other hand, in the ReRAM peripheral circuit region 202, a 4C contact plug 20 connected to the third wiring 16 is formed in an interlayer insulating layer covering the third wiring 16. Further, a fourth wiring (fourth wiring layer) 21 connected to the 4B contact plug 19 and the 4C contact plug 20 is formed on the 4B contact plug 19 and the 4C contact plug 20.

  As described above, in the semiconductor memory device 1000 according to the present embodiment, the first wiring 6, the second wiring 11, and the first wiring 1 are arranged above the first substrate 1 in order from the side closer to the first substrate 1. Four wiring layers of the third wiring 16 and the fourth wiring 21 are provided. Here, two wiring layers are used for the DRAM, and two wiring layers are used for the ReRAM. As a result, the semiconductor memory device of the present invention can be realized with a minimum number of wiring layers, that is, with a reduced number of process steps and reduced costs. However, the present invention is not limited to this, and the number of wiring layers may be increased in response to a request for encryption or higher functionality, or the number of wiring layers may be decreased in response to a request for downsizing. Absent. For example, one wiring layer may be used for ReRAM.

  Further, the boundary between the DRAM memory cell array region 101 and the DRAM peripheral circuit region 102 and the boundary between the ReRAM memory cell array region 201 and the ReRAM peripheral circuit region 202 are boundaries for functionally dividing them into blocks. In this specification, for convenience of understanding, the former boundary is connected to the outer edge of the outermost capacitive element among the plurality of capacitive elements 8, and the latter boundary is connected to the outermost of the plurality of resistance change elements 18. It is assumed that the outer edge of the outer resistance change element is connected by a line. Therefore, the DRAM peripheral circuit region 102 and the ReRAM peripheral circuit region 202 may overlap each other (that is, if there is no actual influence on the operation of each memory, there may be a shared circuit). ). Here, at least a part of the DRAM memory cell array region 101 may be covered and the ReRAM memory cell array region 201 may be disposed, and a semiconductor memory device effective for a small information device such as a mobile terminal can be realized.

  As described above, the semiconductor memory device 1000 according to the present embodiment is formed on the first substrate 1 and includes a DRAM memory cell array (memory cell transistor 4, capacitor element 8 and the like) having a plurality of capacitor elements 8, and A DRAM portion including a DRAM peripheral circuit (peripheral circuit transistor 3 and the like), which is a peripheral circuit for the DRAM memory cell array, and a ReRAM memory cell array (memory cell transistor 13 and resistance change element 18 and the like) having a plurality of resistance change elements 18; And a ReRAM unit including a ReRAM peripheral circuit (peripheral circuit transistor 2 or the like) which is a peripheral circuit for the ReRAM memory cell array. The ReRAM memory cell array is formed in an upper layer than the DRAM portion, and the DRAM peripheral circuit and the ReRAM peripheral circuit are formed in a region on the first substrate 1 and in a peripheral region from the DRAM memory cell array. . As a result, the ReRAM memory cell array, which is the main area, is arranged above (above) the DRAM section, so that a semiconductor memory device with a significantly reduced area is realized, and a small information device such as a mobile terminal Thus, a mixed chip of a volatile memory device and a nonvolatile memory device that is excellent in low power consumption and downsizing performance that can be applied to the present invention is realized.

  In this embodiment, the ReRAM memory cell is a so-called 1T1R type. For this purpose, a second substrate 12 is provided above the DRAM section, and the ReRAM memory cell array has a plurality of memory cell transistors 13 formed on the second substrate 12 in addition to the plurality of resistance change elements 18.

  Next, a method for manufacturing the semiconductor memory device 1000 according to the present embodiment configured as described above will be described. 5A to 5E are cross-sectional views of semiconductor memory device 1000 showing the method for manufacturing semiconductor memory device 1000 in the first embodiment of the present invention.

  First, as shown in FIG. 5A, a DRAM peripheral circuit transistor 3 is formed in the DRAM peripheral circuit region 102 of the first substrate 1.

  Next, as shown in FIG. 5A, a DRAM memory cell transistor 4 is formed in the DRAM memory cell array region 101 of the first substrate 1.

  Next, as shown in (c) of FIG. 5A, the ReRAM peripheral circuit transistor 2 is formed in the ReRAM peripheral circuit region 202 of the first substrate 1.

  Next, as shown in FIG. 5A (d), an interlayer insulating layer that covers the above-described various transistors is formed, and a first contact plug 5 that passes through the interlayer insulating layer and is connected to the main electrodes of the various transistors is formed. To do. Further, a first wiring 6 connected to the first contact plug 5 is formed on the interlayer insulating layer.

  Next, as shown in FIG. 5A (e), after an interlayer insulating layer covering the first wiring 6 is formed, the interlayer insulation is formed on the first contact plug 5 in the DRAM memory cell array region 101. A 2A contact plug 7 penetrating the layer is formed. Further, a capacitor element 8 including a lower electrode, a capacitor insulating film, and an upper electrode is formed on the second A contact plug 7.

  Next, as shown in FIG. 5B (f), an interlayer insulating layer covering the capacitor element 8 is formed, and in the interlayer insulating layer, a second B contact plug 9 connected to the capacitor element 8, and the first A second C contact plug 10 connected to the first wiring 6 is formed. Further, a second wiring 11 connected to these contact plugs is formed on the interlayer insulating layer.

  Next, as shown in FIG. 5B (g), after forming an interlayer insulating layer covering the whole, a second substrate 12 is formed above the DRAM memory cell array region 101. About the 2nd board | substrate 12, it forms by patterning using the method of selectively forming Si semiconductor with a laser, or a desired mask, and forms Si semiconductor. Subsequently, the ReRAM memory cell transistor 13 is formed in the ReRAM memory cell array region 201 of the second substrate 12. It is inevitable that the second substrate 12 produced here has more crystal defects than the first substrate 1 formed by the ingot method, but the ReRAM memory cell transistor 13 has an OFF characteristic. Since the driving current with high ON characteristics is more important than the low leakage performance, desired characteristics can be realized. Since the circuit for controlling the driving of the ReRAM is formed on the first substrate 1, there is no problem in device operation. Here, as will be described in the next step, in the ReRAM peripheral circuit region 202, a part of the ReB peripheral circuit region 202 is formed so that the 3B contact plug 15 connecting the second wiring 11 and the third wiring 16 can be formed. The second substrate 12 may not be formed, or the second substrate 12 may be removed.

  Next, as shown in (h) of FIG. 5C, an interlayer insulating layer that covers the memory cell transistor 13 of ReRAM is formed, and the third insulating layer is formed through the third insulating layer A connected to the main electrode of the memory cell transistor 13 of ReRAM. The contact plug 14 and the 3B contact plug 15 connected to the second wiring 11 are formed. Further, a third wiring 16 connected to the 3A contact plug 14 and the 3B contact plug 15 is formed on the interlayer insulating layer.

  Next, as shown in FIG. 5D (i), after forming an interlayer insulating layer covering the third wiring 16, in the ReRAM memory cell array region 201, the interlayer insulation is formed on the 3A contact plug 14. A 4A contact plug 17 penetrating the layer is formed. Further, a resistance change element 18 including a lower electrode, a resistance change layer, and an upper electrode is formed on the 4A contact plug 17.

  Finally, as shown in FIG. 5E (j), an interlayer insulating layer covering the resistance change element 18 is formed, and in the interlayer insulation layer, a 4B contact plug 19 connected to the resistance change element 18, Then, a 4C contact plug 20 connected to the third wiring 16 is formed. Further, the fourth wiring 21 connected to these contact plugs is formed on the interlayer insulating layer, and the semiconductor memory device 1000 is completed.

  As described above, the manufacturing method of the semiconductor memory device 1000 according to the present embodiment includes (1) the peripheral circuit of the DRAM section in the first region (DRAM peripheral circuit region 102) on the first substrate 1 as main steps. Forming a transistor for a memory, (2) forming a transistor for a memory cell in a DRAM section in a second region (DRAM memory cell array region 101) on the first substrate 1, and (3) a first substrate 1 Forming a peripheral circuit transistor of the ReRAM portion in the upper third region (ReRAM peripheral circuit region 202); and (4) a peripheral circuit wiring of the DRAM portion above the first region (DRAM peripheral circuit region 102). A step of forming (first wiring 6); and (5) a capacitor element 8 and wiring (second wiring 11) in the DRAM section above the second area (DRAM memory cell array area 101). And (6) a memory cell (memory cell transistor 13, resistance change element 18, etc.) and wiring (third wiring) in the ReRAM section above the second region and on the capacitor element 8 and wiring in the DRAM section. 16) and (7) forming a peripheral circuit wiring (first wiring 6, second wiring 11, third wiring 16, etc.) of the ReRAM section above the third region. including.

  In this embodiment, since the ReRAM memory cell is composed of 1T1R, the process of forming the memory cell and the wiring of the ReRAM portion includes (1) a process of forming the second substrate 12 and (2) a second process. A step of forming a memory cell transistor (memory cell transistor 13) in the ReRAM portion on the second substrate 12, and a step of forming a resistance change element (resistance change element 18) in the ReRAM portion.

  With such a manufacturing method, the volatile storage device and the nonvolatile memory excellent in low power consumption and downsizing performance that can be applied to the semiconductor storage device 1000 in this embodiment, that is, a small information device such as a mobile terminal. A mixed chip with a storage device is manufactured.

  Although not shown in the semiconductor memory device 1000 of the present embodiment, a system LSI (SOC baseband for mobile devices) is provided in an area other than the DRAM and ReRAM as in the case of the embedded DRAM process. Processor) or the like. That is, the present invention may be realized as a small information device such as a mobile terminal provided with the semiconductor memory device in this embodiment. At that time, circuits such as various processors may be incorporated in the semiconductor memory device in this embodiment.

  By the manufacturing method described above, a semiconductor memory device can be realized that takes advantage of the low power consumption and non-volatility of ReRAM and the high speed of DRAM as in the case of forming ReRAM and DRAM independently. The reason for this is that the peripheral circuit transistors for memory and the DRAM memory cell transistors sensitive to crystal defects necessary for controlling the operation are formed on the first substrate 1 which is stable and has few crystal defects. This is because the memory cell transistor for ReRAM that only needs to have current and switch characteristics is formed on the second substrate 12. In addition, by utilizing the fact that the thermal budget is small for the formation of the variable resistance element of ReRAM, the ReRAM memory cell array, which is the main area in the area above (above) the DRAM part, is arranged, thereby greatly reducing the area. Is possible. As a result, a thin and small-sized semiconductor memory device that does not require stack packaging technology can be realized.

(Embodiment 2)
A semiconductor memory device according to a second embodiment of the present invention includes a first substrate, a DRAM memory cell array formed on the first substrate and having a plurality of capacitive elements, and a peripheral circuit for the DRAM memory cell array. A DRAM unit including a DRAM peripheral circuit, a ReRAM memory cell array having a plurality of resistance change elements, and a ReRAM unit including a ReRAM peripheral circuit that is a peripheral circuit for the ReRAM memory cell array. The DRAM peripheral circuit and the ReRAM peripheral circuit are formed on a region on the first substrate and in a peripheral region with respect to the DRAM memory cell array. Here, the ReRAM memory cell array is a cross-point type memory cell array having a plurality of current control elements in addition to a plurality of resistance change elements. That is, in this embodiment, the ReRAM memory cell is a cross-point type configured by connecting one current control element (for example, a bidirectional diode) and one resistance change element in series.

  With the above configuration, it is possible to realize a semiconductor memory device that takes advantage of the low power consumption and non-volatility of ReRAM and the high speed of DRAM as in the case where ReRAM and DRAM are formed independently. In addition, since the cross-point type ReRAM memory cell array, which is the main area, can be multilayered above the DRAM section (above), the capacity can be increased and the chip area can be significantly reduced. Is possible.

  A specific example of the structure of the semiconductor memory device in this embodiment will be described below with reference to FIGS. 6A and 6B. FIG. 6A is a cross-sectional view showing a configuration example of the semiconductor memory device 2000 according to the second embodiment of the present invention. FIG. 6B is a plan view thereof.

  The configuration of the semiconductor memory device 2000 according to the second embodiment of the present invention is different from the semiconductor memory device 1000 according to the first embodiment of the present invention in that the switching element of the ReRAM memory cell array is not a memory cell transistor but a current control element. (For example, a bidirectional diode). That is, in the present embodiment, the memory cell composed of the memory cell transistor and the resistance change element in the first embodiment is replaced with a cross-point type memory cell composed of the resistance change element and the current control element. Yes. For this reason, since the memory cell transistor is not required, the second substrate 12 required in the first embodiment is not required. In this respect, the semiconductor memory device 2000 in the present embodiment has a simpler structure. The structure of the DRAM portion and the plan view of the DRAM region and the ReRAM region are the same as in the first embodiment.

  On the first substrate 1, there are three areas: a DRAM memory cell array area 101, a DRAM peripheral circuit area 102, and a ReRAM peripheral circuit area 202. Further, the ReRAM memory cell array region 201 is disposed above the DRAM portion (in the present embodiment, above the DRAM memory cell array region 101 and the DRAM peripheral circuit region 102). That is, in the present embodiment, as in the first embodiment, the ReRAM memory cell array region 201 is located above the DRAM memory cell array region 101 and above the DRAM peripheral circuit region 102. In addition, the ReRAM peripheral circuit region 202 is located on the first substrate 1 and at the periphery of the DRAM peripheral circuit region 102. 6B, the positions of the DRAM memory cell array region 101, the DRAM peripheral circuit region 102, the ReRAM memory cell array region 201, and the ReRAM peripheral circuit region 202 when the semiconductor memory device 2000 is viewed from above are shown in FIG. This is the same as Embodiment 1 shown in 4B.

  As shown in FIG. 6A, a DRAM memory cell transistor 4 is formed on the first substrate 1 in the DRAM memory cell array region 101, and a DRAM peripheral circuit region is formed on the first substrate 1 in the DRAM peripheral circuit region 102. On the first substrate 1 in the ReRAM peripheral circuit area 202, the transistor 3 for the ReRAM peripheral circuit is formed.

  In an interlayer insulating layer covering the various transistors (memory cell transistor 4, peripheral circuit transistor 3, peripheral circuit transistor 2), a first contact connected to the main electrode of each transistor on the first substrate 1 is provided. A plug 5 is formed, and a first wiring (first wiring layer) 6 connected to the plug 5 is formed on the first contact plug 5. In the DRAM memory cell array region 101, in addition to the first wiring 6 functioning as a bit line, a second A contact plug 7 is formed on the first contact plug 5, and a capacitor element 8 is formed thereon. Is done.

  The capacitive element 8 includes a lower electrode, a capacitive insulating film, and an upper electrode. Here, as the structure of the capacitive element 8, a planar type is exemplified here, but a concave type may be used. A 2B contact plug 9 is formed on the capacitive element 8.

  On the other hand, in the DRAM peripheral circuit region 102 and the ReRAM peripheral circuit region 202, a 2C contact plug 10 connected to the first wiring 6 is formed in an interlayer insulating layer covering the first wiring 6. Further, a second wiring (second wiring layer) 11 connected to the second B contact plug 9 and the second C contact plug 10 is formed on the second B contact plug 9 and the second C contact plug 10. With the above-described components, the DRAM portion is completed as a device.

  Above the DRAM memory cell array region 101 and the DRAM peripheral circuit region 102, a ReRAM memory cell array region 201 in which a cross-point type ReRAM memory cell array is formed is disposed. In the ReRAM memory cell array region 201, a second wiring 11 and a third wiring (third wiring layer) 16 are formed via an interlayer insulating layer, and a 4A contact plug 17 and a first wiring are formed thereon. A layer of variable resistance element 18 is formed.

  The first-layer cross-point type memory cell 22 includes a lower electrode, a current control layer, a resistance change layer, and an upper electrode that constitute a resistance change element and a current control element, and has a non-linear current-voltage characteristic, that is, a diode characteristic function. Have On these cross-point type memory cells 22, a third wiring 16 and a fourth wiring (fourth wiring layer) 21 orthogonal to the third wiring 16 connected to the third wiring 16 are formed. . On the fourth wiring 21, a 5A contact plug 23 and a second-layer cross-point type memory cell 24 are formed.

  The cross-point memory cell 24 in the second layer is also composed of a lower electrode, a current control layer, a resistance change layer, and an upper electrode that constitute the resistance change element and the current control element. Characteristic, that is, a diode characteristic function. On these second-layer cross-point type memory cells 24, there are connected a fourth wiring 21 and a fifth wiring (fifth wiring layer) 26 orthogonal to the fourth wiring 21. Is formed. Here, a planar structure is illustrated as a cross-point type memory cell (a memory cell in which a resistance change element and a current control element are connected to an intersection of upper and lower wirings), but a hole type may also be used. . In the ReRAM memory cell array region 201, the third wiring 16 and the fourth wiring 21 are orthogonal to each other, and the fourth wiring 21 and the fifth wiring 26 are orthogonal to each other. This is why it is called a cross-point type.

  On the other hand, in the ReRAM peripheral circuit region 202, a 3B contact plug 15 connected to the second wiring 11 is formed in an interlayer insulating layer covering the second wiring 11. A third wiring 16 is formed on the third-B contact plug 15. In the interlayer insulating layer covering the third wiring 16, a 4C contact plug 20 connected to the third wiring 16 is formed, and further connected to the fourth C contact plug 20 on this. A fourth wiring 21 is formed. Similarly, in the interlayer insulating layer covering the fourth wiring 21, a 5C contact plug 25 connected to the fourth wiring 21 is formed, and the fifth C contact plug 25 is further formed on the fifth C contact plug 25. A wiring 26 is formed. In the ReRAM peripheral circuit region 202, the third wiring 16, the fourth wiring 21, and the fifth wiring 26 are arranged in a desired layout. Therefore, it is not necessary for all of these wirings to be orthogonal to each other, and a part of the wiring may be arranged in parallel with other wirings.

  As described above, the semiconductor memory device 2000 in the present embodiment is formed on the first substrate 1 and includes a DRAM memory cell array (memory cell transistor 4, capacitor element 8, etc.) having a plurality of capacitor elements 8, and A DRAM portion including a DRAM peripheral circuit (peripheral circuit transistor 3 or the like), which is a peripheral circuit for the DRAM memory cell array, and a ReRAM memory cell array (first-layer cross-point type memory cell 22, second layer) having a plurality of resistance change elements. And a ReRAM section including a ReRAM peripheral circuit (peripheral circuit transistor 2 and the like) which is a peripheral circuit for the ReRAM memory cell array. The ReRAM memory cell array is formed in an upper layer than the DRAM portion, and the DRAM peripheral circuit and the ReRAM peripheral circuit are formed in a region on the first substrate 1 and in a peripheral region from the DRAM memory cell array. . As a result, the ReRAM memory cell array, which is the main area, is arranged above (above) the DRAM section, so that a semiconductor memory device with a significantly reduced area is realized, and a small information device such as a mobile terminal Thus, a mixed chip of a volatile memory device and a nonvolatile memory device that is excellent in low power consumption and downsizing performance that can be applied to the present invention is realized.

  In the present embodiment, the ReRAM memory cell array is a cross-point type memory cell array having a plurality of current control elements in addition to a plurality of resistance change elements.

  Next, a method for manufacturing the semiconductor memory device 2000 according to the present embodiment configured as described above will be described. 7A to 7C are cross-sectional views of semiconductor memory device 2000 showing the method for manufacturing semiconductor memory device 2000 in the second embodiment of the present invention. Since the processes before the process shown in FIG. 7A are the same as (a) to (f) of FIG. 5A, description thereof is omitted.

  First, as shown in FIG. 7A, a DRAM is formed in the DRAM memory cell array region 101 and the DRAM peripheral circuit region 102 on the first substrate 1. A ReRAM peripheral circuit transistor 2 is formed in the outer (peripheral) ReRAM peripheral circuit region 202. An interlayer insulating layer covering the whole is formed thereon, and a 3B contact plug 15 connected to the second wiring 11 is formed in the ReRAM peripheral circuit region 202.

  Next, as illustrated in FIG. 7B, in the ReRAM memory cell array region 201, a 4A contact plug 17 that penetrates the interlayer insulating layer is formed on the third wiring 16. Further, on the 4A contact plug 17, a first-layer cross-point type memory cell 22 including a lower electrode, a current control layer, a resistance change layer, and an upper electrode is formed.

  Next, as shown in FIG. 7C, first, a 4C contact plug 20 is formed on the third wiring 16 in the ReRAM peripheral circuit region 202. Further, a fourth wiring 21 connected to the 4C contact plug 20 and the first cross-point type memory cell 22 is formed.

  Next, as illustrated in FIG. 7D, in the ReRAM memory cell array region 201, a 5A contact plug 23 that penetrates the interlayer insulating layer is formed on the fourth wiring 21. Further, on the 5A contact plug 23, a second-layer cross-point type memory cell 24 including a lower electrode, a current control layer, a resistance change layer, and an upper electrode is formed.

  Finally, as shown in FIG. 7E, first, a 5C contact plug 25 is formed on the fourth wiring 21 in the ReRAM peripheral circuit region 202. Further, the fifth wiring 26 connected to the 5C contact plug 25 and the second-layer cross-point type memory cell 24 is formed, and the semiconductor memory device 2000 is completed.

  As described above, the manufacturing method of the semiconductor memory device 2000 according to the present embodiment includes (1) the peripheral circuit of the DRAM section in the first region (DRAM peripheral circuit region 102) on the first substrate 1 as main steps. Forming a transistor for a memory, (2) forming a transistor for a memory cell in a DRAM section in a second region (DRAM memory cell array region 101) on the first substrate 1, and (3) a first substrate 1 Forming a peripheral circuit transistor of the ReRAM portion in the upper third region (ReRAM peripheral circuit region 202); and (4) a peripheral circuit wiring of the DRAM portion above the first region (DRAM peripheral circuit region 102). A step of forming (first wiring 6); and (5) a capacitor element 8 and wiring (second wiring 11) in the DRAM section above the second area (DRAM memory cell array area 101). (6) ReRAM memory cells (one-layer cross-point type memory cell 22, second-layer cross-point type memory) above the second region and on the capacitor element 8 and wiring in the DRAM unit. Cell 24) and wiring (third wiring 16, fourth wiring 21, fifth wiring 26), and (7) peripheral circuit wiring (first circuit) in the ReRAM section above the third region. Forming the second wiring 6, the second wiring 11, the third wiring 16, the fourth wiring 21, and the fifth wiring 26).

  In this embodiment, since the ReRAM memory cell is a cross-point type, in the step of forming the memory cell and wiring of the ReRAM portion, a cross-point type memory cell composed of a resistance change element and a current control element is used. Form.

  With such a manufacturing method, the volatile storage device and the nonvolatile memory excellent in low power consumption and downsizing performance that can be applied to the semiconductor storage device 2000 in this embodiment, that is, a small information device such as a mobile terminal. A mixed chip with a storage device is manufactured.

  Although not shown in the semiconductor memory device 2000 of the present embodiment, as in the case of the embedded DRAM process and the like, a system LSI (an baseband for mobile use) is an SOC other than the above DRAM and ReRAM. (Processor) etc. may be formed. That is, the present invention may be realized as a small information device such as a mobile terminal provided with the semiconductor memory device in this embodiment. At that time, circuits such as various processors may be incorporated in the semiconductor memory device in this embodiment.

  In this device, the number of ReRAM memory cells is two, but it may be one or three or more as required.

  By the manufacturing method described above, a semiconductor memory device can be realized that takes advantage of the low power consumption and non-volatility of ReRAM and the high speed of DRAM as in the case of forming ReRAM and DRAM independently. The reason is that the transistor for the peripheral circuit of the memory necessary for controlling the operation is formed on the first substrate 1 which is stable and has few crystal defects, and the switching of the ReRAM which only requires high driving current and switching characteristics. This is because a current control element having a diode characteristic connected to the variable resistance element is incorporated as the element. In addition, by utilizing the fact that the thermal budget is small for the formation of variable resistance elements in ReRAM, the ReRAM memory cell array, which is the main area in the area above the DRAM part (upper layer), is arranged, thereby greatly reducing the area. Is possible. As a result, it is possible to form a thin and small area that does not require a stack packaging technique. Furthermore, in a ReRAM memory cell that does not require a memory cell transistor, the capacity of the memory in the ReRAM portion can be increased by increasing the number of layers.

  Although the semiconductor memory device and the manufacturing method thereof according to a plurality of aspects of the present invention have been described based on the first and second embodiments, the present invention is not limited to these first and second embodiments. Absent. As long as they do not depart from the gist of the present invention, various modifications conceivable by those skilled in the art are made in these Embodiments 1 and 2, and forms constructed by combining components in different embodiments are also included in the present invention. It may be included within the scope of one or more embodiments.

  For example, in the first and second embodiments, the ReRAM memory cell array region 201 coincides with the combined region of the DRAM memory cell array region 101 and the DRAM peripheral circuit region 102 when the semiconductor memory device is viewed from above. It is not limited to the width and position of such a region. FIG. 8 is a diagram showing a variation of the layout of the semiconductor memory device of the present invention. When the semiconductor memory device is viewed from above, the ReRAM memory cell array region 201 may coincide with the DRAM memory cell array region 101 as shown in FIG. 8A, or FIG. As shown in FIG. 4, a part of the DRAM memory cell array region 101 may be used. Further, as shown in FIG. 8C, it may be a region including a part of the DRAM memory cell array region 101 and a part of the DRAM peripheral circuit region 102, or as shown in FIG. As described above, it may be a region including the entire DRAM memory cell array region 101 and a part of the DRAM peripheral circuit region 102. Further, as shown in FIG. 8E, the DRAM memory cell array region 101, a part of the DRAM peripheral circuit region 102, and a part of the ReRAM peripheral circuit region 202 may be included. As shown in (f) of FIG. 8, it may be a region including all of the DRAM memory cell array region 101, all of the DRAM peripheral circuit region 102, and part of the ReRAM peripheral circuit region 202. Which of these positional relationships (the size and position of the ReRAM memory cell array region 201) is selected may be determined according to the storage capacity required for the ReRAM memory cell array region 201 and the connection relationship with peripheral circuits.

  Further, the ReRAM peripheral circuit region 202 may be on the first substrate 1 as long as it is peripheral to the DRAM memory cell array region 101, and not all locations are necessarily peripheral to the DRAM peripheral circuit region 102. For example, a part of the ReRAM peripheral circuit region 202 may be formed inside the DRAM peripheral circuit region 102.

  The present invention is a semiconductor memory device in which DRAM and ReRAM are mixedly mounted and a method for manufacturing the same, and is a memory that operates stably at high speed and has excellent low power consumption. Therefore, mobile electronic devices such as smartphones and tablet terminals are provided. It is particularly useful as a semiconductor memory device used for the above.

DESCRIPTION OF SYMBOLS 1 1st board | substrate 2 ReRAM peripheral circuit transistor 3 DRAM peripheral circuit transistor 4 DRAM memory cell transistor 5 1st contact plug 6 1st wiring (1st wiring layer)
7 2A Contact Plug 8 Capacitance Element 9 2B Contact Plug 10 2C Contact Plug 11 Second Wiring (Second Wiring Layer)
12 Second Substrate 13 ReRAM Memory Cell Transistor 14 3A Contact Plug 15 3B Contact Plug 16 Third Wiring (Third Wiring Layer)
17 4A Contact Plug 18 Resistance Change Element 19 4B Contact Plug 20 4C Contact Plug 21 Fourth Wiring (Fourth Wiring Layer)
22 Cross-point type memory cell of the first layer (resistance change element + current control element)
23 5A Contact plug 24 Second-layer cross-point type memory cell (resistance change element + current control element)
25 5C contact plug 26 5th wiring (5th wiring layer)
101 DRAM memory cell array region 102 DRAM peripheral circuit region 201 ReRAM memory cell array region 202 ReRAM peripheral circuit region 1000 Semiconductor memory device 2000 according to the first embodiment of the present invention Semiconductor memory device according to the second embodiment of the present invention

Claims (11)

A first substrate;
A DRAM memory cell array formed on the first substrate and having a plurality of capacitive elements, and a DRAM section including a DRAM peripheral circuit which is a peripheral circuit for the DRAM memory cell array;
A ReRAM memory cell array having a plurality of resistance change elements, and a ReRAM unit including a ReRAM peripheral circuit that is a peripheral circuit for the ReRAM memory cell array,
The ReRAM memory cell array is formed in an upper layer than the DRAM unit,
The DRAM peripheral circuit and the ReRAM peripheral circuit are formed in a region on the first substrate and in a peripheral region with respect to the DRAM memory cell array. The semiconductor memory device according to claim 1, wherein the ReRAM memory cell array is formed at least above the DRAM memory cell array. The semiconductor memory device according to claim 2, wherein the ReRAM memory cell array is formed above the DRAM memory cell array and above the DRAM peripheral circuit. 4. The semiconductor memory device according to claim 1, wherein the ReRAM peripheral circuit is a region on the first substrate and is formed in a peripheral region with respect to the DRAM peripheral circuit. 5. And a second substrate formed above the DRAM portion,
The semiconductor memory device according to claim 1, wherein the ReRAM memory cell array includes a plurality of memory cell transistors formed on the second substrate in addition to the plurality of resistance change elements. The semiconductor memory device according to claim 1, wherein the ReRAM memory cell array is a cross-point type memory cell array having a plurality of current control elements in addition to the plurality of resistance change elements. Furthermore, a first wiring layer, a second wiring layer, and a third wiring layer are provided above the first substrate in order from the one closer to the first substrate.
The first wiring layer and the second wiring layer are formed in the DRAM portion,
The semiconductor memory device according to claim 1, wherein the third wiring layer is a lowermost wiring layer of the ReRAM memory cell array.   A mobile terminal equipped with the semiconductor memory device according to claim 1. Forming a peripheral circuit transistor of the DRAM portion in a first region on the substrate;
Forming a memory cell transistor of a DRAM portion in a second region on the substrate;
Forming a peripheral circuit transistor of the ReRAM portion in a third region on the substrate;
Forming a peripheral circuit wiring of a DRAM portion above the first region;
Forming a capacitor and a wiring of a DRAM section above the second region;
Forming a memory cell and a wiring of the ReRAM unit above the second region and on the capacitor and wiring of the DRAM unit;
Forming a peripheral circuit wiring of a ReRAM portion above the third region. A method of manufacturing a semiconductor memory device. Forming the memory cell and the wiring of the ReRAM portion;
Forming a second substrate;
Forming a memory cell transistor of the ReRAM portion on the second substrate;
The method of manufacturing a semiconductor memory device according to claim 9, further comprising: forming a resistance change element of the ReRAM portion. The method of manufacturing a semiconductor memory device according to claim 9, wherein in the step of forming the memory cell and the wiring in the ReRAM portion, a memory cell including a resistance change element and a current control element is formed.

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