KR20140049405A - Liquid crystal display having seal pattern - Google Patents

Abstract

The present invention relates to a liquid crystal display device including a seal pattern. The disclosed configuration includes: a bottom substrate with an active region and a non-display region which includes a thin film transistor formed on the active region, and a top substrate with an active region and a non-display region which includes a color filter; a bottom polarizing plate and a top polarizing plate which are attached to the outer sides of the bottom substrate and the top substrate respectively; and a seal pattern which bonds the top substrate to the bottom substrate and is separated from the bottom polarizing plate and the top polarizing plate in the non-display region.

Description

Liquid crystal display device with seal pattern {LIQUID CRYSTAL DISPLAY HAVING SEAL PATTERN}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a seal pattern in which a warpage of a panel is improved by changing a seal pattern structure.

Recently, with the rapid development of the information society, the need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption has emerged. Among them, a liquid crystal display device has a resolution. It is excellent in color display and image quality, and is actively applied to notebooks, desktop monitors, and TVs.

In general, a liquid crystal display device arranges two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injects liquid crystal between the two substrates, and applies a voltage to the two electrodes to generate an electric field. By moving the liquid crystal molecules, the image is expressed by the transmittance of light that varies accordingly.

The main cause of light leakage, which has been raised as a problem in the liquid crystal display device, is that a polarizer contracts / expands due to environmental changes, and as a result, the shape of the panel is deformed into a cup or a cap. When the panel is deformed, external stress is transmitted to the inside of the panel due to interference of the backlight or the top case.

The stress transmitted in this way causes distortion of the liquid crystal layer inside the panel, and the optical axis of the polarizer and the liquid crystal layer is distorted in the black state, and is recognized as light leakage. That is, light leakage does not occur only by panel bending itself, but because it acts as a major factor of light leakage, the technology is developed to minimize the stress transmitted in the panel by changing the base material of the polarizing plate or keeping a distance from the external top case. However, the light leakage issue is continuously occurring.

In addition, a sealant is basically used for the purpose of maintaining cell gap with the inside of a panel, and maintaining adhesion of upper and lower glass.

A conventional liquid crystal display using the sealant will be described in detail with reference to FIGS. 1 to 4.

1 is a schematic plan view of a liquid crystal display device having a seal pattern according to the related art.

FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, and is a schematic cross-sectional view of a liquid crystal display device in which a seal pattern according to the prior art is disposed.

1 and 2, the liquid crystal display according to the related art includes a lower substrate 10 constituting a lower array substrate and an upper substrate 20 constituting an upper color filter substrate. Black matrices 21 and a seal pattern 40 are formed on the black matrix 21 on the periphery of the substrate 10 and the upper substrate 20, and the seal patterns between the two substrates 10 and 20 are formed. The liquid crystal layer 30 is injected into the 40.

The active area AA divided by the black matrix 21 of the edge is a pixel portion in which an image is displayed, and a plurality of gate wirings (not shown) and data wirings (not shown) intersect to define a pixel area. A thin film transistor (not shown) is positioned at the intersection of the wiring and the data wiring.

In addition, gates and data pads connected to the gate line and the data line are formed at the left and upper edges of the lower substrate 10, respectively, and are connected to the gate driving circuit and the data driving circuit, which are external circuits. Areas other than the active area AA form the non-display area NA.

 As shown in FIG. 2, the gate and the data link, and the area where the active area AA where the recall is represented and a pad (not shown) connected to a driving circuit for applying a signal to the active area AA are located. It is divided into a non-display area (NA) including a covering black matrix area.

In the active region AA, the gate electrode 11 is formed on the lower substrate 10, and the gate insulating layer 12 made of a silicon oxide film covers the gate electrode 11.

An active layer 13 made of amorphous silicon is formed on the gate insulating layer 12 on the gate electrode 11, and an ohmic contact layer 14 made of amorphous silicon doped with impurities is formed thereon.

The source electrode 15a and the drain electrode 15b made of a conductive material such as a metal are formed on the ohmic contact layer 14 together with the gate electrode 11 to form a thin film transistor T.

Although not shown, the gate electrode 11 is connected to the gate line, the source electrode 15a is connected to the data line, and the gate line and the data line are orthogonal to each other to define the pixel area.

A protective layer 16 is formed on the source electrode 15a and the drain electrode 15b, and the protective layer 16 has a contact hole 16a exposing the drain electrode 15b.

The pixel electrode 17 is formed in the pixel area above the passivation layer 16, and the pixel electrode 17 is connected to the drain electrode 15b through the contact hole 16a.

On the other hand, the lower substrate 10 is disposed on the transparent upper substrate 20 is spaced apart from the lower substrate 10 at a predetermined interval, the inner surface of the upper substrate 20 is a black matrix (Black Matrix) 21 is formed at a position corresponding to the thin film transistor T.

In addition, a black matrix 21a is formed in the non-display area NA of the upper substrate 20 so as to cover a link connecting the gate and the data pad. The color filter 22 is formed under the black matrix 21 in the active area AA. The color filter 22 sequentially repeats red, green, and blue colors, and one color is one pixel. Corresponds to the area. A common electrode 23 made of a transparent conductive material is formed under the color filter 22.

A liquid crystal is injected between the lower substrate 10 and the upper substrate 20 to form a liquid crystal layer 30.

Further, the lower polarizing plate 18 and the upper polarizing plate 28 are attached to the outer surfaces of the lower substrate 10 and the upper substrate 20, respectively.

Here, the gate insulating layer 12 and the protective layer 16 on the lower substrate 10 extend to the non-display area NA, and the liquid crystal injection is performed in the non-display area NA of the lower substrate 10. A seal pattern 40 which forms a gap and prevents leakage of the injected liquid crystal is formed.

The seal pattern 40 is formed to bond the lower substrate 10 and the upper substrate 20. The seal pattern 40 is positioned between the non-display areas NA of the entire liquid crystal panel so that the non-display It is formed on the black matrix area 21a surrounding the area NA and serves to bond the lower substrate 10 and the upper substrate 20. At this time, the seal pattern 40 is formed of a non-display area ( The seal pattern 40 is disposed at a position of the non-display area NA that overlaps and overlaps edge portions of the lower polarizing plate 18 and the upper polarizing plate 28.

However, the main cause of light leakage, which is one of the problems of liquid crystal displays, is caused by interference of the back light unit or the top case due to panel bending, or external stress inside the panel. Is transmitted, causing the optical axis of the liquid crystal to be distorted, and perceived as light leakage in the black state.

Thus, the warpage of the panel shrinks and expands due to the inflow or outflow of moisture of PVA according to the environmental change due to the nature of the polarizer, an essential material of the liquid crystal display, and causes the warpage of the panel attached to the polarizer and the adhesive. .

PVA is stretched at the time of fabrication of the polarizing plate to align iodine molecules in the stretching direction to exhibit polarization characteristics.

The polarizer produced through this manufacturing process causes shrinkage and expansion of the polarizer in the direction of absorption axis, which is the stretching axis due to environmental changes, and warpage of the panel, and the warpage causes stress of the panel in the liquid crystal display module (LCM) state. Will occur.

3 is a schematic diagram schematically illustrating a bending state of upper and lower polarizers disposed above and below a liquid crystal display device having a seal pattern according to the related art.

Looking at the in-plane stress distribution by the shrinkage in the panel 50 in the liquid crystal display according to the prior art, as shown in Figure 3, the upper polarizer 28 has an absorption axis of 0 degrees, the upper polarizer 28 The stress due to the contraction of the large shrinkage force is generated toward the center portion in the long side direction, the lower polarizing plate 18 has a form of a greater contraction force toward the center portion in the short side direction because the absorption axis is 90 degrees.

4 is a schematic diagram of the contracting force and the repulsive force of the polarizing plate according to the arrangement position of the seal pattern in the liquid crystal display device having a seal pattern according to the related art.

In the case of the liquid crystal display according to the related art, as shown in FIG. 4, the bending of the panel due to overlapping and overlapping ends of the seal pattern 40 and the ends of the upper and lower polarizers 28 and 18 are arranged. (M1) degree can be calculated | required by following formula (1).

M1 = f1x -f2y1 ----------------- (1)

Here, x is the distance from the center of the panel to the center of the contraction force of the polarizing plate, y1, y2 is the distance from the center of the panel to the end of the seal pattern, f1 is the contraction of the polarizing plate, and f2 represents the repulsion of the lower substrate of the thin film transistor.

In the case of the liquid crystal display according to the prior art, the product of the distance x from the center of the panel to the center of the contraction force of the polarizer and the contraction force of the polarizer f1 is the distance y1 from the center of the panel to the end of the seal pattern and the repulsive force of the thin film transistor array substrate. Since it is larger than the product of (f2), it can be said that the degree of warpage of the panel occurs by that much.

Therefore, the liquid crystal display according to the related art has a problem in that the distance from the seal pattern 40 varies depending on the position according to the contraction of the upper and lower polarizers 28 and 18, and the stress distribution in each part is different. have.

Accordingly, the present invention is to solve the problems of the prior art, an object of the present invention is to change the seal pattern structure in the panel to reduce the panel warp and thereby reduce the light leakage level of the liquid crystal display device having a In providing.

A liquid crystal display device having a seal pattern for achieving the above object comprises: a lower substrate having an active region and a non-display region, and a thin film transistor formed on the active region; An upper substrate on which a color filter is formed; A seal pattern bonded to the upper substrate and the lower substrate and disposed around the non-display area of the lower substrate, the seal pattern being formed closer to the edge of the lower substrate toward the center of the short side and the long side of the lower substrate; And a lower polarizing plate and an upper polarizing plate attached to an outer surface of the lower substrate and the upper substrate.

According to the liquid crystal display device having the seal pattern according to the present invention, the seal pattern disposed around the non-display area of the lower substrate is moved by a predetermined distance closer to the edge portion of the lower substrate toward the center of the short side and the long side of the lower substrate. By changing to the structure formed by moving, the panel warpage can be reduced, thereby minimizing interference with the backlight unit and the upper case to reduce light leakage.

1 is a schematic plan view of a liquid crystal display device having a seal pattern according to the related art.
FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, and is a schematic cross-sectional view of a liquid crystal display device in which a seal pattern according to the prior art is disposed.
3 is a schematic diagram schematically illustrating a bending state of upper and lower polarizers disposed above and below a liquid crystal display device having a seal pattern according to the related art.
4 is a schematic diagram of the contracting force and the repulsive force of the polarizing plate according to the arrangement position of the seal pattern in the liquid crystal display device having a seal pattern according to the related art.
5 is a schematic plan view of a liquid crystal display device having a seal pattern according to an exemplary embodiment of the present invention.
6 is a cross-sectional view taken along line VI-VI of FIG. 1, and is a schematic cross-sectional view of a liquid crystal display device having a seal pattern according to an exemplary embodiment of the present invention.
FIG. 7 is a schematic diagram illustrating a contraction force and a repulsion force of a polarizing plate according to an arrangement position of a seal pattern in a liquid crystal display device having a seal pattern according to an exemplary embodiment.
8 is a schematic plan view of a liquid crystal display device having a seal pattern according to another exemplary embodiment of the present invention.
9 is a cross-sectional view taken along line VII-VII of FIG. 8, and is a schematic cross-sectional view of a liquid crystal display device having a seal pattern according to another exemplary embodiment of the present invention.
10 is a schematic plan view of a liquid crystal display device having a seal pattern according to another exemplary embodiment of the present invention.
FIG. 11 is a graph comparing the degree of deflection of a polarizing plate when a changed seal pattern is attached to a liquid crystal display device having a seal pattern according to an exemplary embodiment of the present disclosure.

Hereinafter, a liquid crystal display device having a seal pattern according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5 is a schematic plan view of a liquid crystal display device having a seal pattern according to an exemplary embodiment of the present invention.

6 is a cross-sectional view taken along line VI-VI of FIG. 1, and is a schematic cross-sectional view of a liquid crystal display device having a seal pattern according to an exemplary embodiment of the present invention.

5 and 6, the liquid crystal display according to an exemplary embodiment of the present invention includes a lower substrate 110 constituting a lower array substrate (not shown) and an upper color filter substrate (not shown). The upper substrate 120 includes a black matrix 121a and a seal pattern 140 formed on the black matrix 121a on the outer sides of the two substrates 110 and 120. The liquid crystal layer 130 is injected into the seal pattern 140 between the 120.

The active area AA divided by the black matrix 121 of the edge is a pixel portion in which an image is displayed, and a plurality of gate lines (not shown) and data lines (not shown) intersect to define a pixel area. The thin film transistor T is positioned at the intersection of the gate line and the data line.

Although not shown in the drawings, gate pads (not shown) and data pads (not shown) connected to the gate line and the data line are formed on the left and upper outer edges of the array substrate 110, respectively. It is connected to the gate driving circuit and the data driving circuit. Areas other than the active area AA form the non-display area NA.

 As shown in FIG. 6, the gate and the data link, and the area where the active area AA where the recall is represented and a pad (not shown) connected to a driving circuit for applying a signal to the active area AA are located. It is divided into a non-display area (NA) including a covering black matrix area.

Here, the gate electrode 111 is formed on the lower array substrate 110 in the active region AA, and a gate insulating layer 112 made of a silicon oxide film covers the gate electrode 111 thereon.

At this time, the gate electrode 111 is aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), Cu alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy) , Gold (Au), Au alloy, Chromium (Cr), Titanium (Ti), Titanium alloy (Ti alloy), Moly tungsten (MoW), Molaritanium (MoTi), Copper / Mortinium (Cu / MoTi It may also comprise at least any one selected from the group of conductive metals, or a combination of two or more thereof, or other suitable material.

In addition, the gate insulating layer 112 may be formed of a silicon (Si) -based oxide film, a nitride film, or a compound including the same, a metal oxide film including an Al ₂ O ₃ , an organic insulating film, and a low dielectric constant (low-k). ) Material having a value of. For example, the gate insulating film 107 may be silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), or tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) Or combinations of two or more thereof or other suitable materials.

An active layer 113 made of amorphous silicon is formed on the gate insulating layer 112 on the gate electrode 111, and an ohmic contact layer 114 made of amorphous silicon doped with impurities is formed thereon. .

In this case, the active layer 113 is a layer for forming a channel through which electrons move between the source electrode 115a and the drain electrode 115b, and is referred to as low temperature polysilicon (LTPS) or amorphous. Silicon (a-Si) or silicon (Si) -based semiconductor films, IGZO-based oxide semiconductor films, compound semiconductors, carbon nanotubes, and graphene may also be used.

In addition, the ohmic contact layer 114 may be used as an amorphous silicon doped with an impurity or a silicon (Si) based semiconductor film doped with an impurity.

The source electrode 115a and the drain electrode 115b formed on the ohmic contact layer 114 and made of a conductive material such as a metal form the thin film transistor T together with the gate electrode 111. In this case, as a material for forming the source electrode 115a and the drain electrode 115b, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), Cu alloy, molybdenum (Mo) , Silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenum (MoTi), at least one selected from the group of conductive metals including copper / mortitanium (Cu / MoTi), or a combination of two or more thereof, or other suitable materials.

Although not illustrated, the gate electrode 111 is connected to the gate line, the source electrode 115a is connected to the data line, and the gate line and the data line are orthogonal to each other to define the pixel area.

A protective layer 116 is formed on the source electrode 115a and the drain electrode 115b, and the protective layer 116 has a contact hole 116a exposing the drain electrode 115b. In this case, the protective layer 116 is formed of a silicon nitride film, a silicon oxide film or an organic material.

In addition, a pixel electrode 117 is formed in the pixel area above the passivation layer 116, and the pixel electrode 117 is connected to the drain electrode 115b through a contact hole 116a.

Meanwhile, an upper substrate 120 constituting the color filter substrate is spaced apart from the lower substrate 110 at a predetermined interval on the lower substrate 110, and is disposed on an inner surface of the upper substrate 120. A black matrix 121 is formed at a position corresponding to the thin film transistor T.

In addition, a black matrix 121a is formed in the non-display area NA of the upper substrate 120 so as to cover a link connecting the gate and the data pad. The color filter 122 is formed under the black matrix 121 in the active area AA. The color filter 122 sequentially repeats red, green, and blue colors, and one color is one pixel. Corresponds to the area. A common electrode 123 made of a transparent conductive material, for example, ITO or IZO, is formed under the color filter 122. In this case, the common electrode 123 may be formed on the lower substrate 110 instead of the upper substrate 120 according to the driving method of the liquid crystal display.

A liquid crystal is injected between the lower substrate 110 and the upper substrates 110 and 120 to form the liquid crystal layer 130.

In addition, the lower polarizing plate 118 and the upper polarizing plate 128 are attached to the outer surfaces of the lower substrate 110 and the upper substrate 120, respectively.

Here, the gate insulating layer 112 and the protective layer 116 on the lower substrate 110 extend to the non-display area NA, and the non-display area between the lower substrate 110 and the upper substrate 120 ( Between the NA), a gap for forming the liquid crystal is formed, and a seal pattern 140 is formed to prevent leakage of the injected liquid crystal. The material of the seal pattern 140 includes all seal materials for the purpose of bonding the lower substrate 110 and the upper substrate 120 irrespective of thermosetting and photocurability.

In this case, the seal pattern 140 is formed to bond the array substrate 110 and the color filter substrate 120. The seal pattern 140 is positioned in the non-display area NA of the entire liquid crystal panel. It is formed on the black matrix area 121a surrounding the non-display area NA to serve to bond the lower substrate 110 and the upper substrate 120.

The seal pattern 140 is disposed in an octagonal shape around the non-display area NA of the lower substrate 110 and the upper substrate 120. The seal pattern 140 has a long side (eg, a long side) of the lower substrate 110. 110a) and toward the center of the short side (110b) is closer to the edge of the lower substrate 110 has a constant distance (d1), for example, a structure that is moved toward the outer portion about 0.5 to 3 mm. That is, the separation distance d1 between the seal pattern 140 and the polarizing plates 118 and 128 is formed farther toward the central portion of the long side 110a and the short side 110b of the lower substrate 110. This means that a predetermined angle is maintained at the central portion of the seal pattern 140 corresponding to the central portion of the long side 110a and the short side 110b of the lower substrate 110.

In some cases, the separation distance d1 of the seal pattern 140 is formed to be farther from the polarizing plates 118 and 128 toward one of the long sides 110a or the central portion of the short sides 110b, or two long sides 110a. ) Toward the central portion of one long side and the central portion of one short side 110b of the two short sides 110b may be formed farther from the polarizing plates 118 and 128.

FIG. 7 is a schematic diagram illustrating a contraction force and a repulsion force of a polarizing plate according to an arrangement position of a seal pattern in a liquid crystal display device having a seal pattern according to an exemplary embodiment.

In the case of the liquid crystal display according to the exemplary embodiment of the present invention, as shown in FIG. 7, the seal pattern 140 is disposed at a position not overlapped with the ends of the upper and lower polarizers 128 and 118, in this case. The degree of warpage (M1) of the panel shown in can be obtained by the following equation (2).

M1 = f1x -f2y1 ----------------- (2)

Here, x is the distance from the center of the panel to the center of the contraction force of the polarizing plate, y1, y2 is the distance from the center of the panel to the end of the seal pattern, f1 is the contraction of the polarizing plate, and f2 represents the repulsion of the lower substrate of the thin film transistor.

In the case of the liquid crystal display according to an exemplary embodiment of the present invention, the product of the distance x from the center of the panel to the center of the contraction force of the polarizer and the contraction force of the polarizer f1 is the distance y1 from the center of the panel to the end of the seal pattern and the thin film transistor. Since the repulsive force f2 of the array substrate is smaller than the product, it can be said that the degree of warpage of the panel is smaller. That is, the position of the center portion of the seal pattern 140 is moved to be closer to the outer side of the panel than the conventional one, so that the distance y2 from the panel center portion to the end of the seal pattern is longer than that of the conventional case (that is, y1). As a result, the degree of warpage of the panel is small.

In particular, in the case of the present invention, the region of the seal pattern may be designed as far as possible from the ends of the polarizing plates 118 and 128 to increase the repulsive force of the moment generated when the polarizing plate shrinks, thereby reducing the panel warpage.

Accordingly, in the liquid crystal display device having the seal pattern according to the exemplary embodiment, the seal pattern disposed at the circumference of the non-display area of the lower substrate is formed at the edge portion of the lower substrate toward the center of the short side and the long side of the lower substrate. By changing to a structure formed by moving a predetermined distance closer to each other, it is possible to reduce panel warpage, thereby minimizing interference with the backlight unit and the upper case to reduce light leakage.

Meanwhile, a liquid crystal display device having a seal pattern according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 and 9.

8 is a schematic plan view of a liquid crystal display device having a seal pattern according to another exemplary embodiment of the present invention.

9 is a cross-sectional view taken along line VII-VII of FIG. 8, and is a schematic cross-sectional view of a liquid crystal display device having a seal pattern according to another exemplary embodiment of the present invention.

According to another exemplary embodiment of the present invention, as shown in FIGS. 8 and 9, the liquid crystal display includes a lower substrate 210 constituting a lower array substrate (not shown) and a color filter substrate (not shown). The upper substrate 220 includes a black matrix 221a and a seal pattern 240 formed on the black matrix 221a on the outer sides of the two substrates 210 and 220. The liquid crystal layer 230 is injected into the seal pattern 240 between the 220.

The active area AA divided by the black matrix 221 of the edge is a pixel portion in which an image is displayed, and a plurality of gate lines (not shown) and data lines (not shown) intersect to define a pixel area. The thin film transistor T is positioned at the intersection of the gate line and the data line.

Although not shown in the drawing, gate pads (not shown) and data pads (not shown) connected to the gate line and the data line are formed at the left and upper outer edges of the array substrate 210, respectively. It is connected to the gate driving circuit and the data driving circuit. Areas other than the active area AA form the non-display area NA.

 As shown in FIG. 9, the gate and the data link, the area where the active area AA where the recall is represented and the pad (not shown) connected to the driving circuit for applying a signal to the active area AA, are located. It is divided into a non-display area (NA) including a covering black matrix area.

The gate electrode 211 is formed on the lower substrate 210 in the active region AA, and a gate insulating film 212 made of a silicon oxide film covers the gate electrode 211.

In this case, the gate electrode 211 is made of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), Cu alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy) , Gold (Au), Au alloy, Chromium (Cr), Titanium (Ti), Titanium alloy (Ti alloy), Moly tungsten (MoW), Molaritanium (MoTi), Copper / Mortinium (Cu / MoTi It may also comprise at least any one selected from the group of conductive metals, or a combination of two or more thereof, or other suitable material.

In addition, the gate insulating film 212 may be formed of a silicon (Si) based oxide film, a nitride film, or a compound including the same, a metal oxide film including an Al ₂ O ₃ , an organic insulating film, and a low dielectric constant (low-k). ) Material having a value of. For example, the gate insulating film 107 may be silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), or tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) Or combinations of two or more thereof or other suitable materials.

An active layer 213 made of amorphous silicon is formed on the gate insulating layer 212 on the gate electrode 211, and an ohmic contact layer 214 made of amorphous silicon doped with impurities is formed thereon. .

In this case, the active layer 213 is a layer for forming a channel through which electrons move between the source electrode 215a and the drain electrode 215b. Low temperature polysilicon (hereinafter referred to as LTPS) or amorphous Silicon (a-Si) or silicon (Si) -based semiconductor films, IGZO-based oxide semiconductor films, compound semiconductors, carbon nanotubes, and graphene may also be used.

In addition, the ohmic contact layer 214 may be used as an amorphous silicon doped with an impurity or a silicon (Si) based semiconductor film doped with an impurity.

The source electrode 215a and the drain electrode 215b formed on the ohmic contact layer 214 and made of a conductive material such as a metal form the thin film transistor T together with the gate electrode 11. At this time, as a material for forming the source electrode 215a and the drain electrode 215b, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), Cu alloy, molybdenum (Mo) , Silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenum (MoTi), at least one selected from the group of conductive metals including copper / mortitanium (Cu / MoTi), or a combination of two or more thereof, or other suitable materials.

Although not shown in the drawing, the gate electrode 211 is connected to the gate line, the source electrode 215a is connected to the data line, and the gate line and the data line are orthogonal to each other to define the pixel area.

A passivation layer 216 is formed on the source electrode 215a and the drain electrode 215b, and the passivation layer 216 has a contact hole 216a exposing the drain electrode 215b. In this case, the protective layer 216 is formed of a silicon nitride film, a silicon oxide film, or an organic material.

In addition, a pixel electrode 217 is formed in the pixel area above the passivation layer 216, and the pixel electrode 217 is connected to the drain electrode 215b through a contact hole 216a.

Meanwhile, an upper substrate 220 constituting the color filter substrate is spaced apart from the lower substrate 210 at a predetermined interval on the lower substrate 210, and is disposed on an inner surface of the upper substrate 220. A black matrix 121 is formed at a position corresponding to the thin film transistor T.

In addition, a black matrix 221a is formed in the non-display area NA of the upper substrate 220 so as to cover a link connecting the gate and the data pad. A color filter 222 is formed under the black matrix 221 in the active area AA. The color filter 222 sequentially repeats red, green, and blue colors, and one color is one pixel. Corresponds to the area. A common electrode 223 made of a transparent conductive material, for example, ITO or IZO, is formed under the color filter 222. In this case, the common electrode 223 may be formed on the lower substrate 210 instead of the upper substrate 220 according to the driving method of the liquid crystal display.

A liquid crystal is injected between the lower substrate 210 and the upper substrates 210 and 220 to form a liquid crystal layer 230.

In addition, the lower polarizing plate 218 and the upper polarizing plate 228 are attached to the outer surfaces of the lower substrate 210 and the upper substrate 220, respectively.

Here, the gate insulating layer 212 and the protective layer 216 on the lower substrate 210 extend to the non-display area NA, and the non-display area between the lower substrate 210 and the upper substrate 220 is formed. NA) forms a gap for liquid crystal injection, and double first and second seal patterns 240 and 241 are formed to prevent leakage of the injected liquid crystal. The materials of the first and second seal patterns 240 and 241 include all seal materials aimed at bonding the lower substrate 210 and the upper substrate 220 regardless of thermosetting and photocurability.

In this case, the double first and second seal patterns 240 and 241 are formed to bond the lower substrate 210 and the upper substrate 220. The seal pattern 240 is a non-display area of the entire liquid crystal panel. The lower substrate 210 and the upper substrate 220 are formed on the black matrix 221a which is positioned at the NA and surrounds the non-display area NA. An interval d3 between the dual first and second seal patterns 240 and 241 may be maintained in a range of about 10 μm or more.

The double first and second seal patterns 240 and 241 are arranged in an octagonal shape around the non-display area NA of the lower substrate 210 and the upper substrate 220. 240 and 241 are a constant separation distance d2 closer to the edge of the lower substrate 210 toward the center of the long side 210a and the short side 210b of the lower substrate 210, for example, about 0.5 to 3 mm. It is composed of a structure moved to the outer part. That is, the separation distance d2 between the double first and second seal patterns 240 and 241 and the polarizers 218 and 228 is farther toward the center of the long side 210a and the short side 210b of the lower substrate 210. Form. This means that a predetermined angle is maintained at the central portion of the first and second seal patterns 240 and 241 corresponding to the central portion of the long side 210a and the short side 210b of the lower substrate 210.

In some cases, the separation distance d2 between the polarizers 218 and 228 and the first and second seal patterns 240 may be toward the central portion of the long side 210a or the short side 210b. ), Or may be formed farther from the polarizers 218 and 228 toward the central portion of one of the two long sides 210a and toward the central portion of one short side of the two short sides 210b. That is, the distance from the center of the panel to the end of the seal pattern is formed by moving the center of the double first and second seal patterns 240 and 241 by a predetermined distance de2 so as to be closer to the outer side of the panel than before. Is longer than that of the conventional case (ie, y1), and thus, the degree of warpage of the panel is small.

Therefore, the liquid crystal display device having the seal pattern according to another embodiment of the present invention, the double first, second seal pattern disposed around the non-display area of the lower substrate toward the center of the short side and long side of the lower substrate By changing to a structure formed by moving a predetermined distance away from the edge of the lower substrate or far from the polarizing plate, the panel warpage is reduced, thereby minimizing interference with the backlight unit and the upper case to reduce light leakage.

On the other hand, the liquid crystal display device with a seal pattern according to another embodiment of the present invention will be described with reference to FIG.

10 is a schematic plan view of a liquid crystal display device having a seal pattern according to another exemplary embodiment of the present invention.

Since components of the liquid crystal display according to another exemplary embodiment of the present invention are the same as those of the exemplary embodiment of the present invention, descriptions of these components will be omitted.

As shown in FIG. 10, a liquid crystal is injected between the lower substrate 310 and the upper substrate (not shown) to form a liquid crystal layer (not shown).

The lower polarizing plate 318 and the upper polarizing plate (not shown) are respectively attached to the outer surfaces of the lower substrate 310 and the upper substrate (not shown).

In the non-display area NA between the lower substrate 310 and the upper substrate 320, a gap for forming liquid crystal is formed, and a seal pattern 340 is formed to prevent leakage of the injected liquid crystal. have. The material of the seal pattern 340 includes all seal materials for the purpose of bonding the lower substrate 310 and the upper substrate (not shown) irrespective of thermosetting and photocurability.

In this case, the seal pattern 340 is formed to bond the lower substrate 310 and the upper substrate (not shown). The seal pattern 340 is positioned in the non-display area NA of the entire liquid crystal panel. It is formed on a black matrix (not shown) surrounding the non-display area NA to serve to bond the lower substrate 310 and the upper substrate 320.

The seal pattern 340 is disposed in the shape of a rectangle around the lower substrate 310 and the non-display area NA of the upper substrate (not shown), and the seal pattern 340 is formed on the bottom of the lower substrate 310. It is located on the outskirts. That is, the seal pattern 340 is formed in a structure disposed at the outermost part of the lower substrate 310 as far as possible from the lower polarizing plate 318 and the upper polarizing plate (not shown). In this case, the distance d4 between the lower polarizing plate 318 and the upper polarizing plate (not shown) and the seal pattern 340 is preferably maintained at about 0.5 to 3 mm.

Accordingly, the liquid crystal display device having the seal pattern according to another exemplary embodiment of the present invention may be configured by changing the seal pattern disposed around the non-display area of the lower substrate to a structure formed by moving the seal pattern at a predetermined distance as far as possible from the polarizing plate. In addition, light leakage can be reduced by reducing panel warpage and thereby minimizing interference with the backlight unit and the upper case.

FIG. 11 is a graph comparing the degree of deflection of a polarizing plate when a changed seal pattern is attached to a liquid crystal display device having a seal pattern according to an exemplary embodiment of the present disclosure.

In the case of a liquid crystal display device having a seal pattern according to an exemplary embodiment of the present invention, as shown in FIG. 11, the seal pattern disposed around the non-display area of the lower substrate is maximized from the polarizer toward the center of the lower substrate. It can be seen that by changing the structure formed by moving far apart by a certain distance, the amount of adhesion displacement of the polarizing plate, that is, the degree of warpage of the polarizing plate is smaller than in the prior art.

As described above, according to the liquid crystal display device having the seal pattern according to the present invention, the seal pattern or the double seal pattern disposed around the non-display area of the lower substrate is gradually lowered toward the center of the short side and the long side of the lower substrate. By changing to a structure formed by moving a predetermined distance to the edge of the substrate or a structure formed by moving a predetermined distance away from the polarizer as much as possible, panel warpage is reduced, thereby reducing interference with the backlight unit and the upper case. By minimizing light leakage.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, those of ordinary skill in the art to which the present invention pertains will be able to vary the components of the thin film transistor of the present invention, the structure may also be modified in various forms.

It will be appreciated that the oxide thin film transistor of the present invention can be applied not only to liquid crystal display devices and organic light emitting display devices but also to memory devices and logic devices. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

110: lower substrate 111: gate electrode
112: gate insulating film 113: active layer
114: ohmic contact layer 115a: source electrode 115b: drain electrode 116: protective layer
116a: contact hole 117: pixel electrode

Claims (7)

An upper substrate having an active region and a non-display region, a lower substrate on which a thin film transistor is formed and an upper substrate on which a color filter is formed;
A lower polarizing plate and an upper polarizing plate attached to outer surfaces of the lower substrate and the upper substrate;
And a seal pattern bonded to the upper substrate and the lower substrate and spaced apart from the lower polarizing plate and the upper polarizing plate in the non-display area. The method of claim 1, wherein the seal pattern has a farther distance from the lower polarizer and the upper polarizer toward the center of the long side and the short side of the lower substrate or the upper substrate, or toward the center of one of the long sides and one of the short sides. The liquid crystal display device having a seal pattern, wherein the seal pattern has a distance from the lower polarizer plate and the upper polarizer plate. The liquid crystal display device with a seal pattern according to claim 1, wherein the separation distance is 0.5 to 3 mm. The liquid crystal display device of claim 1, wherein the seal pattern has an octagonal structure that maintains a predetermined angle at a portion corresponding to a central portion of a long side and a short side of a lower substrate or an upper substrate. The liquid crystal display device of claim 1, wherein the seal pattern comprises dual seal patterns. The liquid crystal display device of claim 5, wherein the separation distance between the dual seal patterns is 10 μm or more. The liquid crystal display device of claim 1, wherein the seal pattern is disposed at an outermost portion of the non-display area that is not overlapped with the lower polarizing plate and the upper polarizing plate.

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