KR20140048505A - Semiconductor having capacitor using line type double pattern and method for manufacturing same - Google Patents

Abstract

Included are a semiconductor substrate having an electric device; a lower support layer of a capacitor electrode; a lower electrode of a capacitor storage node; and an upper support layer of the capacitor electrode. A transistor and a bit line are buried in the semiconductor substrate having an electric device. The lower support layer of the capacitor electrode and an etch preventing layer on the semiconductor substrate together surround the lower part of the capacitor electrode. The upper support layer of the capacitor electrode is formed in the shape of a mesh and connected to the upper part of the capacitor electrode.

Description

Semiconductor and semiconductor manufacturing method with capacitor using line type double pattern {SEMICONDUCTOR HAVING CAPACITOR USING LINE TYPE DOUBLE PATTERN AND METHOD FOR MANUFACTURING SAME}

The present invention relates to a DRAM semiconductor having a capacitor made using a line-type double pattern and a semiconductor manufacturing method for manufacturing the same. More specifically, a capacitor having a stable and good capacity by dividing the photo and etching processes in two steps The present invention relates to a DRAM semiconductor having a semiconductor and a semiconductor manufacturing method for manufacturing the DRAM semiconductor.

In general, as the design rules become smaller, the contact photographing process becomes increasingly difficult. When etching with a smaller capacitor electrode hole size, the etching rate is smaller, and a DRAM capacitor having a desired shape and capacity cannot be obtained. In order to solve this problem, a DRAM semiconductor is manufactured by performing a capacitor process using a line type double pattern when manufacturing a semiconductor capacitor.

The semiconductor capacitor generally includes a semiconductor substrate, a lower support layer disposed on the semiconductor substrate, a capacitor upper and lower electrodes, and an upper support layer. The upper support layer connects and supports the semiconductor capacitor like a net. The lower support film of the semiconductor substrate supports the capacitor at the bottom to prevent collapse and to distribute stress to improve the electrical characteristics of the device.

The semiconductor capacitor having such a general structure is exposed to the limitations of the photolithography process and the etching process when the single pattern is used due to the reduction of the design rule, and thus there is a problem in that a DRAM semiconductor having a capacitor having good electrical characteristics cannot be manufactured.

The present invention provides a DRAM semiconductor device having a large capacitance and a stable capacitor per unit area.

The present invention also provides a method of making a DRAM semiconductor device having the capacitor described above.

According to an aspect of the present disclosure, a DRAM semiconductor device may include a semiconductor substrate on which an electrical device is formed, a lower support layer, a capacitor lower electrode, and an upper support layer. The semiconductor substrate on which the electric element is formed is formed by embedding transistors, bit lines, and capacitor pads. The lower support layer is formed to surround the lower portion of the capacitor electrode together with the etch stop layer on the semiconductor substrate. The upper support layer is formed by being connected in a net form on top of the capacitor electrode to support the capacitor electrodes.

According to an embodiment of the invention, the semiconductor capacitor is a DRAM or a mobile DRAM semiconductor device.

According to another aspect of the present invention, a method of manufacturing a semiconductor capacitor includes forming an etch stop layer on a semiconductor substrate on which transistor electrodes, bit lines, and capacitor pads are formed, forming a first mold layer on the etch stop layer, and forming a line type pattern first mask. A first opening hole is formed through a first photo and a first etching process using a second film, a second mold layer is formed in the first opening hole space, and a second photo and second etching process using a line type pattern second mask. Forming a second opening hole, forming sidewalls of the first and second opening holes, forming a sacrificial layer in the second opening hole, and removing the first mold layer using the sacrificial layer and the second mold layer. A hole is formed, and the sacrificial layer is removed to form a capacitor storage node hole, and a capacitor is formed in the capacitor storage node hole. Forming a lower electrode forming a storage node, and stop supporting the upper part of the storage bottom electrode and the top side, to form a film support lower to partially remove the first molded layer.

According to an embodiment of the present invention, when the first mold film is formed of an oxide film, the second mold film may be formed of a polysilicon film.

According to an embodiment of the present invention, the capacitor storage node lower electrode may be formed of a TiN metal compound.

According to the embodiment of the present invention, after the lower support layer is formed, the capacitor general process and the passivation layer process may be further performed.

According to an embodiment of the present invention, the semiconductor capacitor may proceed to a DRAM or mobile DRAM semiconductor device formation process.

According to the present invention as described above, a DRAM semiconductor device can be obtained by forming a capacitor having a good capacity and a stable capacitor in a process of decreasing the design rule using a line type double pattern.

In addition, the upper and lower support layers of the capacitor electrode may be obtained, thereby preventing the capacitor electrode from falling down and dispersing stress, thereby obtaining a DRAM semiconductor device having good electrical characteristics.

1 is a layout plan view of a DRAM semiconductor device forming a storage electrode in a line type pattern according to an embodiment of the present invention.
2 is a three-dimensional view of a DRAM semiconductor device having a storage electrode according to an embodiment of the present invention.
3 to 14 are cross-sectional views sequentially illustrating a method of manufacturing a DRAM semiconductor device having a storage electrode along a cutting direction A, C, B, and D of FIG. 1.
15 is a complete stereoscopic view of a DRAM semiconductor device having a storage electrode according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

1 is a layout plan view of a DRAM semiconductor device forming a storage node electrode in a line type pattern according to an exemplary embodiment of the present invention.

Referring to FIG. 1, when forming a plurality of storage nodes 135 on a semiconductor substrate 100, a line type pattern mask M is used. At this time, each of the A, B, C, and D directions represents a cut surface.

2 is a three-dimensional view of a DRAM semiconductor device having a storage electrode according to an embodiment of the present invention.

Referring to FIG. 2, a plurality of capacitor storage nodes 135 are formed on a semiconductor substrate (not shown), and the lower support layer 113 and the capacitor storage node 135 are disposed below the capacitor storage node 135. The upper support membrane 145 is formed in a net shape on the top. The structure having the support layers on the upper and lower portions of the capacitor storage node 135 as described above can provide a semiconductor DRAM device having good electrical characteristics by preventing the capacitor electrode from falling down and being uniformly distributed with stress.

3 to 14 are cross-sectional views sequentially illustrating a method of manufacturing a DRAM semiconductor device having a capacitor storage electrode along a direction A, C, B, and D cut in FIG. 1.

Referring to FIG. 3, the A, C, B, and D directions in the drawings represent cross sections which appear when cut in the A, C, B, and D directions in FIG. 1. The semiconductor substrate 100 is not shown, but a plurality of gate structures are formed. In addition, although not shown, structures, such as bit lines and capacitor pads, which should be basically provided in DRAM semiconductor devices are formed. The etch stop layer 105 is formed of a nitride film on the semiconductor substrate 100 in a state where such a structure is completed, and the first mold layer 110 is formed.

The first mold layer 110 is an oxide layer, the thickness of which is 10000 ?? to match the capacitor value required by the device. To 20000 ?? Form a value between. After forming a line type first mask (not shown) on the first mold layer 110, a first opening 111 is formed through an etching process. In this case, line-type openings are formed in the A direction and the B direction, and the first mold layer 110 is not etched in the C direction, and the first mold layer 110 is etched away in the entire D direction.

Referring to FIG. 4, the first opening 111 on the semiconductor substrate 100 is filled with the second mold layer 115 and planarized. The second mold layer 115 is formed of a material having an etching ratio different from that of the first mold layer 110. Usually, it is formed of a polysilicon film. As described above, the present invention has the characteristics of a process in which an etching and a thin film process are subsequently performed when there is one photo process.

Referring to FIG. 5, after forming the second mold layer 115, a second opening hole 118 is formed using a line type pattern second mask (not shown). At this time, due to the difference in the etch rate between the first mold film 110 and the second mold film 115, a slightly etched hole is formed in the upper part of the C-direction cut surface, and the second mold film in the B and D directions is up to the etch stop layer 105. After etching, the second mold layer pillar 120 is formed in the D direction.

6 and 7, a sidewall 125 is formed on the opened first opening hole and the second opening hole, and a sacrificial layer 130 is formed in the hole. The sacrificial layer 130 is filled with a material having a significant etching ratio with the first mold layer 110 and the second mold layer pillar 120. It is usually filled with sodium sodium (TiN) or other metal compounds.

As mentioned in the process using the line type pattern first mask, the line type mask in forming the capacitor electrode hole as in the etching and sacrificial layer 130 is formed after the photo process using the line type pattern second mask (not shown). It is characterized by using two photographic, etching and thin film processes.

8 and 9, the first mold layer 110 is selectively etched using the second mold mall 115, the sidewalls 125, and the sacrificial layer 130 as a mask, and the sacrificial layer 130 is formed. ). Then, the capacitor storage node holes 133 are formed in all directions on the semiconductor substrate 100.

When the capacitor storage node hole 133 is formed by using the photo process using two line type pattern masks and the process of deforming and etching two thin films as described above, the margin of the photo process is increased even in a device process having a very small design rule. The storage node hole 133 may be formed to secure the desired etch rate and obtain a desired capacity.

10 and 11, the etch stop layer 105 in the storage node hole 133 formed by using the first and second opening holes on the semiconductor substrate 100 is removed, and the capacitor storage node lower electrode 135 is removed. ). The capacitor lower electrode 135 uses a metal compound having good conductivity such as sodium nitrate (TiN). After forming the lower electrode of the capacitor, the upper side of the first mold 110 and the second mold 120 are partially etched to form the upper support layer hole 140.

12 and 13, an upper support layer 145 is formed on an upper sidewall of the capacitor storage node lower electrode 135. The upper support layer 145 is formed in the form of a mesh (mesh) in the form of sidewalls depot nitride. Then, the capacitor storage node lower electrode 135 is all stably connected by the upper support layer 145, thereby dispersing stress and preventing the electrode from falling down.

The first mold layer 110 used to form the capacitor storage node lower electrode 135 is partially etched to form the capacitor storage node electrode lower support layer 113. The capacitor storage node lower electrode lower support layer 113 is formed on the lower sidewall of the capacitor lower electrode 135 to stably support the lower part of the electrode to prevent the electrode from collapsing and to relieve stress to improve the electrical characteristics of the DRAM semiconductor device. do.

Referring to FIG. 14, the second mold layer 120 formed on the semiconductor substrate 100 is removed by a lift-off method. At this time, the side wall 125 formed on the side surface of the capacitor lower electrode 135 is also removed.

 15 is a complete stereoscopic view of a DRAM semiconductor device having a storage electrode according to an embodiment of the present invention.

Referring to FIG. 15, an etch stop layer 105 is formed on the semiconductor substrate 100, and the capacitor storage node lower electrode 135 is supported by the capacitor storage electrode lower support layer 113 to support the lower surface of the capacitor storage electrode. The upper portion of the storage node electrode is supported by the upper support layer 145. Because the capacitor process is performed in a line pattern, the electrode model is a rectangular pillar.

When the capacitor is formed through two photolithography and thin film etching processes using the line pattern as in the embodiment of the present invention, the line type is applied even if the margin of the photolithography process is secured and the etching rate is reduced according to the area in the process of decreasing the design rule. Therefore, it is possible to easily form a capacitor by solving the etch rate problem, it is possible to form a semiconductor capacitor having a good capacity and stable structure.

In addition, since a support layer may be formed on the upper and lower portions of the capacitor electrode, a semiconductor DRAM device having good electrical characteristics without stress distribution and falling down can be obtained.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims. It can be understood that it is possible.

100; Semiconductor substrate 105; Etch barrier
110; First mold film 113; Lower support membrane
115, 120; Second mold film 125; Side wall
130; Sacrificial layer 135; Capacitor Storage Node Bottom Electrode
145; Upper support membrane

Claims (10)

A semiconductor substrate on which transistor electrodes, bit lines, and capacitor pads are formed;
A plurality of capacitor storage node lower electrodes in contact with the semiconductor substrate and partially contacting an etch stop layer formed on the semiconductor substrate at a lower side thereof and having a rectangular pillar shape;
A capacitor storage node electrode lower support layer formed in contact with the etch stop layer and surrounding a lower portion of the capacitor storage node lower electrode; And
And a top support layer formed on top of the plurality of capacitor storage nodes to connect and support the plurality of electrodes in a rectangular mesh structure. The DRAM semiconductor device of claim 1, wherein the etch stop layer is a nitride layer. The DRAM semiconductor device of claim 1, wherein the capacitor storage node electrode is a sodium titanate metal compound. The DRAM semiconductor device of claim 1, wherein the capacitor electrode upper support layer is formed of a nitride layer. The semiconductor DRAM device of claim 1, wherein the capacitor electrode lower support layer is an oxide layer. Forming transistor electrodes, bit lines, and capacitor pads in the semiconductor substrate;
Forming an etch stop layer on the semiconductor substrate;
Forming a first opening hole with a line type first mask after forming a first mold layer on the etch stop layer;
Forming a second opening hole using a line type second mask after forming a second mold layer on the first opening hole and the etch stop layer;
Forming a sacrificial layer after forming sidewall spacers on sidewalls of the first mold layer;
Removing the first mold layer by using the sacrificial layer and the second mold layer pattern;
Forming a capacitor storage node electrode in the capacitor storage node electrode hole formed by removing the first mold layer and the sacrificial layer;
Forming a mesh upper support layer at a portion in contact with an upper portion of the capacitor storage node;
Partially removing the remaining first mold layer to form a lower support layer; And
And removing the second mold layer and sidewall spacers to form a DRAM semiconductor device having a plurality of storage nodes. The method of claim 6, further comprising removing a portion of the mold layer before forming the upper support layer. The method of claim 6, wherein the capacitor storage node electrode is formed by a process using sodium titanate (TiN). The method of claim 6, wherein the upper support layer is formed of a nitride film. The method of claim 6, wherein the mold film removing process includes a lift-off method.

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