KR20140042575A - Oxide thin film transistor, method for fabricating tft, array substrate having tft and method for fabricating the same - Google Patents

Abstract

The present invention relates to an oxide thin film transistor, a fabricating method, and an array substrate for a display device and a fabricating method thereof. The disclosed invention includes a gate electrode formed on a substrate; a gate insulating layer which is formed on the entire surface of the substrate including the gate electrode; an active pattern which is formed on the gate insulating layer of the upper part of the gate electrode; an etch stop layer pattern which is formed on the active pattern; a source electrode and a drain electrode which are formed on the active pattern and separated from each other; a passivation layer which is formed on the entire surface of the substrate including the source electrode and the drain electrode; and a light shield pattern which is formed on the passivation layer of the upper side of the active pattern. [Reference numerals] (AA) Light

Description

OXIDE THIN FILM TRANSISTOR, METHOD FOR FABRICATING TFT, ARRAY SUBSTRATE HAVING TFT AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a thin film transistor, and more particularly, to an oxide thin film transistor, a manufacturing method, an array substrate having the same, and a manufacturing method thereof.

The largest application in the rapidly growing flat panel display market is TV (Television) products. Currently, liquid crystal displays (LCDs) are mainly used as TV panels, and organic light emitting displays are also being researched for application to TVs.

The focus of current display technology for TVs is on the market's major demands.The market demands large TV or Digital Information Display (DID), low cost, high definition (video expression power, high resolution, brightness, contrast ratio). , New reappearance).

In order to meet such requirements, a thin film transistor (TFT) to be used as a display switching and driving device having excellent performance without increasing costs, along with the enlargement of a substrate such as glass, is required.

Therefore, the future development of technology should focus on securing TFT manufacturing technology that can manufacture display panels of high performance at low cost in accordance with this trend.

A typical amorphous silicon thin film transistor (a-Si TFT) as a driving and switching element of a display is a device widely used as a device that can be uniformly formed on a large substrate of more than 2 m at a low cost.

However, with the trend toward larger displays and higher image quality, device performance is also required, and the existing a-Si TFT with a mobility of 0.5 cm ² / Vs is expected to reach its limit.

Therefore, there is a need for a high performance TFT and a manufacturing technology having higher mobility than a-Si TFT. In addition, as a-Si TFT continues to operate as its greatest weakness, the device characteristics continue to deteriorate, thereby including a reliability problem in which initial performance cannot be maintained.

This is the main reason why a-Si TFT is difficult to be applied as an organic luminescence display (OLED) that operates by continuously flowing current rather than an AC-driven LCD.

Poly-Si TFTs, which have significantly higher performance than a-Si TFTs, have high mobility from tens to hundreds of cm ² / Vs, so they can be applied to high-definition displays that were difficult to realize in conventional a-Si TFTs. In addition to the performance, the problem of deterioration of device characteristics due to operation compared to a-Si TFT is very small. However, manufacturing a poly-Si TFT requires a large number of processes compared to a-Si TFT, and other additional equipment investment must also be preceded.

Therefore, the p-Si TFT is suitable for high-definition display and applications such as OLED, but in terms of cost is inferior to the existing a-Si TFT, the application is limited.

In particular, in the case of p-Si TFT, due to technical problems such as limitations of manufacturing equipment and poor uniformity, a manufacturing process using a large substrate of more than 1 m has not been realized until now, so that application to TV products is difficult. P-Si TFTs are becoming a factor that makes it difficult to position in the market.

Therefore, the demand for a new TFT technology that can take advantage of both the advantages of a-Si TFT (large size, low cost, uniformity) and the advantages of poly-Si TFT (high performance, reliability) is greater than ever. There is progress, and the representative thing is an oxide semiconductor.

Such oxide semiconductors have advantages of higher mobility than amorphous silicon (a-Si) TFTs and simpler manufacturing processes and lower manufacturing costs than polycrystalline silicon (poly-Si) TFTs. The use value as (LCD) and organic electroluminescent element (OLED) is high.

From this point of view, a structure of an oxide thin film transistor according to the prior art using an oxide semiconductor will be described with reference to FIGS. 1 and 2. FIG.

1 is a schematic cross-sectional view of an oxide thin film transistor structure according to the prior art.

FIG. 2 is a schematic cross-sectional view of an oxide thin film transistor according to the related art, and illustrates a phenomenon in which an active layer deteriorates device characteristics in response to external optical characteristics.

The oxide thin film transistor 10 according to the related art includes a gate electrode 13 patterned with a predetermined width and length on a substrate 11 and a gate electrode 13 patterned on the substrate 11 as shown in Figs. An active layer 17 formed on the gate insulating film 15 including the gate electrode 13 and formed of a patterned oxide semiconductor in a predetermined pattern, An etch stop layer 19 formed on the active layer 17 and formed in a pattern of a predetermined pattern and a gate insulating layer 15 spaced from the top of the etch stop layer 19 and formed on the active layer 17 and the gate insulating layer 15 And a source electrode 21 and a drain electrode 23 formed in this order.

The etch stop layer 19 overlaps with the gate electrode 13 and the active layer 17 and is formed above the channel region of the active layer 17.

The source electrode 21 and the drain electrode 23 are spaced apart from each other on the etch stop layer 19 and are formed on the etch stop layer 19, the active layer 17, and the gate insulating layer 15 .

According to the oxide thin film transistor 10 according to the prior art, as shown in Figure 2, UV light used in the X-ray (Ion) ionizer and photo exposure process used for the antistatic purpose When EUV light irradiation is used for irradiation or cleaning purposes, light is transmitted to an active layer 17 made of an oxide semiconductor, for example, IGZO, such that the active layer 17 reacts to optical properties. It will lower the characteristics. In this case, although the etch stop layer 19 protects the channel region of the active layer 17, light cannot be considered to protect the channel region of the active layer 17 from the light.

In particular, since the prior art requires the above processes using optical characteristics at the time of wiring formation, such optical characteristics degrade the characteristics of the oxide semiconductor constituting the active layer, for example, IGZO.

The present invention is to solve the problems of the prior art, an object of the present invention is to form a light blocking pattern on the channel region of the active layer to block the external light transmitted to the active layer, thereby affecting the device characteristics of the oxide thin film transistor It is to provide an oxide thin film transistor and a manufacturing method that can ensure a stable device characteristics by minimizing this.

Another object of the present invention is to provide an array substrate having an oxide thin film transistor and a method of manufacturing the same, which can be used as a pixel electrode of a display device by conducting an oxide semiconductor constituting an active layer and simplifying a manufacturing process. Is in.

According to an aspect of the present invention, there is provided an oxide thin film transistor including: a gate electrode formed on a substrate; A gate insulating film formed on the entire surface of the substrate including the gate electrode; An active pattern formed on the gate insulating film above the gate electrode; An etch stop layer pattern formed on the active pattern; A source electrode and a drain electrode formed on the active pattern and spaced apart from each other; A passivation film formed on the entire surface of the substrate including the source electrode and the drain electrode; And a light blocking pattern formed on the passivation layer on the upper side of the active pattern.

A first feature of an array substrate having an oxide thin film transistor according to the present invention for achieving the above object is a gate electrode formed on the substrate; A gate insulating film formed on the entire surface of the substrate including the gate electrode; An active pattern formed on the gate insulating film above the gate electrode; An etch stop layer pattern formed on the active pattern; A source electrode and a drain electrode formed on the active pattern and spaced apart from each other; A passivation film formed over the substrate including the source electrode and the drain electrode and exposing the drain electrode; A light blocking pattern formed on the passivation film above the active pattern; And a conductive semiconductor pattern formed on the passivation layer and electrically connected to the exposed drain electrode.

A second aspect of the array substrate having an oxide thin film transistor according to the present invention for achieving the above object is a gate electrode formed on the substrate; A gate insulating film formed on the entire surface of the substrate including the gate electrode; A non-conductive channel region formed on the gate insulating film above the gate electrode, a conductive source region and a drain region, and a pixel electrode region extending from the drain region and conductive; A light blocking pattern formed on the channel region; And a source electrode and a drain electrode formed on the conductive source region and the drain region and spaced apart from each other.

A third aspect of the array substrate having an oxide thin film transistor according to the present invention for achieving the above object is a gate electrode formed on the substrate; A gate insulating film formed on the entire surface of the substrate including the gate electrode; A non-conductive channel region formed on the gate insulating film above the gate electrode, a conductive source region and a drain region, and a pixel electrode region extending from the drain region and conductive; A light blocking pattern formed on the channel region; And a source electrode formed on the conductive source region.

An oxide thin film transistor manufacturing method according to the present invention for achieving the above object comprises the steps of forming a gate electrode on the substrate; Forming a gate insulating film on the entire surface of the substrate including the gate electrode; Forming an active pattern on the gate insulating layer above the gate electrode; Forming an etch stop layer pattern on the active pattern; Forming a source electrode and a drain electrode spaced apart from each other on the active pattern; Forming a passivation film on the entire surface of the substrate including the source electrode and the drain electrode; And forming a light blocking pattern on the passivation layer on the upper side of the active pattern.

A first aspect of the method of manufacturing an array substrate having an oxide thin film transistor according to the present invention for achieving the above object is the step of forming a gate electrode on the substrate; Forming a gate insulating film on the entire surface of the substrate including the gate electrode; Forming an active pattern on the gate insulating layer above the gate electrode; Forming an etch stop layer pattern on the active pattern; Forming a source electrode and a drain electrode spaced apart from each other on the active pattern; Forming a passivation film exposing the drain electrode on the entire surface of the substrate including the source electrode and the drain electrode; Forming a light blocking pattern on the passivation layer on the active pattern; And forming a conductive oxide semiconductor pattern electrically connected to the exposed drain electrode on the passivation layer.

A second aspect of the method of manufacturing an array substrate having an oxide thin film transistor according to the present invention for achieving the above object comprises the steps of: forming a gate electrode on the substrate; Forming a gate insulating film on the entire surface of the substrate including the gate electrode; Forming an oxide semiconductor layer on the gate insulating film above the gate electrode; Irradiating the oxide semiconductor layer with light to form a non-conductive channel region, a conductive source region and a drain region, and a pixel electrode region extending from the drain region and having a conductivity; Forming a light blocking pattern on the channel region; And a source electrode and a drain electrode respectively formed on the conductive source and drain regions and spaced apart from each other.

A third aspect of the method for manufacturing an oxide thin film transistor according to the present invention for achieving the above object comprises the steps of: forming a gate electrode on a substrate; Forming a gate insulating film on the entire surface of the substrate including the gate electrode; Forming a non-conductive channel region, a conductive source region and a conductive pixel electrode region on the gate insulating film above the gate electrode; Forming a light blocking pattern on the channel region; And forming a source electrode on the conductive source region.

According to the oxide thin film transistor according to the present invention, a manufacturing method, an array substrate having the same, and a manufacturing method thereof have the following effects.

According to the oxide thin film transistor according to the present invention, a manufacturing method, an array substrate having the same, and a manufacturing method thereof, an X-ray ionizer and a photo process are formed by forming a light blocking pattern on an upper portion of an active layer. By blocking the reaction of the oxide semiconductor by external light characteristics such as UV light used at the time and EUV light used at the cleaning process, the device characteristics of the oxide thin film transistor can be minimized to ensure stable device characteristics.

According to the oxide thin film transistor according to the present invention, a manufacturing method, an array substrate having the same, and a manufacturing method thereof, the conductorization is performed by conducting the characteristics of the remaining portions of the oxide semiconductor constituting the active layer except for the portion corresponding to the channel region. The applied portion can be applied to the pixel electrode to simplify the process of manufacturing the array substrate for the display device.

1 is a schematic cross-sectional view of an oxide thin film transistor structure according to the prior art.
FIG. 2 is a schematic cross-sectional view of an oxide thin film transistor according to the related art, and illustrates a phenomenon in which an active layer deteriorates device characteristics in response to external optical characteristics.
3 is a schematic cross-sectional view of an oxide thin film transistor according to a first embodiment of the present invention.
FIGS. 4A to 4G are cross-sectional views illustrating an oxide thin film transistor manufacturing process according to the first embodiment of the present invention.
5 is a schematic cross-sectional view of an oxide thin film transistor having a double gate structure according to a second embodiment of the present invention.
6 is a schematic cross-sectional view of an array substrate for a display device to which an oxide thin film transistor according to a first embodiment of the present invention is applied.
7A to 7L are cross-sectional views illustrating a process of manufacturing an array substrate for a display device to which an oxide thin film transistor according to a first embodiment of the present invention is applied.
8 is a schematic cross-sectional view of an array substrate for a display device to which an oxide thin film transistor according to a third exemplary embodiment of the present invention is applied.
9A to 9F are cross-sectional views illustrating a manufacturing process of an array substrate for a display device to which an oxide thin film transistor according to a third exemplary embodiment of the present invention is applied.
10 is a schematic cross-sectional view of an array substrate for a display device to which an oxide thin film transistor according to a fourth exemplary embodiment of the present invention is applied.
11A through 11E are cross-sectional views illustrating fabrication processes of an array substrate for a display device to which an oxide thin film transistor according to a fourth exemplary embodiment of the present invention is applied.

Hereinafter, a structure of an oxide thin film transistor according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic cross-sectional view of an oxide thin film transistor according to a first embodiment of the present invention.

An oxide thin film transistor 100 according to the present invention, as shown in Figure 3, the gate electrode 103a formed on the substrate 101; A gate insulating film 107 formed on the entire surface of the substrate including the gate electrode 103a; An active pattern 109a formed on the gate insulating film 107 over the gate electrode 103a; An etch stop layer pattern 113a formed on the active pattern 109a; Source and drain electrodes 117a and 117b formed on the active pattern 109a and spaced apart from each other; A passivation film 121 formed on the entire surface of the substrate including the source electrode 117a and the drain electrode 117b; And a light blocking pattern 123a formed on the passivation film 121 above the active pattern 109a.

Here, the oxide thin film transistor 100 according to the first embodiment of the present invention includes all the thin film transistor structures that can be driven including a top gate, a bottom gate, and the like. The thin film transistor 100 includes a thin film transistor using an etch stop layer and a thin film transistor having a BCE structure.

The thin film transistor 100 according to the present invention may be a driving element or a switching element of a flat panel display such as a liquid crystal display (LCD), an organic light emitting diode (OLED) And a device for constituting a peripheral circuit of the device.

The substrate 101 may comprise silicon, glass, plastic or other suitable material.

As the gate electrode 103a, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy) , Gold (Au), Au alloy, Chromium (Cr), Titanium (Ti), Titanium alloy (Ti alloy), Moly tungsten (MoW), Molaritanium (MoTi), Copper / Mortinium (Cu / MoTi It may also comprise at least any one selected from the group of conductive metals, or a combination of two or more thereof, or other suitable material.

In addition, the gate insulating layer 107 may be a silicon (Si) -based oxide film, a nitride film, or a compound including the same, a metal oxide film including an Al ₂ O ₃ , an organic insulating film, a low dielectric constant (low −). k) material having a value. For example, the gate insulating film 107 may include silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) Or combinations of two or more thereof or other suitable materials.

In addition, the active pattern 109a is a layer for forming a channel through which electrons move between the source electrode 117a and the drain electrode 117b, and is referred to as low temperature polysilicon (hereinafter referred to as LTPS) or amorphous. Instead of the silicon (a-Si) material, a silicon (Si) -based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nanotube, and graphene are used.

At this time, the oxide semiconductor may be at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium And a material in which silicon (Si) is added to an oxide semiconductor containing zinc (Zn). For example, the active pattern 109a may be made of silicon-indium zinc oxide (Si-InZnO: SIZO) to which an indium zinc composite oxide (InZnO) is added with silicon ions.

When the active pattern 109a is made of SIZO, the composition ratio of the silicon atom content to the total content of zinc (Zn), indium (In) and silicon (Si) atoms in the active layer is about 0.001 wt% ) To about 30 wt%. The higher the silicon (Si) atomic content, the stronger the role of controlling electron generation, so that the mobility may be lowered, but the stability of the device may be better.

Meanwhile, the active pattern 109a may be a group I element such as lithium (Li) or potassium (K), a group II element such as magnesium (Mg), calcium (Ca), or strontium (Sr), in addition to the above materials. Group III elements such as gallium (Ga), aluminum (Al), indium (In) or yttrium (Y), titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge) Group V elements such as Group IV elements, tantalum (Ta), vanadium (V), niobium (Nb) or antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd) ), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolidium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium Lanthanum (Ln) -based elements such as (Yb) or ruthedium (Lu) may be further included.

The etch stop layer pattern 113a may be a silicon oxide layer, a nitride layer, a metal oxide layer containing Al ₂ O ₃ , an organic insulating layer, a low dielectric constant -k) < / RTI > value.

The source electrode 117a and the drain electrode 117b include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), and silver (Ag). , Silver alloy (Ag), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum (MoW), molybdenum (MoTi), copper It may also comprise at least any one selected from the group of conductive metals including / molitanium (Cu / MoTi) or a combination of two or more thereof or other suitable materials.

In addition, the light blocking pattern 123a is disposed to block the entirety of the active pattern 109a including the channel region. In this case, the light blocking pattern 123a may be formed of a material capable of shielding light. For example, any one of a group containing a metal-based material, Ni, Co, Cu, a copper alloy, a plastic-based material, and these metal alloys may be used. Use

Therefore, according to the oxide thin film transistor according to the present invention, the light blocking pattern is formed on the active pattern, and the X-ray ionizer used during the process and the UV light used during the photo process and the cleaning process By blocking the reaction of the oxide semiconductor by external optical characteristics such as EUV light to be used, it is possible to minimize the influence of the device characteristics of the oxide thin film transistor to secure stable device characteristics.

The oxide thin film transistor according to the first embodiment of the present invention will be described in detail with reference to FIGS. 4A to 4G.

4A to 4G are cross-sectional views illustrating a manufacturing process of an oxide thin film transistor according to the first embodiment of the present invention.

4A, a first conductive layer 103 is formed by depositing a first conductive material for a gate electrode on a substrate 101 by a sputtering method, a first photosensitive layer (not shown) is coated on the first conductive layer 103, The first photoresist pattern 105 is formed by patterning the first photoresist layer (not shown) through a first mask process using a photolithography process technique.

In this case, the substrate 101 may be made of silicon, glass, plastic or other suitable material.

The first conductive layer 103 may be formed of a metal such as aluminum (Al), an aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo) A metal alloy such as Ag alloy, Au, Au alloy, Cr, Ti, Ti alloy, MoW, MoTi, (Cu / MoTi), or a combination of two or more thereof, or other suitable material.

Next, referring to FIG. 4B, the first conductive layer 103 is selectively etched using the first photoresist pattern 105 as an etching mask to form a gate electrode 103a.

Subsequently, the first photoresist pattern 105 is removed, and a gate insulating layer 107 is formed on the entire surface of the substrate including the gate electrode 103a. In this case, the gate insulating layer 107 may include a silicon (Si) -based oxide film, a nitride film, or a compound including the same, a metal oxide including Al ₂ O ₃ , an organic insulating film, and a low dielectric constant (low −). k) material having a value. For example, the gate insulating film 107 may include silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) Or combinations of two or more thereof or other suitable materials.

Next, an active layer 109 is formed on the gate insulating layer 107. In this case, the active layer 109 is a layer for forming a channel through which electrons move between a source electrode (not shown) and a drain electrode (not shown), which is referred to as Low Temperature Poly Silicon (hereinafter referred to as LTPS). Alternatively, a silicon (Si) -based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nanotube, or graphene may be used instead of an amorphous silicon (a-Si) material.

At this time, the oxide semiconductor may be at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium And a material in which silicon (Si) is added to an oxide semiconductor containing zinc (Zn). For example, the active layer 109 may be formed of silicon indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to indium zinc complex oxide (InZnO).

When the active layer 109 is made of SIZO, the composition ratio of the silicon (Si) atom content to the total content of zinc (Zn), indium (In) and silicon (Si) atoms in the active layer is about 0.001 wt% ) To about 30 wt%. The higher the silicon (Si) atomic content, the stronger the role of controlling electron generation, so that the mobility may be lowered, but the stability of the device may be better.

On the other hand, the active layer 109, in addition to the above-described materials, Group I elements such as lithium (Li) or potassium (K), Group II elements such as magnesium (Mg), calcium (Ca) or strontium (Sr), Group III elements such as gallium (Ga), aluminum (Al), indium (In) or yttrium (Y), titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge) Group V elements such as group IV elements, tantalum (Ta), vanadium (V), niobium (Nb) or antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd) ), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolidium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium Lanthanum (Ln) -based elements such as (Yb) or ruthedium (Lu) may be further included.

Next, a second photoresist layer (not shown) is coated on the active layer 109, and the second photoresist layer is exposed and developed through a second mask process using a photolithography process technique. Then, Is selectively patterned to form a second photoresist pattern 111.

4C, the active layer 109 is selectively removed using the second photoresist pattern 111 as an etching mask to form an active pattern 109 on the gate insulating film 107 on the gate electrode 103a, (109a).

Subsequently, the second photoresist pattern 111 is removed, an etch stop layer 113 is formed on the gate insulating film 107 including the active pattern 109a, a third photoresist layer (not shown) is coated thereon do. The etch stop layer 113 may be formed of a metal oxide, an organic insulating film, a low dielectric constant material such as silicon oxide, nitride, or Al ₂ O ₃ , k). < / RTI >

Then, after the third photoresist film (not shown) is exposed and developed through a third mask process using a photolithography process technique, the third photoresist film pattern 115 is selectively patterned to selectively expose the third photoresist film 115 . At this time, the third photoresist pattern 115 remains only on the upper portion of the etch stop layer 113 which overlaps the channel region of the active pattern 109a.

Next, as shown in FIG. 4D, the etch stop layer 113 is etched using the third photoresist pattern 115 as an etch mask, thereby forming an etch stop layer pattern 113a.

4E, after the third photoresist pattern 115 is removed, the entire surface of the substrate including the etch stop layer pattern 113a, for example, the active pattern 109a and the gate insulating film 107 A conductive material is deposited by sputtering to form a second conductive layer 117, and a fourth photosensitive film (not shown) is further coated thereon. In this case, as the second conductive layer 117, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenum (MoTi), copper / molity titanium It may comprise at least any one selected from the group of conductive metals containing (Cu / MoTi) or a combination of two or more thereof or other suitable materials.

Then, the fourth photosensitive film (not shown) is exposed and developed through a fourth mask process using a photolithography process technique, and then the fourth photosensitive film (not shown) is selectively patterned to form a fourth photosensitive film pattern 119 do.

Next, the second conductive layer 117 is etched using the fourth photoresist pattern 119 as an etching mask to form the source electrode 117a and the drain electrode 117a spaced apart from each other with reference to the etch stop layer pattern 113a, The second photoresist pattern 117b is formed and the fourth photoresist pattern 119 is removed.

Then, as shown in FIG. 4F, a passivation film 121 is deposited on the entire surface of the substrate including the source electrode 117a and the drain electrode 117b. In this case, the passivation layer 121 may include a silicon (Si) -based oxide layer, a nitride layer, or a compound including the same, a metal oxide layer including Al ₂ O ₃ , an organic insulating layer, and a low dielectric constant. k) material having a value. For example, the a gate insulating film 107, silicon oxide (SiO _2), silicon nitride (SiNx), zirconium oxide (ZrO _2), hafnium oxide (HfO _2), titanium oxide (TiO _2), tantalum oxide ( Ta ₂ O _5), barium-strontium-titanium-one selected from the group consisting of oxygen compounds (Bi-Zn-Nb-O ) - oxygen compound (Ba-Sr-Ti-O ) and bismuth-zinc-niobium Or a combination of two or more thereof or other suitable material.

Next, a light blocking layer 123 is formed on the passivation film 121 for use as a film for blocking external light from being transmitted to the channel region of the active pattern 109a, and a fifth photoresist film (on (Not shown). In this case, the light blocking layer 123 may be any material capable of shielding external light, for example, any one of a group containing a metal-based material, Ni, Co, Cu, a copper alloy, a plastic-based material, and these metal alloys. Use

Then, the fifth photosensitive film (not shown) is exposed and developed through a fifth mask process using a photolithography process technique, and then the fifth photosensitive film (not shown) is selectively patterned to form a fifth photosensitive film pattern 125 do.

Next, as shown in FIG. 4G, the fifth photoresist pattern 125 is used as an etch mask and the light blocking layer 123 is etched to shield the entire active pattern 109a from external light. By forming the blocking pattern 123a and removing the fifth photoresist pattern 125, the oxide thin film transistor manufacturing process according to the first embodiment of the present invention is completed.

Therefore, according to the oxide thin film transistor manufacturing method according to the first embodiment of the present invention, by forming a light blocking pattern on the upper portion of the active layer, which is used during the X-ray ionizer and photo process used during the process By blocking the reaction of the oxide semiconductor due to external light characteristics such as UV light and EUV light used in the cleaning process, stable device characteristics can be secured by minimizing the influence of device characteristics of the oxide thin film transistor.

Meanwhile, an oxide thin film transistor structure according to a second embodiment of the present invention will be described with reference to FIG. 5.

5 is a schematic cross-sectional view of an oxide thin film transistor having a double gate structure according to a second embodiment of the present invention.

Here, the structure of the oxide thin film transistor 200 of the double gate structure according to the second embodiment of the present invention is the same as the structure of the oxide thin film transistor 100 according to the first embodiment of the present invention, and only the light blocking pattern ( 223a) is used as the upper gate and is electrically connected to the lower gate.

The oxide thin film transistor 200 according to the second embodiment of the present invention, as shown in Figure 5, the gate electrode formed on the substrate 201 (203a); A gate insulating film 207 formed on the entire surface of the substrate including the gate electrode 203a; An active pattern 209a formed on the gate insulating film 207 on the gate electrode 203a; An etch stop layer pattern 213a formed on the active pattern 209a; A source electrode 217a and a drain electrode 217b formed on the active pattern 209a and spaced apart from each other; A passivation film 221 formed over the substrate including the source electrode 217a and the drain electrode 217b and exposing the gate electrode 203a; And a light blocking pattern 123a formed on the passivation layer 221 on the active pattern 209a and electrically connected to the gate electrode 203a.

Here, the oxide thin film transistor 200 according to the first embodiment of the present invention includes both a thin film transistor structure that can be driven including a top gate, a bottom gate method, and the like. In addition, the thin film transistor 200 includes a thin film transistor using an etch stop layer and a thin film transistor having a BCE structure.

The thin film transistor 200 according to the present invention is a driving element or switching element of a flat panel display such as a liquid crystal display (hereinafter referred to as LCD), an organic light emitting diode (hereinafter referred to as OLED), a memory, It can be applied to various electronic devices such as devices for the peripheral circuit configuration of the device.

The substrate 101 may comprise silicon, glass, plastic or other suitable material.

The gate electrode 203a may be formed of a metal such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag) Au alloy, Au alloy, Cr alloy, Ti alloy, Ti alloy, MoW, MoTi, Cu / MoTi alloy, ), Or a combination of two or more thereof, or other suitable materials.

The gate insulating layer 207 may be a silicon oxide layer, a nitride layer or a compound containing the oxide layer, a metal oxide layer including Al ₂ O ₃ , an organic insulating layer, a low- k). < / RTI > For example, the gate insulating film 107 may include silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) Or combinations of two or more thereof or other suitable materials.

In addition, the active pattern 209a is a layer for forming a channel through which electrons move between the source electrode 117a and the drain electrode 117b, and is referred to as low temperature polysilicon (hereinafter referred to as LTPS) or amorphous. Instead of the silicon (a-Si) material, a silicon (Si) -based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nanotube, and graphene are used.

At this time, the oxide semiconductor may be at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium And a material in which silicon (Si) is added to an oxide semiconductor containing zinc (Zn). For example, the active pattern 109a may be made of silicon-indium zinc oxide (Si-InZnO: SIZO) to which an indium zinc composite oxide (InZnO) is added with silicon ions.

When the active pattern 209a is made of SIZO, the composition ratio of the silicon atom content to the total content of zinc (Zn), indium (In) and silicon (Si) atoms in the active layer is about 0.001 wt% ) To about 30 wt%. The higher the silicon (Si) atomic content, the stronger the role of controlling electron generation, so that the mobility may be lowered, but the stability of the device may be better.

On the other hand, as the active pattern 209a, in addition to the above materials, Group I elements such as lithium (Li) or potassium (K), Group II elements such as magnesium (Mg), calcium (Ca) or strontium (Sr), Group III elements such as gallium (Ga), aluminum (Al), indium (In) or yttrium (Y), titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge) Group V elements such as Group IV elements, tantalum (Ta), vanadium (V), niobium (Nb) or antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd) ), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolidium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium Lanthanum (Ln) -based elements such as (Yb) or ruthedium (Lu) may be further included.

The etch stop layer pattern 213a may be a silicon oxide layer, a nitride layer, or a metal oxide layer including Al ₂ O ₃ , an organic insulating layer, a low dielectric constant -k) < / RTI > value.

The source electrode 217a and the drain electrode 217b include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), and silver (Ag). , Silver alloy (Ag), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum (MoW), molybdenum (MoTi), copper It may also comprise at least any one selected from the group of conductive metals including / molitanium (Cu / MoTi) or a combination of two or more thereof or other suitable materials.

In addition, the light blocking pattern 223a is disposed to block the entirety of the active pattern 109a including the channel region. In this case, the light blocking pattern 123a may be formed of a material capable of shielding light. For example, any one of a group containing a metal-based material, Ni, Co, Cu, a copper alloy, a plastic-based material, and these metal alloys may be used. Use

Therefore, according to the oxide thin film transistor of the double gate structure according to the second embodiment of the present invention, by forming a light blocking pattern on the active pattern, during the X-ray ionizer and photo process used in the process By blocking the reaction of the oxide semiconductor by external light characteristics such as UV light to be used and EUV light to be used in the cleaning process, the device characteristics of the oxide thin film transistor can be minimized to ensure stable device characteristics.

In addition, an array substrate for a display device to which the oxide thin film transistor according to the first exemplary embodiment of the present invention is applied will be described with reference to FIG. 6.

6 is a schematic cross-sectional view of an array substrate for a display device to which an oxide thin film transistor according to a first embodiment of the present invention is applied.

3 is a schematic cross-sectional view of an oxide thin film transistor according to a first embodiment of the present invention.

As shown in FIG. 6, an array substrate 300 to which an oxide thin film transistor is applied includes a gate electrode 303a formed on a substrate 301; A gate insulating film 307 formed on the entire surface of the substrate including the gate electrode 303a; An active pattern 309a formed on the gate insulating film 307 above the gate electrode 303a; An etch stop layer pattern 313a formed on the active pattern 309a; Source and drain electrodes 317a and 317b formed on the active pattern 309a and spaced apart from each other; A passivation film 321 formed over the substrate including the source electrode 317a and the drain electrode 317b and exposing the drain electrode 317b; A light blocking pattern 323a formed on the passivation film 321 above the active pattern 309a; And an oxide semiconductor pattern 331a having a conductivity formed on the passivation layer 321 and electrically connected to the drain electrode 317b through an exposed portion of the passivation layer 321.

Here, the display device array substrate 300 to which the oxide thin film transistor according to the first embodiment of the present invention is applied includes a liquid crystal display (LCD) and an organic luminescence diode (hereinafter referred to as "LCD"). It may be applied to a flat panel display and the like.

The substrate 301 may comprise silicon, glass, plastic or other suitable material.

As the gate electrode 303a, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy) , Gold (Au), Au alloy, Chromium (Cr), Titanium (Ti), Titanium alloy (Ti alloy), Moly tungsten (MoW), Molaritanium (MoTi), Copper / Mortinium (Cu / MoTi It may also comprise at least any one selected from the group of conductive metals, or a combination of two or more thereof, or other suitable material.

In addition, the gate insulating layer 307 may be a silicon (Si) -based oxide film, a nitride film, or a compound including the same, a metal oxide film including an Al ₂ O ₃ , an organic insulating film, a low dielectric constant (low −). k) material having a value. For example, the gate insulating film 107 may include silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) Or combinations of two or more thereof or other suitable materials.

The active pattern 309a is a layer for forming a channel through which electrons move between the source electrode 317a and the drain electrode 317b, and is referred to as low temperature polysilicon (LTPS) or amorphous. Instead of the silicon (a-Si) material, a silicon (Si) -based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nanotube, and graphene are used.

At this time, the oxide semiconductor may be at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium And a material in which silicon (Si) is added to an oxide semiconductor containing zinc (Zn). For example, the active pattern 109a may be made of silicon-indium zinc oxide (Si-InZnO: SIZO) to which an indium zinc composite oxide (InZnO) is added with silicon ions.

When the active pattern 309a is made of SIZO, the composition ratio of silicon (Si) atom content to the total content of zinc (Zn), indium (In), and silicon (Si) atoms in the active layer is about 0.001% by weight (wt%). ) To about 30 wt%. The higher the silicon (Si) atomic content, the stronger the role of controlling electron generation, so that the mobility may be lowered, but the stability of the device may be better.

On the other hand, as the active pattern 309a, in addition to the above materials, Group I elements such as lithium (Li) or potassium (K), Group II elements such as magnesium (Mg), calcium (Ca) or strontium (Sr), Group III elements such as gallium (Ga), aluminum (Al), indium (In) or yttrium (Y), titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge) Group V elements such as Group IV elements, tantalum (Ta), vanadium (V), niobium (Nb) or antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd) ), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolidium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium Lanthanum (Ln) -based elements such as (Yb) or ruthedium (Lu) may be further included.

In addition, the etch stop layer pattern 313a may be formed of a silicon-based oxide, nitride, or Al ₂ O ₃ metal oxide, an organic insulating layer, or a low dielectric constant. -k) include materials with values.

The source electrode 317a and the drain electrode 317b include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), molybdenum (Mo), silver (Ag), and a silver alloy. (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenum (MoTi), copper / molity titanium It may comprise at least any one selected from the group of conductive metals containing (Cu / MoTi) or a combination of two or more thereof or other suitable materials.

In addition, the light blocking pattern 323a is disposed to block the entirety of the active pattern 309a including the channel region. In this case, the light blocking pattern 323a may be formed of a material capable of shielding light. For example, any one of a group containing a metal-based material, Ni, Co, Cu, a copper alloy, a plastic-based material, and a metal alloy may be used. Use

On the other hand, as the conductive oxide semiconductor pattern 331a, a silicon (Si) -based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, and a carbon nanotube that are conductive by X-ray light irradiation ), Graphene is used.

Accordingly, according to the array substrate for a display device to which the oxide thin film transistor according to the present invention is applied, a light blocking pattern is formed on an active pattern, and used in an X-ray ionizer and a photo process used during the process. By blocking the reaction of the oxide semiconductor by external light characteristics such as UV light and EUV light used in the cleaning process, stable device characteristics can be secured by minimizing the influence of device characteristics of the oxide thin film transistor.

Further, according to the array substrate to which the oxide thin film transistor according to the first embodiment of the present invention is applied, the conductive semiconductor can be applied as a pixel electrode by converting the oxide semiconductor into a conductor.

An array substrate for a display device to which the oxide thin film transistor according to the first embodiment of the present invention having the above structure is applied will be described in detail with reference to FIGS. 7A to 7L.

7A to 7L are cross-sectional views illustrating a manufacturing process of an array substrate for a display device to which an oxide thin film transistor according to a first exemplary embodiment of the present invention is applied.

Referring to FIG. 7A, after depositing a first conductive material for a gate electrode on a substrate 301 by a sputtering method, a first conductive layer 303 is formed and a first photosensitive film (not shown) is applied thereon. The first photoresist layer is patterned through a first mask process using a photolithography process technology to form a first photoresist layer pattern 305.

In this case, the substrate 301 may include silicon, glass, plastic, or other suitable material.

In addition, as the first conductive layer 303, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenum (MoTi), copper / molity titanium It may comprise at least any one selected from the group of conductive metals containing (Cu / MoTi) or a combination of two or more thereof or other suitable materials.

Next, referring to FIG. 7B, the first conductive layer 303 is selectively etched using the first photoresist pattern 305 as an etching mask to form a gate electrode 303a.

Subsequently, the first photoresist layer pattern 305 is removed, and a gate insulating layer 307 is formed on the entire surface of the substrate including the gate electrode 303a. In this case, the gate insulating film 307 may be a silicon (Si) -based oxide film, a nitride film, or a compound including the same, a metal oxide film including an Al ₂ O ₃ , an organic insulating film, and a low dielectric constant (low −). k) material having a value. For example, the a gate insulating film 307, silicon oxide (SiO _2), silicon nitride (SiNx), zirconium oxide (ZrO _2), hafnium oxide (HfO _2), titanium oxide (TiO _2), tantalum oxide ( Ta ₂ O _5), barium-strontium-titanium-one selected from the group consisting of oxygen compounds (Bi-Zn-Nb-O ) - oxygen compound (Ba-Sr-Ti-O ) and bismuth-zinc-niobium Or a combination of two or more thereof or other suitable material.

Next, an active layer 309 is formed on the gate insulating layer 307. In this case, the active layer 309 is a layer for forming a channel through which electrons move between a source electrode (not shown) and a drain electrode (not shown), which is referred to as Low Temperature Poly Silicon (LTPS). Alternatively, a silicon (Si) -based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nanotube, or graphene may be used instead of an amorphous silicon (a-Si) material.

At this time, the oxide semiconductor may be at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium And a material in which silicon (Si) is added to an oxide semiconductor containing zinc (Zn). For example, the active layer 109 may be formed of silicon indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to indium zinc complex oxide (InZnO).

When the active layer 309 is made of SIZO, the composition ratio of silicon (Si) atom content to the total content of zinc (Zn), indium (In), and silicon (Si) atoms in the active layer is about 0.001 wt% (wt%). ) To about 30 wt%. The higher the silicon (Si) atomic content, the stronger the role of controlling electron generation, so that the mobility may be lowered, but the stability of the device may be better.

On the other hand, the active layer 309, in addition to the above-described materials, Group I elements such as lithium (Li) or potassium (K), Group II elements such as magnesium (Mg), calcium (Ca) or strontium (Sr), Group III elements such as gallium (Ga), aluminum (Al), indium (In) or yttrium (Y), titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge) Group V elements such as group IV elements, tantalum (Ta), vanadium (V), niobium (Nb) or antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd) ), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolidium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium Lanthanum (Ln) -based elements such as (Yb) or ruthedium (Lu) may be further included.

Subsequently, a second photoresist film (not shown) is coated on the active layer 309, the second photoresist film is exposed and developed through a second mask process using a photolithography process technology, and then the second photoresist film (not shown). ) Is selectively patterned to form a second photoresist pattern 111.

Next, referring to FIG. 7C, the active layer 309 is selectively removed by using the second photoresist layer pattern 311 as an etch mask, thereby forming an active pattern on the gate insulating layer 307 above the gate electrode 303a. 309a is formed.

Subsequently, the second photoresist layer pattern 311 is removed, an etch stop layer 313 is formed on the gate insulation layer 307 including the active pattern 309a, and a third photoresist layer (not shown) is applied thereon. do. In this case, the etch stop layer 313 may be formed of silicon (Si) based oxide, nitride, or Al ₂ O ₃ including metal oxide, organic insulating layer, and low dielectric constant. k) material having a value.

Next, after exposing and developing the third photoresist film (not shown) through a third mask process using a photolithography process technology, the third photoresist film (not shown) is selectively patterned to form a third photoresist pattern 315. Form. In this case, the third photoresist layer pattern 315 remains only on the etch stop layer 313 overlapping the channel region of the active pattern 309a.

Subsequently, as illustrated in FIG. 7D, the etch stop layer 313 is etched using the third photoresist pattern 315 as an etch mask to form an etch stop layer pattern 313a.

Next, as shown in FIG. 7E, after the third photoresist layer pattern 315 is removed, the entire surface of the substrate including the etch stop layer pattern 313a, for example, the active pattern 309a, and the gate insulating layer 307. The second conductive layer 317 is formed by depositing a conductive material on the substrate) by a sputtering method, and a fourth photosensitive film (not shown) is coated on the conductive material. In this case, as the second conductive layer 317, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenum (MoTi), copper / molity titanium It may comprise at least any one selected from the group of conductive metals containing (Cu / MoTi) or a combination of two or more thereof or other suitable materials.

Subsequently, after exposing and developing the fourth photoresist film (not shown) through a fourth mask process using a photolithography process technology, the fourth photoresist film (not shown) is selectively patterned to form a fourth photoresist pattern 319. do.

Next, the fourth photoresist layer pattern 319 is etched and the second conductive layer 317 is etched to separate the source electrode 317a and the drain electrode spaced apart from each other based on the etch stop layer pattern 313a. 317b is formed to remove the fourth photoresist pattern 319.

Subsequently, as illustrated in FIG. 7F, a passivation film 321 is deposited on the entire surface of the substrate including the source electrode 317a and the drain electrode 317b. In this case, the passivation film 321 may be a silicon (Si) -based oxide film, a nitride film, or a compound including the same, a metal oxide film including an Al ₂ O ₃ , an organic insulating film, and a low dielectric constant (low −). k) material having a value. For example, the gate insulating film 307 may be silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), or tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) Or combinations of two or more thereof or other suitable materials.

Next, a light blocking layer 323 is formed on the passivation film 321 for use as a film for blocking external light from being transmitted to the channel region of the active pattern 309a, and a fifth photoresist film ( (Not shown). In this case, the light blocking layer 323 may be any material capable of shielding external light. For example, any one of a group containing a metal-based material, Ni, Co, Cu, a copper alloy, a plastic-based material, and these metal alloys may be used. Use

Subsequently, after exposing and developing the fifth photoresist film (not shown) through a fifth mask process using a photolithography process technology, the fifth photoresist film (not shown) is selectively patterned to form a fifth photoresist pattern 325. do.

Subsequently, as shown in FIG. 7G, the light having the fifth photoresist pattern 325 as an etch mask and the light blocking layer 323 is etched to shield the entire active pattern 309a from external light. The blocking pattern 323a is formed, and the fifth photosensitive film pattern 325 is removed.

Subsequently, after applying a sixth photoresist film (not shown) on the passivation film 321 including the light blocking pattern 323a, the sixth photoresist film (not shown) through a sixth mask process using a photolithography process technology After the exposure and development, the sixth photoresist layer (not shown) is selectively patterned to form a sixth photoresist layer pattern 327.

Next, as shown in FIG. 7H, a drain contact hole 329 is formed to expose the drain electrode 317b by etching the passivation layer 321 using the sixth photoresist layer pattern 327 as an etch mask. The sixth photosensitive film pattern 327 is removed.

Subsequently, as shown in FIG. 7I, the light blocking layer 331 is formed on the entire surface of the substrate including the drain contact hole 329.

Next, as shown in FIG. 7J, the light blocking layer 331 is irradiated with X-ray light, UV light, or EUV light to conductor the light blocking layer 331.

Subsequently, as shown in FIG. 7K, after applying a seventh photoresist film (not shown) on the conductive light blocking layer 331, the seventh photoresist ( After the exposure and development are performed, the seventh photoresist layer (not shown) may be selectively patterned to form a seventh photoresist layer pattern 333.

Next, as shown in FIG. 7L, the conductive photo-blocking layer 331 is etched using the seventh photoresist pattern 333 as an etch mask, and light blocking having conductivity applied to the pixel electrode of the display device. The pattern 331a is formed. In this case, the conductive light blocking pattern 331a has a property of transmitting light and can be used as a pixel electrode of a display device.

Thereafter, the seventh photoresist layer pattern 333 is removed to complete the array substrate manufacturing process using the oxide thin film transistor according to the first embodiment of the present invention.

According to the method of manufacturing an array substrate using the oxide thin film transistor according to the first embodiment of the present invention, a light blocking pattern is formed on an active layer, and used during the X-ray ionizer and photo process. By blocking the reaction of the oxide semiconductor by external light characteristics such as UV light to be used and EUV light to be used in the cleaning process, the device characteristics of the oxide thin film transistor can be minimized to ensure stable device characteristics.

In addition, according to the method of manufacturing an array substrate to which the oxide thin film transistor according to the first embodiment of the present invention is applied, the conductorization is performed by conducting the characteristics of the remaining portions of the oxide semiconductor constituting the active layer except for the portion corresponding to the channel region. The applied portion can be applied to the pixel electrode to simplify the process of manufacturing the array substrate for the display device.

Meanwhile, an array substrate for a display device to which an oxide thin film transistor according to a third exemplary embodiment of the present invention is applied will be described with reference to FIG. 8.

8 is a schematic cross-sectional view of an array substrate for a display device to which an oxide thin film transistor according to a third exemplary embodiment of the present invention is applied.

The array substrate 400 to which the oxide thin film transistor is applied according to the third embodiment of the present invention includes a gate electrode 403a formed on the substrate 401, as shown in FIG. A gate insulating film 405 formed on the entire surface of the substrate including the gate electrode 403; From the non-conductive channel region 407a formed on the gate insulating film 405 above the gate electrode 403, the conductive source region 407b and the drain region 407c, and the drain region 407c. An extended and conductive pixel electrode region 407d; A light blocking pattern 409 formed on the channel region 407a; And a source electrode 413a and a drain electrode 413b formed on the conductive source region 407b and the drain region 407c and spaced apart from each other.

Here, the array substrate 300 for applying the oxide thin film transistor according to the third embodiment of the present invention is a liquid crystal display (LCD), an organic light emitting diode (Organic Luminescence Emitted Diode) It may be applied to a flat panel display and the like.

The substrate 401 may include silicon, glass, plastic, or other suitable material.

As the gate electrode 403, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy) , Gold (Au), Au alloy, Chromium (Cr), Titanium (Ti), Titanium alloy (Ti alloy), Moly tungsten (MoW), Molaritanium (MoTi), Copper / Mortinium (Cu / MoTi It may also comprise at least any one selected from the group of conductive metals, or a combination of two or more thereof or other suitable material.

In addition, the gate insulating film 405 may be a silicon (Si) -based oxide film, a nitride film, or a compound including the same, a metal oxide film including an Al ₂ O ₃ , an organic insulating film, a low dielectric constant (low −). k) material having a value. For example, the gate insulating film 107 may include silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) Or combinations of two or more thereof or other suitable materials.

As the material for forming the channel region 407a, the conductive source region 407b and the drain region 407c, and the conductive pixel electrode region 407d extending from the drain region 407c, Silicon (Si) -based semiconductor film, IGZO-based oxide semiconductor film, compound semiconductor, carbon nanotube (carbon nano tube), graphene (graphene) is used.

At this time, the oxide semiconductor may be at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium And a material in which silicon (Si) is added to an oxide semiconductor containing zinc (Zn). For example, the active pattern 109a may be made of silicon-indium zinc oxide (Si-InZnO: SIZO) to which an indium zinc composite oxide (InZnO) is added with silicon ions.

The channel region 407a, the conductive source region 407b and the drain region 407c, and a material extending from the drain region 407c and forming the conductive pixel electrode region 407d are made of SIZO. In this case, the composition ratio of the content of silicon (Si) atoms to the total content of zinc (Zn), indium (In), and silicon (Si) atoms in the active layer may be about 0.001 wt% (wt%) to about 30 wt%. The higher the silicon (Si) atomic content, the stronger the role of controlling electron generation, so that the mobility may be lowered, but the stability of the device may be better.

On the other hand, the material forming the channel region 407a, the conductive source region 407b and the drain region 407c, and the conductive pixel electrode region 407d extending from the drain region 407c, Group I elements such as lithium (Li) or potassium (K), group II elements such as magnesium (Mg), calcium (Ca) or strontium (Sr), gallium (Ga), aluminum (Al), indium (In) or Group III elements such as yttrium (Y), group IV elements such as titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge), tantalum (Ta), vanadium (V), Group V elements such as niobium (Nb) or antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu) ), Lanthanum (Ln) such as gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) or ruthedium (Lu) A series element may be further included.

The source electrode 413a and the drain electrode 413b include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), and silver (Ag). , Silver alloy (Ag), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum (MoW), molybdenum (MoTi), copper It may also comprise at least any one selected from the group of conductive metals including / molitanium (Cu / MoTi) or a combination of two or more thereof or other suitable materials.

Further, the light blocking pattern 409 is arranged to block the channel region 407a including the channel region. In this case, the light blocking pattern 409 may be any material capable of shielding light. For example, any one of a group containing a metal-based material, Ni, Co, Cu, a copper alloy, a plastic-based material, and a metal alloy may be used. Use

Therefore, according to the display device array substrate to which the oxide thin film transistor according to the third embodiment of the present invention is applied, an X-ray ionizer and a photo used in the process by forming a light blocking pattern on the upper portion of the channel region By blocking the reaction of the oxide semiconductor by external light characteristics such as UV light used in the process and EUV light used in the cleaning process, the device characteristics of the oxide thin film transistor can be minimized to ensure stable device characteristics. .

Further, according to the array substrate to which the oxide thin film transistor according to the third embodiment of the present invention is applied, the conductive semiconductor can be applied to the pixel electrode by conducting the oxide semiconductor.

An array substrate for a display device to which the oxide thin film transistor according to the third exemplary embodiment of the present invention having the above structure is applied will be described in detail with reference to FIGS. 9A to 9F.

9A to 9F are cross-sectional views illustrating a manufacturing process of an array substrate for a display device to which an oxide thin film transistor according to a third exemplary embodiment of the present invention is applied.

Although not shown in the drawing, a first conductive material for a gate electrode is deposited on the substrate 401 by sputtering to form a first conductive layer (not shown), and a first photosensitive film (not shown) is coated thereon. Thereafter, the first photoresist layer (not shown) is patterned through a first mask process using a photolithography process technology to form a first photoresist layer pattern (not shown).

In this case, the substrate 401 may be made of silicon, glass, plastic or other suitable material.

In addition, as the first conductive layer (not shown), aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver Alloy (Ag), Gold (Au), Gold (Au alloy), Chromium (Cr), Titanium (Ti), Titanium alloys (Ti alloy), Molytungsten (MoW), Motitanium (MoTi), Copper / Molli It may also comprise at least any one selected from the group of conductive metals comprising titanium (Cu / MoTi) or a combination of two or more thereof or other suitable materials.

Next, referring to FIG. 9A, a gate electrode 403 is formed by selectively etching the first conductive layer using the first photoresist pattern (not shown) as an etching mask.

Subsequently, referring to FIG. 9B, the first photoresist layer pattern is removed, and a gate insulating layer 405 is formed on the entire surface of the substrate including the gate electrode 403. In this case, the gate insulating layer 405 may include a silicon (Si) -based oxide film, a nitride film, or a compound including the same, a metal oxide including Al ₂ O ₃ , an organic insulating film, and a low dielectric constant (low −). k) material having a value. For example, the a gate insulating film 307, silicon oxide (SiO _2), silicon nitride (SiNx), zirconium oxide (ZrO _2), hafnium oxide (HfO _2), titanium oxide (TiO _2), tantalum oxide ( Ta ₂ O _5), barium-strontium-titanium-one selected from the group consisting of oxygen compounds (Bi-Zn-Nb-O ) - oxygen compound (Ba-Sr-Ti-O ) and bismuth-zinc-niobium Or a combination of two or more thereof or other suitable material.

Next, referring to FIG. 9C, an active layer 407 is formed on the gate insulating layer 403. In this case, the active layer 407 is a layer for forming a channel through which electrons move between a source electrode (not shown) and a drain electrode (not shown), and is referred to as Low Temperature Poly Silicon (hereinafter referred to as LTPS). Alternatively, a silicon (Si) -based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nanotube, or graphene may be used instead of an amorphous silicon (a-Si) material.

At this time, the oxide semiconductor may be at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium And a material in which silicon (Si) is added to an oxide semiconductor containing zinc (Zn). For example, the active layer 109 may be formed of silicon indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to indium zinc complex oxide (InZnO).

When the active layer 407 is made of SIZO, the composition ratio of silicon (Si) atom content to the total content of zinc (Zn), indium (In), and silicon (Si) atoms in the active layer is about 0.001% by weight (wt%). ) To about 30 wt%. The higher the silicon (Si) atomic content, the stronger the role of controlling electron generation, so that the mobility may be lowered, but the stability of the device may be better.

On the other hand, the active layer 407, in addition to the above-described materials, Group I elements such as lithium (Li) or potassium (K), Group II elements such as magnesium (Mg), calcium (Ca) or strontium (Sr), Group III elements such as gallium (Ga), aluminum (Al), indium (In) or yttrium (Y), titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge) Group V elements such as group IV elements, tantalum (Ta), vanadium (V), niobium (Nb) or antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd) ), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolidium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium Lanthanum (Ln) -based elements such as (Yb) or ruthedium (Lu) may be further included.

Subsequently, after forming a light blocking layer (not shown) on the active layer 407, a second photosensitive film (not shown) is applied thereon, and then the second mask process using a photolithography process technology. After exposing and developing the photoresist film, the second photoresist film (not shown) is selectively patterned to form a second photoresist film pattern (not shown). In this case, the light blocking layer (not shown) may be any material capable of shielding external light. For example, any one of a group including a metal-based material, Ni, Co, Cu, and a plastic-based material may be used.

Next, referring to FIG. 9C, the light blocking layer (not shown) may be selectively removed using the second photoresist layer pattern as an etch mask, thereby forming an active layer on the gate insulating layer 307 above the gate electrode 403. A light blocking pattern 409 is formed on the channel region of 407.

Subsequently, the second photoresist layer pattern is removed and the active layer 407 is irradiated with X-ray light, UV light, or EUV light on the active layer 407 using the light blocking pattern 409 as a blocking mask. Make it angry. At this time, the channel region 407a in which light transmission is blocked by the light blocking pattern 409 becomes unconducted, and the remaining source region 407b, drain region 407c, and pixel electrode region 407d are Light is transmitted and becomes a conductor state.

Next, as shown in FIG. 9E, a second conductive layer 413 is formed on the entire surface of the substrate including the light blocking pattern 409, and a third photoresist film (not shown) is applied thereon. In this case, as the second conductive layer 413, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenum (MoTi), copper / molity titanium It may comprise at least any one selected from the group of conductive metals containing (Cu / MoTi) or a combination of two or more thereof or other suitable materials.

Subsequently, after exposing and developing the third photoresist film (not shown) through a third mask process using a photolithography process technology, the third photoresist film (not shown) is selectively patterned to form a third photoresist pattern (not shown). Form.

Next, as illustrated in FIG. 9F, the second conductive layer 413 is etched using the third photoresist pattern (not shown) as an etch mask, and then applied to each of the source region 407b and the drain electrode 407c. The source electrode 413a and the drain electrode 413b are formed in direct contact with each other.

Subsequently, the array substrate manufacturing process to which the oxide thin film transistor according to the third embodiment of the present invention is applied is completed by removing the third photoresist pattern (not shown).

Accordingly, according to the method of manufacturing an array substrate using the oxide thin film transistor according to the third embodiment of the present invention, an X-ray ionizer and a photo process are formed by forming a light blocking pattern on an upper portion of an active layer. By blocking the reaction of the oxide semiconductor by external light characteristics such as UV light used at the time and EUV light used at the cleaning process, the device characteristics of the oxide thin film transistor can be minimized to ensure stable device characteristics.

In addition, according to the method of manufacturing an array substrate to which the oxide thin film transistor according to the third embodiment of the present invention is applied, the conductive material is formed by conductorizing the characteristics of the remaining portions except the portion corresponding to the channel region in the oxide semiconductor constituting the active layer. The applied portion can be applied to the pixel electrode to simplify the process of manufacturing the array substrate for the display device.

In addition, an array substrate for a display device to which an oxide thin film transistor according to a fourth exemplary embodiment of the present invention is applied will be described with reference to FIG. 10.

10 is a schematic cross-sectional view of an array substrate for a display device to which an oxide thin film transistor according to a fourth exemplary embodiment of the present invention is applied.

An array substrate 500 for applying an oxide thin film transistor according to a fourth embodiment of the present invention includes a gate electrode 503 formed on a substrate 501, as shown in FIG. A gate insulating film 505 formed on the entire surface of the substrate including the gate electrode 503; From the non-conductive channel region 507a formed on the gate insulating film 505 above the gate electrode 403, the conductive source region 507b and the drain region 507c, and the drain region 507c. An extended and conductive pixel electrode region 507d; A light blocking pattern 509 formed on the channel region 507a; And a source electrode 513a formed on the conductive source region 507b.

Here, the display device array substrate 300 to which the oxide thin film transistor according to the fourth embodiment of the present invention is applied is a liquid crystal display (LCD), an organic luminescence diode (OLED); It may be applied to a flat panel display and the like.

The substrate 501 may include silicon, glass, plastic, or other suitable material.

As the gate electrode 503, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy) , Gold (Au), Au alloy, Chromium (Cr), Titanium (Ti), Titanium alloy (Ti alloy), Moly tungsten (MoW), Molaritanium (MoTi), Copper / Mortinium (Cu / MoTi It may also comprise at least any one selected from the group of conductive metals, or a combination of two or more thereof, or other suitable material.

In addition, the gate insulating layer 505 may include a silicon (Si) -based oxide film, a nitride film, or a compound including the same, a metal oxide including an Al ₂ O ₃ , an organic insulating film, and a low dielectric constant. k) material having a value. For example, the gate insulating film 107 may include silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) Or combinations of two or more thereof or other suitable materials.

The material for forming the channel region 507a, the conductive source region 507b and the drain region 507c, and the conductive pixel electrode region 507d extending from the drain region 507c may be used. Silicon (Si) -based semiconductor film, IGZO-based oxide semiconductor film, compound semiconductor, carbon nanotube (carbon nano tube), graphene (graphene) is used.

At this time, the oxide semiconductor may be at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium And a material in which silicon (Si) is added to an oxide semiconductor containing zinc (Zn). For example, the active pattern 109a may be made of silicon-indium zinc oxide (Si-InZnO: SIZO) to which an indium zinc composite oxide (InZnO) is added with silicon ions.

The material forming the channel region 507a, the conductive source region 507b and the drain region 507c, and the conductive pixel electrode region 507d extending from the drain region 507c is made of SIZO. In this case, the composition ratio of the content of silicon (Si) atoms to the total content of zinc (Zn), indium (In), and silicon (Si) atoms in the active layer may be about 0.001 wt% (wt%) to about 30 wt%. The higher the silicon (Si) atomic content, the stronger the role of controlling electron generation, so that the mobility may be lowered, but the stability of the device may be better.

On the other hand, the material forming the channel region 507a, the conductive source region 507b and the drain region 507c, and the conductive pixel electrode region 507d extending from the drain region 507c, Group I elements such as lithium (Li) or potassium (K), group II elements such as magnesium (Mg), calcium (Ca) or strontium (Sr), gallium (Ga), aluminum (Al), indium (In) or Group III elements such as yttrium (Y), group IV elements such as titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge), tantalum (Ta), vanadium (V), Group V elements such as niobium (Nb) or antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu) ), Lanthanum (Ln) such as gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) or ruthedium (Lu) A series element may be further included.

The source electrode 513a may be aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy). ), Gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenum (MoTi), copper / mortitanium (Cu / Or at least one selected from the group of conductive metals including MoTi) or a combination of two or more thereof, or other suitable material.

Further, the light blocking pattern 509 is disposed to block the channel region 507a including the channel region. In this case, the light blocking pattern 509 may be any material capable of shielding light. For example, any one of a group containing a metal-based material, Ni, Co, Cu, a copper alloy, a plastic-based material, and a metal alloy may be used. Use

Therefore, according to the array substrate for a display device to which the oxide thin film transistor according to the fourth embodiment of the present invention is applied, an X-ray ionizer and a photo which are used during a process by forming a light blocking pattern on an upper portion of a channel region, By blocking the reaction of the oxide semiconductor by external light characteristics such as UV light used in the process and EUV light used in the cleaning process, the device characteristics of the oxide thin film transistor can be minimized to ensure stable device characteristics. .

In addition, according to the array substrate to which the oxide thin film transistor according to the fourth embodiment of the present invention is applied, the conductive semiconductor can be applied as a pixel electrode by forming an oxide semiconductor. In particular, since the conductive oxide semiconductor is used as the drain electrode and the pixel electrode without forming the drain electrode, the aperture ratio as much as the area of the drain electrode can be secured.

An array substrate for a display device to which the oxide thin film transistor according to the fourth exemplary embodiment of the present invention having the above structure is applied will be described in detail with reference to FIGS. 11A through 11E.

11A through 11F are cross-sectional views illustrating fabrication processes of an array substrate for a display device to which an oxide thin film transistor according to a fourth exemplary embodiment of the present invention is applied.

Although not shown in the drawing, a first conductive material for a gate electrode is deposited on the substrate 501 by sputtering to form a first conductive layer (not shown), and a first photosensitive film (not shown) is coated thereon. Thereafter, the first photoresist layer (not shown) is patterned through a first mask process using a photolithography process technology to form a first photoresist layer pattern (not shown).

In this case, the substrate 501 may be made of silicon, glass, plastic or other suitable material.

In addition, as the first conductive layer (not shown), aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver Alloy (Ag), Gold (Au), Gold (Au alloy), Chromium (Cr), Titanium (Ti), Titanium alloys (Ti alloy), Molytungsten (MoW), Motitanium (MoTi), Copper / Molli It may also comprise at least any one selected from the group of conductive metals comprising titanium (Cu / MoTi) or a combination of two or more thereof or other suitable materials.

Next, referring to FIG. 11A, the first conductive layer is selectively etched using the first photoresist pattern (not shown) as an etching mask to form a gate electrode 503.

Subsequently, referring to FIG. 11B, the first photoresist layer pattern is removed and a gate insulating layer 505 is formed on the entire surface of the substrate including the gate electrode 503. In this case, the gate insulating film 505 may be a silicon (Si) -based oxide film, a nitride film, or a compound including the same, a metal oxide film including an Al ₂ O ₃ , an organic insulating film, and a low dielectric constant (low −). k) material having a value. For example, the a gate insulating film 307, silicon oxide (SiO _2), silicon nitride (SiNx), zirconium oxide (ZrO _2), hafnium oxide (HfO _2), titanium oxide (TiO _2), tantalum oxide ( Ta ₂ O _5), barium-strontium-titanium-one selected from the group consisting of oxygen compounds (Bi-Zn-Nb-O ) - oxygen compound (Ba-Sr-Ti-O ) and bismuth-zinc-niobium Or a combination of two or more thereof or other suitable material.

Next, referring to FIG. 11C, an active layer 507 is formed on the gate insulating layer 503. In this case, the active layer 507 is a layer for forming a channel through which electrons move between a source electrode (not shown) and a drain electrode (not shown), and is referred to as low temperature polysilicon (hereinafter referred to as LTPS). Alternatively, a silicon (Si) -based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nanotube, or graphene may be used instead of an amorphous silicon (a-Si) material.

At this time, the oxide semiconductor may be at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium And a material in which silicon (Si) is added to an oxide semiconductor containing zinc (Zn). For example, the active layer 109 may be formed of silicon indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to indium zinc complex oxide (InZnO).

When the active layer 507 is made of SIZO, the composition ratio of silicon (Si) atom content to the total content of zinc (Zn), indium (In), and silicon (Si) atoms in the active layer is about 0.001 wt% (wt%). ) To about 30 wt%. The higher the silicon (Si) atomic content, the stronger the role of controlling electron generation, so that the mobility may be lowered, but the stability of the device may be better.

Meanwhile, the active layer 507 may be a group I element such as lithium (Li) or potassium (K), a group II element such as magnesium (Mg), calcium (Ca), or strontium (Sr), in addition to the above materials. Group III elements such as gallium (Ga), aluminum (Al), indium (In) or yttrium (Y), titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge) Group V elements such as group IV elements, tantalum (Ta), vanadium (V), niobium (Nb) or antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd) ), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolidium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium Lanthanum (Ln) -based elements such as (Yb) or ruthedium (Lu) may be further included.

Subsequently, after forming a light blocking layer (not shown) on the active layer 507, a second photosensitive film (not shown) is applied thereon, and then the second mask process using a photolithography process technology. After exposing and developing the photoresist film, the second photoresist film (not shown) is selectively patterned to form a second photoresist film pattern (not shown). In this case, the light blocking layer (not shown) may be any material capable of shielding external light. For example, any one of a group including a metal-based material, Ni, Co, Cu, and a plastic-based material may be used.

Next, referring to FIG. 11C, the light blocking layer (not shown) may be selectively removed by using the second photoresist pattern as an etch mask, thereby forming an active layer on the gate insulating layer 505 above the gate electrode 503. The light blocking pattern 509 is formed on the channel region of 507.

Subsequently, the second photoresist layer pattern is removed, and the active layer 507 is formed by irradiating X-ray light, UV light, or EUV light to the active layer 507 using the light blocking pattern 509 as a blocking mask. Make it angry. At this time, the channel region 507a in which light transmission is blocked by the light blocking pattern 509 becomes unconducted, and the remaining source region 507b, the drain region 507c, and the pixel electrode region 507d are Light is transmitted and becomes a conductor state.

Next, as illustrated in FIG. 11D, a second conductive layer 511 is formed on the entire surface of the substrate including the light blocking pattern 509, and a third photosensitive film (not shown) is coated thereon. In this case, as the second conductive layer 511, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenum (MoTi), copper / molity titanium It may comprise at least any one selected from the group of conductive metals containing (Cu / MoTi) or a combination of two or more thereof or other suitable materials.

Subsequently, after exposing and developing the third photoresist film (not shown) through a third mask process using a photolithography process technology, the third photoresist film (not shown) is selectively patterned to form a third photoresist pattern (not shown). Form.

Next, as illustrated in FIG. 9E, the source electrode 511a which directly contacts the source region 507b by etching the second conductive layer 511 using the third photoresist pattern (not shown) as an etching mask. ). At this time, the portion of the second conductive layer 511 in the drain region 507c is also removed.

Subsequently, the array substrate manufacturing process using the oxide thin film transistor according to the fourth embodiment of the present invention is completed by removing the third photoresist pattern (not shown).

Therefore, according to the array substrate manufacturing method using the oxide thin film transistor according to the fourth embodiment of the present invention, by forming a light blocking pattern on the active layer, X-ray ionizer and photo process to be used during the process By blocking the reaction of the oxide semiconductor by external light characteristics such as UV light used at the time and EUV light used at the cleaning process, the device characteristics of the oxide thin film transistor can be minimized to ensure stable device characteristics.

In addition, according to the method of manufacturing an array substrate to which the oxide thin film transistor according to the fourth embodiment of the present invention is applied, the conductive material is formed by conductorizing the characteristics of the remaining portions except the portion corresponding to the channel region of the oxide semiconductor constituting the active layer. The applied portion can be applied to the pixel electrode to simplify the process of manufacturing the array substrate for the display device. In particular, since the conductive oxide semiconductor is used as the drain electrode and the pixel electrode without forming the drain electrode, the aperture ratio as much as the area of the drain electrode can be secured.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, those of ordinary skill in the art to which the present invention pertains will be able to vary the components of the thin film transistor of the present invention, the structure may also be modified in various forms.

It will be appreciated that the oxide thin film transistor of the present invention can be applied not only to liquid crystal display devices and organic light emitting display devices but also to memory devices and logic devices. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

100: oxide thin film transistor 103a: gate electrode
107: gate insulating film 109a: active pattern
113a: etch stop layer pattern 117a: source electrode 117b: drain electrode 123a: light blocking pattern

Claims (30)

A gate electrode formed on the substrate;
A gate insulating film formed on the entire surface of the substrate including the gate electrode;
An active pattern formed on the gate insulating film above the gate electrode;
An etch stop layer pattern formed on the active pattern;
A source electrode and a drain electrode formed on the active pattern and spaced apart from each other;
A passivation film formed on the entire surface of the substrate including the source electrode and the drain electrode;
And a light blocking pattern formed on the passivation layer on the active pattern. The thin film transistor of claim 1, wherein the light blocking pattern uses any one of a group including a metal-based material, Ni, Co, Cu, a copper alloy, and a plastic-based material. The method of claim 1, wherein the active pattern is a silicon (Si) -based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, carbon nanotube (carbon nano tube), graphene (graphene) characterized in that using Thin film transistor. The thin film transistor of claim 1, wherein the light blocking pattern is applied as an upper gate of a double gate structure. A gate electrode formed on the substrate;
A gate insulating film formed on the entire surface of the substrate including the gate electrode;
An active pattern formed on the gate insulating film above the gate electrode;
An etch stop layer pattern formed on the active pattern;
A source electrode and a drain electrode formed on the active pattern and spaced apart from each other;
A passivation film formed on the entire surface of the substrate including the source electrode and the drain electrode, the passivation film exposing the drain electrode;
A light blocking pattern formed on the passivation film above the active pattern;
And a conductive semiconductor pattern formed on the passivation layer and electrically connected to the exposed drain electrode. The array substrate of claim 5, wherein the light blocking pattern is any one selected from the group consisting of metal, Ni, Co, Cu, and plastic materials. The method of claim 5, wherein the active pattern is a silicon (Si) -based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nanotube, or graphene. Array board for display device. The method of claim 5, wherein the conductive semiconductor pattern is a silicon (Si) -based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nanotube, graphene Array substrate for display device, characterized in that using a). A gate electrode formed on the substrate;
A gate insulating film formed on the entire surface of the substrate including the gate electrode;
A non-conductive channel region formed on the gate insulating film above the gate electrode, a conductive source region and a drain region, and a pixel electrode region extending from the drain region and conductive;
A light blocking pattern formed on the channel region;
And a source electrode and a drain electrode formed on the conductive source and drain regions and spaced apart from each other. The array substrate of claim 9, wherein the light blocking pattern comprises any one of a group including a metal, Ni, Co, Cu, and plastic materials. 10. The semiconductor device of claim 9, wherein the non-conductive channel region, the conductive source region and the drain region, and the conductive pixel electrode region extending from the drain region are formed of a silicon (Si) series semiconductor film, an IGZO series, and the like. An array substrate for a display device, comprising an oxide semiconductor film, a compound semiconductor, a carbon nano tube, and graphene. A gate electrode formed on the substrate;
A gate insulating film formed on the entire surface of the substrate including the gate electrode;
A non-conductive channel region formed on the gate insulating film above the gate electrode, a conductive source region and a drain region, and a pixel electrode region extending from the drain region and conductive;
A light blocking pattern formed on the channel region;
And a source electrode formed on the conductive source region. The array substrate of claim 12, wherein the light blocking pattern comprises any one of a group including a metal-based material, Ni, Co, Cu, and plastic-based materials. 10. The semiconductor device of claim 9, wherein the non-conductive channel region, the conductive source region and the drain region, and the conductive pixel electrode region extending from the drain region are formed of a silicon (Si) series semiconductor film, an IGZO series, and the like. An array substrate for a display device, comprising an oxide semiconductor film, a compound semiconductor, a carbon nano tube, and graphene. The display device array substrate of claim 12, wherein the pixel electrode region simultaneously serves as a drain electrode and a pixel electrode. Forming a gate electrode on the substrate;
Forming a gate insulating film on an entire surface of the substrate including the gate electrode;
Forming an active pattern on the gate insulating layer above the gate electrode;
Forming an etch stop layer pattern on the active pattern;
Forming a source electrode and a drain electrode spaced apart from each other on the active pattern;
Forming a passivation film on an entire surface of the substrate including the source electrode and the drain electrode;
And forming a light blocking pattern on the passivation layer on the active pattern. The method of claim 16, wherein the light blocking pattern uses any one of a group including a metal-based material, Ni, Co, Cu, and plastic-based materials. The method of claim 16, wherein the active pattern is a silicon (Si) -based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, carbon nanotube (Carbon nano tube), graphene (graphene) characterized in that using Thin film transistor manufacturing method. The method of claim 16, wherein the light blocking pattern is applied as an upper gate of a double gate structure. Forming a gate electrode on the substrate;
Forming a gate insulating film on an entire surface of the substrate including the gate electrode;
Forming an active pattern on the gate insulating layer above the gate electrode;
Forming an etch stop layer pattern on the active pattern;
Forming a source electrode and a drain electrode spaced apart from each other on the active pattern;
Forming a passivation film exposing the drain electrode on an entire surface of the substrate including the source electrode and the drain electrode;
Forming a light blocking pattern on the passivation layer on the active pattern;
And forming a conductive semiconductor pattern electrically connected to the exposed drain electrode on the passivation layer. The method of claim 20, wherein the light blocking pattern comprises any one of a group including a metal-based material, Ni, Co, Cu, and plastic-based materials. The method of claim 20, wherein the active pattern is a silicon (Si) -based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, carbon nanotube (carbon nano tube), graphene (graphene) characterized in that using Method of manufacturing array substrate for display device. 21. The method of claim 20, wherein the conductive semiconductor pattern is a silicon (Si) -based semiconductor film, IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nanotube (graphene), graphene Method for manufacturing an array substrate for a display device, characterized in that using a). Forming a gate electrode on the substrate;
Forming a gate insulating film on an entire surface of the substrate including the gate electrode;
Forming an oxide semiconductor layer on the gate insulating film above the gate electrode;
Irradiating the oxide semiconductor layer with light to form a non-conductive channel region, a conductive source region and a drain region, and a pixel electrode region extending from the drain region and having a conductivity;
Forming a light blocking pattern on the channel region;
And forming source and drain electrodes spaced apart from each other on the conductive source and drain regions. 25. The method of claim 24, wherein the light blocking pattern uses any one of a group including a metal-based material, Ni, Co, Cu, and a plastic-based material. 25. The semiconductor device according to claim 24, wherein the non-conductive channel region, the conductive source region and the drain region, and the conductive pixel electrode region extending from the drain region are formed of a silicon (Si) series semiconductor film, an IGZO series, and the like. An oxide semiconductor film, a compound semiconductor, a carbon nano tube, and graphene are used, the method of manufacturing an array substrate for a display device. Forming a gate electrode on the substrate;
Forming a gate insulating film on an entire surface of the substrate including the gate electrode;
Forming a non-conductive channel region, a conductive source region and a conductive pixel electrode region on the gate insulating film above the gate electrode;
Forming a light blocking pattern on the channel region;
Forming a source electrode on the conductive source region; and a method of manufacturing an array substrate for a display device. 28. The method of claim 27, wherein the light blocking pattern uses any one of a group including a metal, Ni, Co, Cu, and plastic materials. 28. The semiconductor device of claim 27, wherein the non-conductive channel region, the conductive source region and the drain region, and the conductive pixel electrode region extending from the drain region are formed of a silicon (Si) series semiconductor film, an IGZO series, and the like. An oxide semiconductor film, a compound semiconductor, a carbon nano tube, and graphene are used, the method of manufacturing an array substrate for a display device. 28. The method of claim 27, wherein the pixel electrode region serves as a drain electrode and a pixel electrode at the same time.

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