KR20140029823A - Semiconductor integrated circuit apparatus having new interconnection structure - Google Patents

Abstract

A semiconductor integrated circuit apparatus includes a first semiconductor plane in which a plurality of first signal lines to transfer a first level signal and a plurality of second signal lines to transfer a second level signal having a level opposite to a level of the first level signal are placed; and a second semiconductor plane disposed on the first semiconductor plane and formed thereon with a plurality of third signal lines to transfer the first level signal and a plurality of fourth signal lines to transfer the second level signal, wherein a part of the first signal lines faces a part of the fourth signal lines to cancel a signal, and a part of the second signal lines faces a part of the third signal lines to cancel the signal.

Description

Semiconductor Integrated Circuit Apparatus Having New Interconnection Structure

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit devices, and more particularly to an interconnect structure of a sense amplifier.

The semiconductor memory device is provided with a sense amplifier to detect the state of the stored data. These sense amplifiers depend on fast sensing, fast data driving and low leakage current.

As semiconductor densities increase in current density, not only bit line pairs (hereinafter referred to as BL / BLB) but also segment input / output line pairs (hereinafter referred to as SIO / SIOB), local input / output line pairs (hereinafter referred to as LIO / LIOB), and global Layered with input / output line pairs (hereinafter referred to as GIO / GIOB).

Currently, sense amplifiers are installed between BL / BLB and SIO / SIOB and between LIO / LIOB and GIO / GIOB to sense data.

Typical sense amplifiers include latch blocks, equalization blocks, and column select blocks.

The latch block is positioned between the bit line and the bit line bar and may be configured by connecting NMOS transistors and PMOS transistors in a latch form.

The equalization block is connected between the bit line and the bit line bar and serves to make the BL bit line and the bit line bar equipotential in response to the equalization signal. The column select block may be configured to switch the signals of the bit line and the bit line bar to the data transfer line in response to the column select signal.

The latch block, equalization / precharge block, and column select block may all be composed of MOS transistors, and the gate, source, and drain of the MOS transistors may be properly connected by a metal line to have the sense amplifier structure described above. .

However, as the integration density of semiconductor memory devices increases, the number of metal lines arranged in a limited space increases.

In particular, since the first metal line M0 constitutes a true line, a bar line, and other connection lines, it is difficult to secure the line width and spacing of these lines in a limited space.

Further, when the first metal line M0 is disposed at such a high integration density, an area overlapping with the second metal line M1 positioned in the upper layer is increased, thereby increasing the coupling capacitance.

SUMMARY OF THE INVENTION The present invention provides a semiconductor integrated circuit device capable of reducing coupling capacitance.

In an embodiment, a semiconductor integrated circuit device may include a plurality of first signal lines for transmitting a first level signal and a plurality of second signal lines for transmitting a second level signal having a level opposite to the first level signal. The first semiconductor plane disposed thereon, and a plurality of third signal lines positioned on the first semiconductor plane and transmitting the first level signal, and a plurality of fourth signal lines transmitting the second level signal, A second semiconductor plane, wherein some of the plurality of first signal lines are disposed to face some of the plurality of fourth signal lines for signal cancellation, and some of the plurality of second signal lines are signal Disposed to face some of the plurality of third signal lines for cancellation.

Each of the plurality of first to fourth signal lines includes a shifting region, and the plurality of first to fourth signal lines may be configured to be moved by a predetermined distance within the semiconductor plane by the shifting region. Can be.

In addition, the first and second semiconductor planes may include at least one contact region connected to each of the plurality of first to fourth signal lines, and the plurality of first to fourth signal lines may correspond The display apparatus may further include a plurality of connecting regions drawn from each of the first to fourth signal lines for connection with a corresponding contact region positioned on the semiconductor plane.

The first and the first and second signal lines to face the rest of the plurality of first signal lines, the rest of the plurality of second signal lines, the rest of the plurality of third signal lines, and the rest of the plurality of fourth signal lines. The method may further include a shielding line disposed on each of the second semiconductor planes.

In addition, the semiconductor integrated circuit device according to another embodiment of the present invention is a wiring interconnection structure for primarily connecting transistors constituting the sense amplifier, and includes a plurality of first true lines and the first true line. A first plane on which a plurality of first bar lines having a level opposite to the first true line are disposed, and a plurality of second true lines and a plurality of second bar lines located on the first semiconductor plane; It includes a second plane disposed. At this time, a part of the first true line is disposed to face a part of the second bar line, and a part of the first bar line is disposed to face a part of the second true line.

By dividing the metal line plane into two layers to disperse the metal lines, not only can the placement margin of the metal line be improved, but also the signal lines can be offset in the distributing arrangement, thereby reducing the coupling capacitance. Can be. Accordingly, noise and speed of the signal line can be improved.

1 is a block diagram illustrating the concept of an embodiment of the present invention.
2 is a schematic perspective view of a semiconductor integrated circuit device according to an embodiment of the present invention.
3 is a layout diagram of a first sub metal line plane according to an embodiment of the present invention.
4 is a layout diagram of a second sub metal line plane according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only the embodiments are to make the disclosure of the present invention complete, the scope of the invention to those skilled in the art It is provided to fully understand the present invention, the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

In the present embodiment, as shown in FIG. 1, the first metal line plane M0 is formed as the first metal line plane M0 so as to secure the line width and the distance between the true line and the bar line constituting the first metal line plane M0. The sub metal line plane M0_1 and the second sub metal line plane M0_2 may be divided and configured.

That is, in the present embodiment, instead of the first metal line plane M0 and the second metal line plane M1 that are conventionally stacked, the first sub metal line plane M0_1, the second sub metal line plane M0_2, and the second metal line plane M0_2 may be formed. Two metal lines are stacked on the plane M1 to form metal lines constituting the sense amplifier. In this case, the present embodiment and the conventional second metal line plane M1 may be positioned at substantially the same level as in FIG. 1, or the second sub metal line plane M0_2 of the present embodiment may be the second metal line. It may be located at the same level as the plane M1.

In addition, as shown in FIG. 2, each of the lines positioned in the first sub metal line plane M0_1 and the second sub metal line plane M0_2 may provide a mutually canceled signal to reduce the occurrence of coupling capacitance. Lines to transfer are arranged to face each other.

In more detail, the first true line M_T01 disposed on the first sub metal line plane M0_1 may be disposed to correspond to the second bar line M_B02 disposed on the second sub metal line plane M0_2. This results in less coupling capacitance since signal cancellation between the opposing lines occurs.

In addition, the shifting region 110 and the first and second true lines M_T01 and M_T02 and the first and second bar lines M_B01 and M_B02 may prevent overlap between the same signal lines without disconnection. It includes a connecting region.

The first and second true lines M_T01 and M_T02 and the first and second bar lines M_B01 and M_B02 are positioned by the shifting region 110 in an upper or lower row on the same plane. You can change it.

Similarly, the first and second true lines M_T01 and M_T02 and the first and second bar lines M_B01 and M_B02 are positioned by the connecting region 120 in the upper or lower rows on the same plane. You can change it. In addition, the connecting region 120 connects the metal lines formed on the upper and lower metal planes with the contact region 130.

As described above, the first and second true lines M_T01 and M_T02 and the first and second bar lines M_B01 and M_B02 are formed on the plane of the first metal line even if the position change is performed so as to offset each other. The contact position with the wiring line and the contact position with the conductive region formed in the lower substrate may be fixed. Accordingly, the connecting region 120 is withdrawn from portions of the first and second true lines M_T01 and M_T02 and the first and second bar lines M_B01 and M_B02 that are repositioned, so as to contact the contact region 130. It may be configured to be connected.

In addition, since the first and second true lines M_T01 and M_T02 and the first and second bar lines M_B01 and M_B02 formed on one plane are formed by separating the two layers, the line density is higher than in the related art. relaxed. Accordingly, the shielding line 140 may be additionally installed in regions where line densities of the first and second sub metal line planes M_01 and M_02 are relaxed.

In this case, the shielding line 140 is formed on the first and second sub metal line planes M_01 and M_02, so that the metal line corresponding to the other metal line planes facing each other does not exist (to face the metal line). ) Can be arranged arbitrarily. For example, a power voltage may be applied to the shielding line 140. Thus, further coupling capacitance can be reduced.

FIG. 3 is a layout diagram showing a first sub metal line plane M_01 according to an embodiment of the present invention, and FIG. 4 is a layout diagram showing a second sub metal line plane M_02 according to an embodiment of the present invention. to be.

Referring to FIGS. 3 and 4, as the true line and the bar line formed of the first metal line are divided into the first and second sub metal line planes M_01 and M_02, the first and second sub metal lines are formed. True lines M_T01 and M_T02 and bar lines M_B01 and M_B02 formed in the planes M_01 and M_02 may be relatively relaxed.

In addition, the true lines M_T01 and M_T02 and the bar lines M_B01 and M_B02 formed in the first and second sub metal line planes M_01 and M_02 are mutually connected by the shifting region 110 and the connecting region 120. The opposite signal lines may be disposed to face each other, and when the true lines M_T01 and M_T02 and the bar lines M_B01 and M_B02 are disposed alone, the shielding line may be additionally disposed in the opposite plane to form a coupling. Capacitance can be reduced. As such, according to the present embodiment, by dividing the metal line plane into two layers, by distributing the metal lines, not only can the placement margin of the metal line be improved, but also the signal lines are offset in the distributing arrangement. By doing so, it is possible to reduce the coupling capacitance. Accordingly, noise and speed of the signal line can be improved.

As described above, embodiments of the present invention have been described with reference to the accompanying drawings, but those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that it can be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

M0_1: first sub metal line plane M0_2: second sub metal line plane
M0: first metal line plane M1: second metal line plane
M_T01, M_T02: True line M_B01, M_B02: Bar line
110: shifting area 120: connecting area
130: contact area 140: shielding line

Claims (10)

A first semiconductor plane having a plurality of first signal lines transferring a first level signal and a plurality of second signal lines transferring a second level signal at a level opposite to the first level signal; And
A second semiconductor plane positioned on the first semiconductor plane and including a plurality of third signal lines transmitting the first level signal and a plurality of fourth signal lines transmitting the second level signal;
Some of the plurality of first signal lines are disposed to face some of the plurality of fourth signal lines for signal cancellation,
And some of the plurality of second signal lines are disposed to face some of the plurality of third signal lines for signal cancellation. The method of claim 1,
Each of the plurality of first to fourth signal lines includes a shifting region, and the plurality of first to fourth signal lines are configured to be moved by a predetermined distance within the semiconductor plane by the shifting region. Integrated circuit devices. The method of claim 1,
And a contact region for correspondingly connecting the first through fourth signal lines of the first semiconductor plane and the first through fourth signal lines of the second semiconductor plane, respectively. 5. The method of claim 4,
The plurality of first to fourth signal lines further include a plurality of connecting regions drawn from each of the first to fourth signal lines for connection with the corresponding contact region located on the semiconductor plane. Device. The method of claim 1,
The first and the first and second signal lines to face the rest of the plurality of first signal lines, the rest of the plurality of second signal lines, the rest of the plurality of third signal lines, and the rest of the plurality of fourth signal lines. And a shielding line respectively disposed in the second semiconductor plane. A semiconductor integrated circuit device comprising a lower wiring for primarily connecting transistors constituting a sense amplifier and an upper wiring for connecting the lower wirings.
The lower wirings include a plurality of first and second true lines and first and second bar lines.
The plurality of first true lines and the plurality of first bar lines having a level opposite to the first true line are located in a first plane,
The plurality of second second true lines and the plurality of second bar lines are located in a second plane on the first semiconductor plane,
A portion of the first true line is disposed to face a portion of the second bar line, and a portion of the first bar line is disposed to face a portion of the second true line. The method according to claim 6,
Each of the plurality of first and second true lines and the plurality of first and second bar lines includes a shifting region, wherein the plurality of first and second true lines and the plurality of first lines are shifted by the shifting region. And the second bar line is configured to be moved by a distance within the plane. The method according to claim 6,
And the first and second planes include a plurality of contact regions connected to the plurality of first and second true lines and the plurality of first and second bar lines, respectively. The method of claim 8,
The plurality of first and second true lines and the plurality of first and second bar lines are the plurality of first and second true lines and the plurality of first lines for connection with corresponding contact regions located on a corresponding plane. And at least one connecting region drawn from each of the first and second bar lines. The method of claim 7, wherein
The first and second surfaces to face the remainder of the plurality of first true lines, the remainder of the plurality of second true lines, the remainder of the plurality of first bar lines and the remainder of the plurality of second true lines. And a shielding line disposed in the second plane, respectively.

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