KR20140004271A - Local sense amp structure and semiconductor memory device having the same - Google Patents

Abstract

The present technology relates to a local sense amplifier structure and a semiconductor integrated circuit device including the same. The semiconductor integrated circuit device includes a semiconductor substrate which includes an active reserve area and a dummy active reserve area which is arranged near the active reserve area, an active area which includes the active reserve area and the dummy active reserve area on the semiconductor substrate, a plurality of signal lines which are arranged on the active area, and a contact part which electrically connects the signal line to the active area in an overlap area between the active area and at least one signal line selected among the signal lines.

Description

Local sense amplifier structure and semiconductor integrated circuit device including the same {Local Sense Amp Structure and Semiconductor Memory Device Having the Same}

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a local sense amplifier structure and a semiconductor memory device including the same.

The semiconductor memory device is provided with a sense amplifier to detect the state of the stored data. These sense amplifiers depend on fast sensing, fast data driving and low leakage current.

As the integration density increases, semiconductor memory devices are layered into not only bit lines (hereinafter referred to as BL / BLB) but also global input / output lines (hereinafter referred to as GIO / GIOB) and local input / output lines (hereinafter referred to as LIO / LIOB). In addition, a local sense amplifier is generally installed between BL / BLB and LIO / LIOB or between LIO / LIOB and GIO / GIOB.

1 is a layout diagram illustrating a region of a general local sense amplifier.

As shown in FIG. 1, the local sense amplifier 10 includes an active region 20 and a dummy active region 30. Elements (not shown) to be formed on the dummy active region 30 and the dummy active region 30 thereafter are positioned in the empty local sense amplifier region 10 remaining after the active region 20 is formed, The constituent elements are provided to prevent pattern defects caused by the empty areas.

The gate line 40 is disposed above the active region 20 to be parallel to the long axis of the active region 20. The dummy gate line 42 is also formed in the dummy active region 30.

A plurality of bit line pairs BL / BLB are disposed on the active region 20 and the dummy active region 30 to be substantially orthogonal to the gate line 40.

The selected bit line BL or BLB and the active region 20 are electrically connected to each other.

In this case, the electrical connection between the selected BL / BLB and the active region 20 is implemented by the contact C. Since the contact C is formed in the limited active region 20, the contact C / B will be formed in a minimum number and area. This, in turn, leads to an increase in the bit line contact resistance.

Accordingly, the present invention provides a local sense amplifier structure capable of reducing contact resistance and a semiconductor integrated circuit device including the same.

A semiconductor integrated circuit device according to an embodiment of the present invention includes a semiconductor substrate including an active predetermined region and a dummy active predetermined region disposed adjacent to the active predetermined region, the active predetermined region of the semiconductor substrate, and the dummy active scheduled The signal line and the active area in an area overlapping the active area with an active area formed to include an area, a plurality of signal lines disposed on the active area, and at least one signal line selected from the plurality of signal lines; A contact portion formed for electrical connection between the regions.

In addition, the local sense amplifier structure according to another embodiment of the present invention, a semiconductor substrate including an active predetermined region for the light control portion and a dummy active predetermined region disposed adjacent to the active predetermined region, the active predetermined region of the semiconductor substrate An active region for a light control part formed to include the dummy active predetermined region, a gate line disposed on the active region, extending in a first direction, and disposed on the active region in which the gate line is disposed; A plurality of bit line pairs arranged in a second direction orthogonal to a first direction, and a bit line contact unit connecting the bit line pair selected from the plurality of bit line pairs to the active region, with respect to the gate line; do.

It may be formed over the entire overlapping area of the selected bit line pair and the active region.

 The active area of the circuit constituting the local sense amplifier is extended to include an adjacent dummy active area, thereby increasing the overlap area between the bit line and the active area, and providing a contact part corresponding to the overlap area, thereby improving contact resistance. can do

1 is a layout diagram of a portion of a typical local sense amplifier.
2 is a circuit diagram of a local sense amplifier according to an embodiment of the present invention.
3 is a layout diagram of a write operation controller of the local sense amplifier of FIG. 2.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only the embodiments are to make the disclosure of the present invention complete, the scope of the invention to those skilled in the art It is provided to fully understand the present invention, the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

2 is a circuit diagram of a local sense amplifier according to an embodiment of the present invention.

Referring to FIG. 2, the local sense amplifier circuit 100 includes an amplifier circuit unit 110 and a write operation controller 120.

The amplifying circuit unit 110 and the write operation control unit 120 are each connected between a lower input / output line pair, for example, a bit line pair (SIO / SIOB), and an upper input / output line pair, for example, a local input / output line (LIO / LIOB). Can be connected to.

The amplifier circuit unit 110 includes first to fifth NMOS transistors 111 to 115. The ground voltage VSS is applied to a source of the first NMOS transistor 111.

The amplifier circuit 110 is driven in response to the read control signal RD controlling the read operation of the semiconductor memory device. , And the fifth transistors 111, 114, and 115 are turned on. At this time, the logic state of the data transferred from the memory core (not shown) to the bit line BL is at a high level, and the logic state of the data transferred from the memory core to the bit line bar BLB is at a low level. ), The third NMOS transistor 113 is turned on so that the potential of the local input / output line bar LIOB is amplified to a low level. Thus, the potentials of the local input / output line pair are amplified by a predetermined potential difference.

The write operation controller 120 is enabled in response to the write control signal WE which is an inverted signal of the read control signal RD. That is, the NMOS transistors 121 and 122 included in the write operation control circuit bit the data transmitted to the local input / output line pair LIO / LIOB in response to the write control signal WE activated to the high level. It acts as a switch for transferring to a line pair (BL / BLB).

3 is a block diagram illustrating an arrangement of a write operation controller of the local sense amplifier of FIG. 2.

The write operation controller 120 of the local sense amplifier includes an active region 200, a gate line 210, and a plurality of bit line pairs BL / BLB.

The active region 200 may be formed in an area defined by the active predetermined area A and the dummy active predetermined area B. FIG. The active region 200 may be, for example, an impurity region formed on a semiconductor substrate (not shown).

The gate line 210 is disposed on the active region 200. The gate line 210 may extend along the long direction of the active region 200. The conventional gate line 210 is positioned in the active predetermined area A. However, in the present embodiment, since the active area 200 extends to the dummy active predetermined area B, for example, the active predetermined area A is disposed. And a vicinity of an interface of the dummy active predetermined area B. FIG.

The plurality of bit line pairs BL / BLB extend in a direction substantially perpendicular to the gate line 210 on the active region 200. The plurality of bit line pairs BL / BLB may be configured by alternately arranging bit lines BL and bit line bars BLB, and they may be arranged at regular intervals.

In this case, a line selected from among the plurality of bit line pairs BL / BLB is connected to a bit line selected from the pair of bit lines BL / BLB and connected to the transistor such as the write operation controller 120 of FIG. 2. It is in contact with the region 200. The contacted area will be referred to as a bit line contact part CT. The bit line contact portion CT may be disposed on both sides of the gate line 210.

In the present embodiment, as the active region 200 is formed to extend to the dummy active predetermined region B, the area of the active region 200 is substantially increased. Accordingly, the overlap area of the bit line pair BL / BLB and the active region 200 is also relatively increased. Accordingly, in the present exemplary embodiment, the bit line contact portion CT is formed to have a size of an overlap area between the bit line pair BL / BLB and the active region 200. As such, when the area of the bit line contact portion CT is increased, the contact resistance is reduced, thereby improving the characteristics of the local sense amplifier.

In the present embodiment, for example, it is shown that the bit line contact portion CT is formed for every four bit line pairs, but is not limited to the above rule.

In addition, although the active region 200 of the write operation controller 120 shown in the present embodiment is not shown in the drawing, a plurality of the active regions 200 may be provided in succession. It will be apparent to those skilled in the art that the electrical connection with the other active regions arranged in FIG. In addition, the other active region may be formed to extend to the dummy active region as in the present exemplary embodiment.

As described in detail above, according to the present embodiment, the active area of the circuit part constituting the local sense amplifier is formed to extend to include an adjacent dummy active area, thereby increasing the overlap area between the bit line and the active area and increasing the overlap. By providing a contact portion corresponding to the area, the contact resistance can be improved.

120: light operation control unit 200: active area
210: gate line BL / BLB: bit line pair

Claims (8)

A semiconductor substrate including an active predetermined region and a dummy active predetermined region disposed adjacent to the active predetermined region;
An active region formed to include the active predetermined region and the dummy active predetermined region of the semiconductor substrate;
A plurality of signal lines disposed on the active region; And
And at least one signal line selected from the plurality of signal lines and a contact portion formed in an overlapping region of the active region for electrical connection between the signal line and the active region. The method of claim 1,
The contact portion includes:
And a total area overlapping the active region, the at least one selected signal line, and an insulating layer therebetween. 3. The method of claim 2,
And the signal line is a bit line and a bit line bar. The method of claim 1,
And a gate line positioned between the active region and the plurality of signal lines and disposed above the active region in a form orthogonal to the plurality of signal lines. 5. The method of claim 4,
And the contact portion is disposed at both sides of the gate line. A semiconductor substrate including an active planar region for a light control unit and a dummy active planar region disposed adjacent to the active planar region;
An active region for a light control portion formed to include the active predetermined region and the dummy active predetermined region of the semiconductor substrate;
A gate line disposed on the active region and extending in a first direction;
A plurality of bit line pairs disposed on the active region in which the gate lines are disposed and arranged along a second direction orthogonal to the first direction; And
And a bit line contact unit configured to connect between the bit line pair selected from the plurality of bit line pairs and the active region around the gate line. The method according to claim 6,
The bit line contact portion,
And a local sense amplifier structure formed over the entire overlapping area of the selected bit line pair and the active region. The method according to claim 6,
And the gate line is formed near a boundary between the active active area and the dummy active predetermined area.

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