KR20140023506A - Light emitting device - Google Patents

Light emitting device Download PDF

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Publication number
KR20140023506A
KR20140023506A KR1020120089371A KR20120089371A KR20140023506A KR 20140023506 A KR20140023506 A KR 20140023506A KR 1020120089371 A KR1020120089371 A KR 1020120089371A KR 20120089371 A KR20120089371 A KR 20120089371A KR 20140023506 A KR20140023506 A KR 20140023506A
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KR
South Korea
Prior art keywords
layer
electrode
light emitting
semiconductor layer
conductive semiconductor
Prior art date
Application number
KR1020120089371A
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Korean (ko)
Inventor
최운경
이태림
Original Assignee
엘지이노텍 주식회사
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Priority to KR1020120089371A priority Critical patent/KR20140023506A/en
Publication of KR20140023506A publication Critical patent/KR20140023506A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

Abstract

The light emitting device according to the embodiment, the light transmissive substrate; A first conductive semiconductor layer disposed on the substrate, a second conductive semiconductor layer disposed on the first conductive semiconductor layer, and between the first conductive semiconductor layer and the second conductive semiconductor layer; A light emitting structure comprising an active layer; A first electrode disposed on the first conductive semiconductor layer and a second electrode disposed on the second conductive semiconductor layer; A first electrode pad electrically connected to the first electrode and a second electrode pad electrically connected to the second electrode; And a semi-insulated submount substrate on which the first and second electrode pads are disposed.

Description

[0001] LIGHT EMITTING DEVICE [0002]

An embodiment relates to a light emitting element.

In general, III-V nitride semiconductors, such as gallium nitride (GaN), have a green or blue light emitting diode (LED) which is provided as a light source to a full color display, an image scanner, various signal systems, and an optical communication device due to its excellent physical and chemical properties. Widely used in devices. These LED devices generate and emit light in an active layer that uses the recombination principle of electrons and holes.

Recently, high brightness is required to use such a gallium nitride-based LED device as an illumination light source, and high output gallium nitride-based LED devices that can operate at a large current have been manufactured to achieve such high brightness.

Such gallium nitride-based LED devices are classified into horizontally structured light emitting diodes (LEDs) and vertically structured light emitting diodes (LEDs).

The gallium nitride based LED devices having the above-described horizontal structure are classified into top-emitting light emitting diodes (LEDs) and flip-chip light emitting diodes (LEDs).

The top-emit type LED is formed to emit light through the ohmic electrode layer in contact with the second conductive semiconductor layer, and the flip chip LED is formed to emit light through the sapphire substrate.

On the other hand, such gallium nitride-based LED device is generally die attach on the submount (or package or lead frame: hereinafter referred to as 'submount'), the light is extracted and not die attached to the submount Emitted through one side of the LED chip.

The submount of a conventional flip chip type light emitting device requires two electrodes, an N-pad and a P-pad, for connecting two electrodes of an anode and a cathode of the LED. In the case of using a conductive substrate, a passivation layer was inserted between the conductive substrate and the pads of the two electrodes in order to distinguish the two electrodes of the N-pad and the P-pad. . At this time, the passivation layer (passivation layer) was formed using an oxide film such as SiO 2 , SiNx.

However, the passivation layer degrades the thermal conductivity between the LED device and the submount. Therefore, the light emitting device having the passivation layer has a high thermal resistance. This not only increases the driving voltage but also deteriorates the characteristics and reliability of the device.

Such a problem is very difficult to ensure high output especially in a light emitting device for lighting apparatus having a large size (for example, 1000 μm × 1000 μm).

In addition, a Zener diode is inserted in parallel to the existing LED package for ESD protection. However, there is a problem in that there are a lot of restrictions on the additional process and the amount of light decrease thereby.

SUMMARY In order to solve the above problem, an embodiment of the present invention is to provide a light emitting device that does not require a passivation layer formed on a submount substrate.

In addition, another technical problem to be achieved by the embodiment is to achieve the same ESD protection effect by using the Schottkey diode characteristics between the semiconductor and the metal without mounting the existing additional Zener diode. To present a light emitting device that can be.

Another object of the present invention is to provide a light emitting device capable of lowering thermal resistance.

The light emitting device according to the embodiment, the light transmissive substrate; A first conductive semiconductor layer disposed on the substrate, a second conductive semiconductor layer disposed on the first conductive semiconductor layer, and between the first conductive semiconductor layer and the second conductive semiconductor layer; A light emitting structure comprising an active layer; A first electrode disposed on the first conductive semiconductor layer and a second electrode disposed on the second conductive semiconductor layer; A first electrode pad electrically connected to the first electrode and a second electrode pad electrically connected to the second electrode; And a semi-insulated submount substrate on which the first and second electrode pads are disposed.

According to the exemplary embodiment, the same ESD protection effect may be obtained by using a schottkey diode characteristic between a semiconductor and a metal without mounting an existing zener diode.

In addition, since the passivation layer is not used, the thermal conductivity is large and the thermal resistance can be lowered.

1 is a view showing a light emitting device according to an embodiment.
2 is a schematic diagram illustrating ESD shock protection using the schottkey characteristics of a metal-semiconductor.

The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. In addition, the size of each component does not necessarily reflect the actual size.

In the description of the embodiment according to the present invention, in the case of being described as being formed "on or under" of each element, the upper (upper) or lower (lower) or under are all such that two elements are in direct contact with each other or one or more other elements are indirectly formed between the two elements. Also, when expressed as "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Example

1 is a view illustrating a light emitting device according to an embodiment, and FIG. 2 is a schematic view showing an ESD shock protection function using a schottkey characteristic of a metal-semiconductor.

Referring to FIG. 1, the light emitting device 100 according to the embodiment may include a chip and a submount.

In the chip of the light emitting device 100, a substrate 110 and a first conductive semiconductor layer 111, an active layer 112, and a second conductive semiconductor layer 113 are sequentially stacked on the substrate 110. The light emitting structure 114, the second electrode 115 formed on the second conductive semiconductor layer 113, the first electrode 117 formed on the first conductive semiconductor layer 111, A first base metal (UBM) layer 116 formed on the second electrode 115 and a second base metal (UBM) layer 118 formed on the first electrode 117 are included. can do.

The submount of the light emitting device 100 may include a submount substrate 120, a second electrode pad 121 formed on the first region of the submount substrate 120, and an upper portion of the second electrode pad 121. A third base metal (UBM) layer 122 formed on the first electrode pad 125, a first electrode pad 125 formed on the second region of the submount substrate 120, and a first electrode pad 125 formed on the first electrode pad 125. 4 may include a base metal (UBM) layer 126.

The chip of the light emitting device 100 and the submount of the light emitting device 100 may be coupled by a first solder bumper 123 and a second solder bumper 127. Specifically, a first solder bumper 123 is disposed between the first base metal layer (UBM) 116 of the chip and the third base metal (UBM) layer 122 of the submount. A second solder bumper 127 is disposed between the second base metal (UBM) layer 118 of the chip and the fourth base metal (UBM) layer 126 of the submount.

The substrate 110 has a light transmitting characteristic. The substrate 110 is an insulating substrate such as sapphire (Al 2 O 3), spinel (MgAl 2 O 4) mainly on the C surface, R surface, or A surface, SiC (including 6H, 4H, 3C), Si, GaAs, GaN At least one of semiconductor substrates such as ZnO, Si, GaP, InP, and Ge. Here, the substrate 110 is not limited to the above-described materials, and may be formed of any material capable of sequentially growing the first conductive semiconductor layer 111, the active layer 112, and the second conductive semiconductor layer 113. It is to be understood that the substrate also includes.

The buffer layer (not shown) may be disposed between the substrate 110 and the light emitting structure 114. Specifically, the buffer layer (not shown) is a layer for improving lattice matching with the substrate 110 before growing the first conductivity-type semiconductor layer 111 on the substrate 110. It can be omitted depending on the device characteristics.

The first conductivity type semiconductor layer 111 may be, for example, an n-type semiconductor layer, and may have an In X Al Y Ga 1-XY N composition formula (where 0 ≦ X, 0 ≦ Y, and X + Y ≦ 1). It may be made of a semiconductor material having. Here, the material of the first conductive semiconductor layer 111 is not limited. More specifically, the first conductivity type semiconductor layer 111 may be formed of a GaN layer or a GaN / AlGaN layer doped with an n-type dopant. In this case, the n-type dopant may be included in the first conductivity-type semiconductor layer 300 at a concentration of 3 × 10 18 / cm 3 or more, preferably 5 × 10 18 / cm 3 or more. When the n-type dopant is heavily doped in this way, the forward voltage Vf and the threshold current can be lowered. If the concentration of the dopant is out of the above range, Vf will not be substantially lowered. In addition, when the first conductivity type semiconductor layer 111 is formed on u-GaN having good crystallinity, it may have good crystallinity even though it contains a high concentration of n-type dopant. Although the upper limit of the concentration of the n-type dopant is not limited, the upper limit is preferably 5 x 10 < 21 > / cm < 3 > or less in order to maintain good crystallinity.

As illustrated in FIG. 1, the first conductive semiconductor layer 111 may have a single layer structure or a multilayer structure.

The first conductivity type semiconductor layer 111 may include a first region 111 on which the second electrode 115 is disposed and a region on the left side of the second region 111 on which the first electrode 117 is disposed. ) Can be separated. The first region defines a light emitting surface, and accordingly, an area of the first region may be larger than that of the second region to improve luminance characteristics of the device.

In the active layer 112, electrons (or holes) injected through the first conductivity type semiconductor layer 111 and holes (or electrons) injected through the second conductivity type semiconductor layer 113 formed later meet each other (Recombination). ), A layer that emits light due to a band gap difference of an energy band according to a material forming the active layer 112.

The active layer 112 may be formed of a single quantum well structure or a multi quantum well structure (MQW). The active layer 112 may be an MQW having an InGaN / GaN layer.

The active layer 112 generally includes a quantum well layer and a barrier layer. Here, the order of stacking the barrier layer and the quantum well layer is not specifically defined. However, the order of stacking the barrier layer and the quantum well layer may be laminated from the quantum well layer to the quantum well layer, or may be laminated from the quantum well layer to the barrier layer. In addition, the barrier layer may be laminated from the barrier layer to the barrier layer, or may be laminated from the barrier layer to the quantum well layer.

The second conductivity-type semiconductor layer 113 is, for example, a p-type semiconductor layer, and has In X Al Y Ga 1 -X - Y N composition formula (where 0 ≦ X, 0 ≦ Y, and X + Y ≦ 1). It may be a semiconductor material having.

The second conductive semiconductor layer 113 is doped with p-type dopants such as Mg and Ba. Here, when the p-type dopant is Mg, the p-type characteristic is easily obtained, and the ohmic contact is easy to be obtained. The concentration of Mg may be 1 × 10 18 / cm 3 to 1 × 10 21 / cm 3, preferably 5 × 10 19 / cm 3 to 3 × 10 20 / cm 3, more preferably 1 × 10 20 / cm 3. If the Mg concentration is within this range, a good p-type film can be easily obtained and the Vf can be lowered.

Here, the second conductivity type semiconductor layer 113 may have a single layer structure or a multilayer structure.

The second electrode 115 is formed on the second conductive semiconductor layer 113. The second electrode 115 may be formed of at least one layer selected from a reflective electrode, an ohmic contact electrode, and a transparent electrode. For example, the second electrode 115 may include a single layer or a reflective electrode / ohmic contact electrode, an ohmic contact electrode / a transparent electrode, or an ohmic contact electrode including any one layer selected from a reflective electrode, an ohmic contact electrode, and a transparent electrode. It is a multi-layer consisting of transparent electrode and reflective electrode, and can be selected according to process conditions and device characteristics.

The first electrode 117 is formed on the second region of the first conductivity type semiconductor layer 111. The second region of the first conductivity type semiconductor layer 111 is a region in which part of the emission surface is removed by mesa etching. The first electrode 117 may be formed of at least one layer selected from a reflective electrode, an ohmic contact electrode, and a transparent electrode. For example, the first electrode 117 may include a single layer or a reflective electrode / ohmic contact electrode, an ohmic contact electrode / a transparent electrode, and an ohmic contact electrode including any one layer selected from a reflective electrode, an ohmic contact electrode, and a transparent electrode. It is a multi-layer consisting of transparent electrode and reflective electrode, and can be selected according to process conditions and device characteristics.

A first base metal (UBM) layer 116 is formed on the second electrode 115. The first base metal (UBM) layer 116 may include the light emitting structure 114, that is, the second conductive semiconductor layer, having the first solder bumper 123 through the second electrode 115. (113), the active layer 112 and the first conductivity-type semiconductor layer 111 is diffused to prevent the chip portion of the light emitting device 100 is destroyed, and the second electrode 115 And to enhance the adhesive force between the first solder bumper (solder bumper) (123).

A second base metal (UBM) layer 118 is formed on the first electrode 117. The second base metal (UBM) layer 118 has the second solder bumper 127 diffused through the first electrode 117 into the first conductive semiconductor layer 111 to emit light. It serves to prevent the chip portion of the device 100 from being destroyed, and also enhances the adhesion between the first electrode 117 and the second solder bumper 127.

The first and second base metal (UBM) layers 116 and 118 may include a first adhesive layer (not shown) for enhancing adhesion to the second electrode 115 or the first electrode 117. A diffusion barrier layer (not shown) for preventing the first or second solder bumpers 123 and 127 from being diffused into the chip portion of the light emitting device 100, and the first or second solder bumpers 123 and 127. It may include a second adhesive layer (not shown) to enhance the adhesive force with). The first adhesive layer (not shown) may be made of one of metals including chromium (Cr) and titanium (Ti), and the diffusion barrier layer may be made of one of metals including copper (Cu) and tungsten (W). The second adhesive layer (not shown) may be made of one of metals including gold (Au) and nickel (Ni).

The submount substrate 120 may be a semi-insulated substrate, such as a silicon (Si) substrate. In this case, when the submount substrate 120 is a semi-insulator substrate, since the passivation layer does not need to be used, heat from the chip may be easily transferred to the submount substrate 120.

The submount substrate 120 may be replaced with a printed circuit board (PCB). The submount substrate 120 may be mounted with a plurality of chips to be used as a light source or an indicator.

First and second electrode pads 121 and 125 opposing the first and second electrodes 115 and 117 of the chip may be formed on the submount substrate 120. Specifically, the second electrode pad 121 is formed in a predetermined region on the submount substrate 120 facing the second electrode 115 and the submount substrate facing the first electrode 117. The first electrode pad 125 may be formed in a predetermined region on the 120. In this case, the second electrode pad 121 and the first electrode pad 125 may be spaced apart from each other by a predetermined distance on the submount substrate 120.

Subsequently, the third base metal (UBM) layer 122 may be disposed to face the first base metal (UBM) layer 116 on the second electrode pad 121. In addition, the fourth base metal layer 126 may be disposed on the first electrode pad 125 so as to face the second base metal layer 118.

In this case, the third and fourth base metal (UBM) layers 122 and 126 may have the first or second solder bumpers 123 and 127 through the first or second electrodes 121 and 125. Serves to prevent diffusion into the mount substrate 120, and also enhances adhesion between the first or second electrodes 121 and 125 and the first or second solder bumpers 123 and 127. .

To this end, the third and fourth base metal (UBM) layers 122 and 126 may include a first adhesive layer (not shown) for enhancing adhesion to the first or second electrodes 121 and 125, and the first or fourth base metal (UBM) layers 122 and 126. A diffusion barrier layer (not shown) for preventing the second solder bumpers 123 and 127 from being diffused into the submount substrate 120, and a second adhesive layer for enhancing adhesion between the first or second solder bumpers 123 and 127. (Not shown). The first adhesive layer (not shown) may be made of one of metals including chromium (Cr) and titanium (Ti), and the diffusion barrier layer may be made of one of metals including copper (Cu) and tungsten (W). The second adhesive layer (not shown) may be made of one of metals including gold (Au) and nickel (Ni).

The light emitting device 100 may include the first base metal (UBM) layer 116 of the chip and the third base metal (UBM) layer of the submount in order to bond the chip and the submount to one. A first solder bumper 123 is formed between the 122s. A second solder bumper 127 is formed between the second base metal (UBM) layer 118 of the chip and the fourth base metal (UBM) layer 126 of the submount. have.

The first and second solder bumpers 123 and 127 may provide heat generated from the chip through electrical contact between the chip and the submount through the first to fourth base metal layers 116, 118, 122, and 126. A passage for delivering to the mount substrate 120 is provided.

The first and second solder bumpers 123 and 127 may be generally made of a conductive metal mainly composed of lead (Pb) and tin (Sn), and the first base metal (UBM) layer 116 and the first Flip chip bonding is performed between the three base metal (UBM) layers 122 and between the second base metal (UBM) layer 118 and the fourth base metal (UBM) layer 126.

As shown in FIG. 2, the light emitting device 100 includes the second electrode pad 121 and the first electrode pad 125 and the sub-mount substrate 120 of the semi-insulator of the pn junction where heat is generated. Since no passivation layer is formed in between, the thermal conductivity is excellent. Therefore, the light emitting device 100 has an advantage of low thermal resistance.

In addition, an ESD shock may be absorbed by using a schottkey diode characteristic between the first and second electrode pads 121 and 125 and the submount substrate 120 of the semi-insulator.

As described above, the light emitting device according to the embodiment has the same ESD protection effect by using a schottkey diode characteristic between a semiconductor and a metal without mounting an existing additional zener diode. By obtaining it, the technical subject of this invention can be solved.

In the present embodiment, a light emitting device having a pn junction structure is taken as an example, but a light emitting device chip formed of light emitting devices having a pnp or npn junction structure may also be mounted.

Although the above description has been made with reference to the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains are not illustrated above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

The light emitting device according to the embodiment may be applied to a lighting module, a lighting device, a back light unit (BLU), a semiconductor device, or the like.

100: Light emitting element
110 substrate 111 first conductive semiconductor layer
112: active layer 113: second conductive semiconductor layer
114: light emitting structure 115: second electrode
116: First Bumper Metalization (UBM) layer
117: first electrode 118: second base metal (UBM) layer
120: submount substrate 121: second electrode pad
122: third base metal (UBM) layer
123: first solder bumper
125: first electrode pad 126: fourth base metal (UBM) layer
127: second solder bumper

Claims (6)

Light transmissive substrate;
A first conductive semiconductor layer disposed on the substrate, a second conductive semiconductor layer disposed on the first conductive semiconductor layer, and between the first conductive semiconductor layer and the second conductive semiconductor layer; A light emitting structure comprising an active layer;
A first electrode disposed on the first conductive semiconductor layer and a second electrode disposed on the second conductive semiconductor layer;
A first electrode pad electrically connected to the first electrode and a second electrode pad electrically connected to the second electrode; And
A semi-insulated submount substrate on which the first and second electrode pads are disposed;
It comprises a light emitting device.
The method of claim 1,
A first solder bumper disposed between the first electrode and the first electrode pad; And
A second solder bumper disposed between the second electrode and the second electrode pad;
Further comprising a light emitting device.
3. The method of claim 2,
Between the first electrode and the first solder bumper, between the first electrode pad and the first solder bumper, between the second electrode and the second solder bumper, and between the second electrode pad and the second solder bumper. A light emitting device further comprising a base metal layer disposed.
The method of claim 3, wherein the base metal layer,
A first adhesive layer;
A diffusion barrier layer disposed on the first adhesive layer and preventing diffusion of the first and second solder bumpers into the submount substrate; And
A second adhesive layer disposed on the diffusion barrier layer;
It comprises a light emitting device.
5. The method of claim 4,
The first adhesive layer is chromium (Cr) or titanium (Ti),
The diffusion barrier layer is copper (Cu) or tungsten (W),
The second adhesive layer is gold (Au) or nickel (Ni), the light emitting device.
6. The method according to any one of claims 1 to 5,
The second conductive semiconductor layer is a GaN layer or a GaN / AlGaN layer doped with a p-type conductive impurity,
The first conductive semiconductor layer is a GaN layer or a GaN / AlGaN layer doped with n-type conductive impurities, a light emitting device.
KR1020120089371A 2012-08-16 2012-08-16 Light emitting device KR20140023506A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020120089371A KR20140023506A (en) 2012-08-16 2012-08-16 Light emitting device

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Application Number Priority Date Filing Date Title
KR1020120089371A KR20140023506A (en) 2012-08-16 2012-08-16 Light emitting device

Publications (1)

Publication Number Publication Date
KR20140023506A true KR20140023506A (en) 2014-02-27

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