KR20140021125A - Solar cell - Google Patents

Abstract

The present invention relates to a solar cell. The solar cell according to the present invention comprises; a semiconductor substrate containing first conductive foreign substances; an emitter unit which is arranged on the back side of the semiconductor substrate and forms a p-n junction with the semiconductor substrate and has second conductive foreign substances which are opposite to the first conductive foreign substances; a back surface field unit which is arranged on the back side of the semiconductor substrate and contains first conductive foreign substances with high concentration compared with the semiconductor substrate; a first electrode formed on the emitter unit; a second electrode formed on the bask surface field unit; and a buffer layer arranged between the first and second electrodes. The surface area per unit area of the back side of the semiconductor layer in at least one area among areas which are in contact with the emitter and back surface field units among the back sides of the semiconductor substrate except for an area overlapped with the buffer layer is formed larger than the surface area per unit area of the back side of the semiconductor substrate in an area overlapped with the buffer layer among the back sides of the semiconductor substrate.

Description

Solar cell {SOLAR CELL}

The present invention relates to a solar cell.

Recently, as energy resources such as oil and coal are expected to be depleted, interest in alternative energy to replace them is increasing, and solar cells that produce electric energy from solar energy are attracting attention.

Typical solar cells have a semiconductor portion that forms a p-n junction by different conductive types, such as p-type and n-type, and electrodes connected to semiconductor portions of different conductivity types, respectively.

When light is incident on the solar cell, a plurality of electron-hole pairs are generated in the semiconductor, and the generated electron-hole pairs are separated into electrons and holes, which are electric charges, and the electrons move toward the n-type semiconductor portion, and the holes are p-type. Move toward the semiconductor portion. The transferred electrons and holes are collected by the different electrodes connected to the p-type semiconductor portion and the n-type semiconductor portion, respectively, and the electrodes are connected by a wire to obtain electric power.

The present invention aims at improving the efficiency of solar cells.

A solar cell according to the present invention comprises a semiconductor substrate containing an impurity of a first conductivity type; An emitter portion disposed on a rear surface of the semiconductor substrate, forming a p-n junction with the semiconductor substrate, the emitter portion having a second conductivity type opposite to the first conductivity type; A rear field unit disposed on a rear surface of the semiconductor substrate and containing a higher concentration of impurities of a first conductivity type than the semiconductor substrate; A first electrode formed on the emitter portion; A second electrode formed on the rear electric field; And a buffer layer disposed between the first electrode and the second electrode of the rear surface of the substrate, wherein the buffer layer is disposed in at least one region of the rear surface of the semiconductor substrate except for the region overlapping the buffer layer and in contact with the emitter portion or the rear electric field portion. The surface area per unit area of the back surface of the semiconductor substrate is larger than the surface area per unit area of the back surface of the semiconductor substrate in the region overlapping with the buffer layer in the back surface of the semiconductor substrate.

Herein, unevenness having a first shape is formed in a region overlapping the buffer layer among the back surface of the semiconductor substrate, and a region different from the first shape in a region in contact with the emitter portion or the backside electric field portion among the back surface of the semiconductor substrate except the region overlapping the buffer layer. Unevenness having a second shape may be formed.

Here, the unevenness having the first shape may include a flat surface at the top portion, and the unevenness having the second shape may not include the flat surface at the top portion.

Specifically, the side cross-sectional shape of the unevenness having the first shape may include a trapezoidal shape, and the side cross-sectional shape of the unevenness having the second shape may include a pyramid shape. In this case, the width of the flat surface formed on the top portion of the unevenness having the first shape may be between 1 and 20 μm.

In addition, the maximum height among the irregularities having a trapezoidal shape may be smaller than the height of the irregularities having a maximum height among the irregularities having a pyramidal shape. Specifically, the maximum height of the irregularities having a trapezoidal shape is 5 μm and the irregularities having a pyramidal shape May have a maximum height of 15 μm.

In addition, the bottom shape of the irregularities having a trapezoidal shape may be the same as the bottom shape of the irregularities having a pyramidal shape.

In addition, a region in which the unevenness having the second shape is formed in the rear surface of the semiconductor substrate may overlap the junction surface of the first electrode and the emitter portion, and a region in which the unevenness in which the second shape is formed in the rear surface of the semiconductor substrate is formed It may overlap with the junction surface of a 2 electrode and a back electric field part.

In addition, the emitter unit and the rear electric field unit may be in contact with each other, and the buffer layer may be disposed on a junction surface of the emitter unit and the rear electric field unit in contact with each other, and the buffer layer may include a non-conductive insulating material.

For example, the buffer layer may include at least one of silicon oxide (SiOx) and silicon nitride (SiNx).

In addition, the emitter portion and the backside electric field portion may include crystalline silicon or amorphous silicon, and the semiconductor substrate may include crystalline silicon.

In addition, the side cross-sectional shape of the concave-convex shape having the first shape may include a pyramid shape, and the side cross-sectional shape of the concave-convex shape having the second shape may include a shape in which a plurality of small concave-convex concave-convex surfaces are coupled to the inclined surface of the pyramid shape. .

Alternatively, the side cross-sectional shape of the concave-convex shape having the first shape may include a trapezoidal shape, and the side cross-sectional shape of the concave-convex shape having the second shape may include a shape in which a plurality of small irregularities are combined with a trapezoidal inclined surface. can do.

The solar cell according to the present invention has a surface area per unit area of the rear surface of the semiconductor substrate in at least one of the regions in contact with the emitter portion or the rear electric field portion of the rear surface of the semiconductor substrate except for the region overlapping the buffer layer. The surface area per unit area of the back surface of the semiconductor substrate in the overlapping region is made larger, whereby the short circuit current of the solar cell can be further improved.

1 to 3 are diagrams for explaining a first embodiment of a solar cell according to the present invention.
4 is a view for explaining a second embodiment of a solar cell according to the present invention.
5 is a view for explaining a third embodiment of a solar cell according to the present invention.
6 is a view for explaining a fourth embodiment of the solar cell according to the present invention.
7 and 8 are views for explaining another example of the shape of the unevenness shown in FIGS.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle. Also, when a part is formed as "whole" on the other part, it means not only that it is formed on the entire surface (or the front surface) of the other part but also not on the edge part.

Hereinafter, a solar cell according to the present invention will be described with reference to the accompanying drawings.

1 to 3 are diagrams for explaining a first embodiment of a solar cell according to the present invention.

Specifically, FIG. 1 is a partial perspective view of a solar cell according to the present invention, FIG. 2 is a cross-sectional view of the solar cell shown in FIG. 1 taken along the line II-II, and FIG. 3 is a first shape of the substrate in FIG. It is a figure for comparing and explaining the shape of the unevenness | corrugation which has a 2nd shape, and the unevenness which has a 2nd shape.

1 and 2, a solar cell 1 according to an exemplary embodiment of the present invention includes a semiconductor substrate 110 and a front surface electric field part 171 positioned on a first surface of the semiconductor substrate 110, that is, on a front surface thereof. (front surface field (FSF)) 171, the anti-reflection portion 130 located on the front electric field portion 171, the second surface opposite to the first surface of the semiconductor substrate 110, that is located on the rear surface A plurality of emitter portions 121, a plurality of back surface fields (BSFs) 172 located on the rear surface of the substrate and extending in parallel with the plurality of emitter portions 121, respectively, and a plurality of emitter portions 121. Between the plurality of first electrodes 141 and the plurality of second electrodes 142 positioned on the plurality of rear electric field parts 172 and the rear surface of the substrate, between the first electrodes 141 and the second electrodes 142, respectively. It may include a buffer layer 150 disposed in.

1 and 2 illustrate an example in which the solar cell 1 according to the present invention includes the anti-reflection unit 130 and the front electric field unit 171, but here, the anti-reflection unit 130 is included. ) And the front electric field unit 171 may be omitted.

However, when the anti-reflection unit 130 and the front electric field unit 171 are formed, since the photoelectric efficiency of the solar cell 1 may be further improved, the anti-reflection unit 130 and the front electric field unit 171 will be described below. What is included in the solar cell 1 is demonstrated as an example.

The semiconductor substrate 110 may be a crystalline semiconductor substrate 110 made of silicon of a first conductivity type, for example, n-type conductive type. At this time, the silicon may be crystalline silicon such as single crystal silicon or polycrystalline silicon. Impurities of pentavalent elements such as phosphorus (P), arsenic (As), and antimony (Sb) are doped in the semiconductor substrate 110 when the semiconductor substrate 110 has an n-type conductivity type. Alternatively, however, the semiconductor substrate 110 may be of the p-type conductivity type and may be made of a semiconductor material other than silicon. When the semiconductor substrate 110 has a p-type conductivity type, the semiconductor substrate 110 is doped with impurities of a trivalent element such as boron (B), gallium (Ga), indium (In) do.

The semiconductor substrate 110 has an uneven surface by texturing the incident surface. For convenience, in FIG. 1, only the edge portion of the semiconductor substrate 110 is illustrated as an uneven surface. However, substantially the entire front surface of the semiconductor substrate 110 has an uneven surface, and thus, antireflection is disposed on the front surface of the semiconductor substrate 110. The part 130 and the front electric field part 171 also have an uneven surface.

1 and 2, the semiconductor substrate 110 may have a concave-convex surface on the rear surface as well as the front surface. However, the concave-convex shape having a second shape which is a part of the rear surface of the semiconductor substrate 110 may be formed. The shape of the unevenness formed in the region to be formed may be the same as the shape of the unevenness formed in the front surface of the semiconductor substrate 110, but the shape of the unevenness formed in the region in which the unevenness having the first shape, which is the remaining part, is formed is the front surface of the semiconductor substrate 110. It may differ from the uneven shape formed in the.

Next, the front electric field unit 171 may be located on the front surface of the semiconductor substrate 110, as shown in FIG. 1.

The front electric field unit 171 is formed with a potential barrier due to a difference in impurity concentration between the semiconductor substrate 110 and the front electric field unit 171 to prevent charge (eg, hole) movement toward the front surface of the semiconductor substrate 110. There is a field effect.

Accordingly, the front electric field unit 171 has a front electric field effect for returning holes moving toward the front surface of the semiconductor substrate 110 toward the rear surface of the semiconductor substrate 110 by the potential barrier, and thus, the front electric field unit 171 ) Increases the output amount of charge output to the external device and reduces the amount of charge lost by recombination or defects in the front surface of the semiconductor substrate 110.

The front electric field unit 171 may include hydrogen, and in the case of containing hydrogen, defects such as dangling bonds mainly present on and near the surface of the semiconductor substrate 110 may be formed. A passivation function may be performed to reduce the dissipation of charges on the front surface of the semiconductor substrate 110 due to defects by switching to a stable bond.

The front electric field unit 171 may include any one of amorphous silicon, amorphous silicon oxide (a-SiOx), and amorphous silicon silicon (a-SiC).

Next, the anti-reflection unit 130 may be positioned on the front electric field unit 171 and may reduce the reflectivity of light incident on the solar cell 1 and increase the selectivity of a specific wavelength region, thereby increasing the efficiency of the solar cell 1. Increase The anti-reflection portion 130 may include at least one of a silicon nitride film (SiNx), a zinc oxide (ZnO), or an aluminum zinc oxide (AZO).

Although the anti-reflection portion 130 has a single-layer structure in FIGS. 1 and 2, the anti-reflection portion 130 may have a double-layer structure or a multi-layer structure.

The plurality of emitter parts 121 extend in parallel with the plurality of rear electric field parts 172 in a predetermined direction on the rear surface of the semiconductor substrate 110.

As shown in FIGS. 1 and 2, the rear electric field part 172 and the emitter part 121 are alternately positioned on the semiconductor substrate 110.

Each emitter portion 121 is formed on the rear surface of the semiconductor substrate 110, and has a second conductivity type, for example, a p-type conductivity type, which is opposite to the conductivity type of the semiconductor substrate 110. 121 forms a pn junction with the semiconductor substrate 110.

Hole pairs formed by the light incident on the semiconductor substrate 110 are separated into electrons and holes by the pn junction formed between the semiconductor substrate 110 and the plurality of emitter sections 121, And the holes move toward the p-type. Therefore, when the semiconductor substrate 110 is n-type and the plurality of emitter portions 121 are p-type, the separated holes move toward the respective emitter portions 121 and the separated electrons are higher in impurity concentration than the semiconductor substrate 110 And moves toward the plurality of rear electric sections 172.

Since each emitter portion 121 forms a pn junction with the semiconductor substrate 110, unlike the present embodiment, when the semiconductor substrate 110 has a p-type conductivity type, the emitter portion 121 has an n-type conductivity. Has type In this case, the separated electrons move toward the plurality of emitter parts 121, and the separated holes move toward the plurality of rear electric field parts 172.

When the emitter portion 121 has a p-type conductivity type The emitter portion 121 may be doped with an impurity of a trivalent element. On the contrary, when the emitter portion 121 has an n-type conductivity type. The emitter unit 121 may be doped with impurities of a pentavalent element.

The emitter unit 121 may be formed by diffusing impurities of the second conductivity type on the back surface of the semiconductor substrate 110, and an amorphous silicon material containing impurities of the second conductivity type on the back surface of the semiconductor substrate 110. It may be formed by depositing.

When the semiconductor substrate 110 includes crystalline silicon and the emitter portion 121 includes amorphous silicon, the emitter portion 121 forms a hetero junction as well as a p-n junction with the semiconductor substrate 110. As described above, when the semiconductor substrate 110 and the emitter portion 121 form heterojunctions, the open voltage Voc of the solar cell 1 can be further improved.

The plurality of rear electric field sections 172 are regions containing impurities of the same conductivity type as that of the semiconductor substrate 110 at a higher concentration than the semiconductor substrate 110. For example, when the substrate includes an n-type impurity, the plurality of backside electric fields 172 may be n + impurity regions.

The plurality of backside electric fields 172 are disposed on the back surface of the semiconductor substrate 110 and extend in a predetermined direction in parallel with the emitter portion 121. Here, the back electric field unit 172 may be formed to be in contact with each other, as shown in FIGS. 1 and 2, the emitter unit 121 may be formed to be spaced apart from each other. Hereinafter, as shown in FIGS. 1 to 3, a case in which the rear electric field part 172 and the emitter part 121 are formed in contact with each other will be described as an example.

In addition, the rear electric field unit 172 may be formed by diffusing impurities of the first conductivity type on the rear surface of the semiconductor substrate 110, and may contain impurities of the first conductivity type on the rear surface of the semiconductor substrate 110. It may also be formed by depositing an amorphous silicon material.

The rear electric field 172 prevents hole movement toward the rear electric field 172 in the direction of movement of electrons by a potential barrier due to a difference in impurity concentration between the semiconductor substrate 110 and the rear electric field 172. It facilitates the movement of charge (eg, electrons) toward the backside electric field 172. Thus, the amount of charge lost by recombination of electrons and holes in the rear electric field 172 and in the vicinity thereof or at the first and second electrodes 141 and 142 is reduced and the electron movement is accelerated to the rear electric field 172 The electron transfer amount can be increased.

Each of the plurality of first electrodes 141 is located on the plurality of emitter sections 121 and extends along the plurality of emitter sections 121 and is electrically and physically connected to the plurality of emitter sections 121. Each first electrode 141 collects charges, for example, holes, which have migrated toward the corresponding emitter section 121.

A plurality of second electrodes 142 extend over the plurality of rear electrical components 172 and are electrically and physically connected to the plurality of rear electrical components 172 have. Each second electrode 142 collects a charge, e. G., Electrons, that travels toward the corresponding rear electric field 172.

 The plurality of first and second electrodes 141 and 142 may be formed of a conductive metal material. For example, nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti), gold (Au) and these It may be made of at least one conductive material selected from the group consisting of, or alternatively, it may be formed including a transparent conductive metal, for example TCO.

The buffer layer 150 is disposed between the first electrode 141 and the second electrode 142 on the rear surface of the substrate, and functions to insulate between the first electrode 141 and the second electrode 142. Therefore, the buffer layer 150 includes a non-conductive insulating material, and for example, may include at least one of silicon oxide (SiOx) and silicon nitride (SiNx).

The buffer layer 150 may be disposed on the bonding surface of the emitter unit 121 and the rear electric field unit 172.

The operation of the solar cell 1 according to this embodiment having such a structure is as follows.

When light is irradiated to the solar cell 1 and is incident on the semiconductor substrate 110, electron-hole pairs are generated in the semiconductor substrate 110 due to light energy. These electron-hole pairs are separated from each other by the pn junction of the semiconductor substrate 110 and the emitter section 121, and the holes move toward the emitter section 121 having the p-type conductivity type, and electrons move to the n- To the first electrode 141 and the second electrode 142, and are collected by the first and second electrodes 141 and 142, respectively. When the first electrode 141 and the second electrode 142 are connected to each other by a conductor, a current flows and the external power is utilized.

On the other hand, in the solar cell 1 according to the present invention, of the region of the back surface of the semiconductor substrate 110 except for the region (S1) overlapping the buffer layer 150 of the region in contact with the emitter portion 121 or the electric field portion 172 of the back surface The surface area per unit area of the rear surface of the semiconductor substrate 110 in at least one region is greater than the surface area per unit area of the rear surface of the semiconductor substrate 110 in the region S1 overlapping the buffer layer 150 among the rear surfaces of the semiconductor substrate 110. Is formed.

This is because unevenness having a first shape having a relatively small surface area is formed in the region S1 overlapping with the buffer layer 150 in the back surface of the semiconductor substrate 110, and the semiconductor except for the region S1 overlapping with the buffer layer 150 is formed. The surface SE and SB of the rear surface of the substrate 110 contacting with the emitter portion 121 or the rear electric field portion 172 have a relatively large surface area and have irregularities having a second shape different from the first shape. Can be.

For example, as shown in FIG. 2, in the solar cell 1 according to the present invention, the unevenness having the first shape is formed in the region S1 overlapping with the buffer layer 150 in the rear surface of the semiconductor substrate 110. Is formed, and irregularities having a second shape different from the first shape are formed in the region SE in contact with the emitter portion 121 of the back surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150. Can be. That is, the region having the second shape among the rear surfaces of the semiconductor substrate 110 may overlap the surface where the first electrode 141 and the emitter portion 121 are bonded.

In addition, at this time, the unevenness P1 having the first shape is formed in the region SB of the back surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150. Although illustrated as an example, the concave-convex (P2) having a second shape may be formed differently. This will be described in more detail with reference to FIGS. 5 and 6.

Specifically, as shown in FIG. 3, the unevenness P1 having the first shape includes a flat surface PT at the top portion, and the unevenness P2 having the second shape has a flat surface PT at the top portion. ) May not be included. For example, as shown in FIG. 3, the side cross-sectional shape of the unevenness P2 having the second shape may include a pyramid shape, and the side cross-sectional shape of the unevenness P1 having the first shape may include a trapezoidal shape. have.

Here, the unevenness P1 having the first shape may be formed by another etching process that is formed or added by performing damage damage etching on the back surface of the semiconductor substrate 110, and has a second shape. After the unevenness P2 is subjected to the damage etching on the rear surface of the semiconductor substrate 110, the front surface of the emitter portion 121 or the rear surface of the semiconductor substrate 110 is excluded from the rear surface of the semiconductor substrate 110 except the region S1 to overlap the buffer layer 150. It may be formed by additionally performing dry or wet etching only on the regions SE and SB to be in contact with the step 172.

In more detail, during the cutting process of forming the semiconductor substrate 110 for the solar cell 1, defects may occur on the surface of the semiconductor substrate 110. Such defects may be saw damage etching. Can be removed by

Such damage damage (saw damage etching) may be performed by wet etching, and when performing damage damage (saw damage etching), the surface of the semiconductor substrate 110 is a first shape having a flat top, that is, Unevenness P1 having a trapezoidal shape may be formed.

Subsequently, additional wet etching is further performed only on regions SE and SB of the back surface of the semiconductor substrate 110 except for the region S1 to overlap with the buffer layer 150, which are to be in contact with the emitter portion 121 or the back surface electric field portion 172. It can be performed to form the concave-convex (P2) having a second shape, that is, a pyramid shape as described above.

When forming the concave-convex (P2) having such a pyramid shape, KOH or NaOH may be used as an etching solution that can be used in the case of wet etching.

As described above, an uneven surface P1 having a trapezoidal shape is formed in the region S1 overlapping with the buffer layer 150 in the back surface of the semiconductor substrate 110, except for the region S1 overlapping the buffer layer 150. An uneven surface P2 having a pyramid shape may be formed in the areas SE and SB in contact with the emitter unit 121 or the rear electric field unit 172 among the rear surfaces of the 110, thereby increasing the efficiency of the solar cell 1. Can be.

More specifically, the concave-convex (P2) structure having a pyramid shape formed on the rear surface of the semiconductor substrate 110 may be a junction surface of the semiconductor substrate 110 and the emitter portion 121 or the semiconductor substrate 110 and the rear electric field portion ( The joint area SE and SB of the joint surface of the 172 can be made larger, and the joint surface of the emitter part 121 and the first electrode 141 or the rear electric field part 172 and the second electrode 142 can be made larger. We can do it more than junction area of total surface of). As a result, the carrier can be collected more efficiently through the emitter unit 121 and the rear electric field unit 172, and the short circuit current of the solar cell 1 can be further improved.

In addition, since the unevenness P2 having the pyramid shape does not include the flat surface PT at the top of the unevenness, unlike the unevenness P1 having the trapezoidal shape, the semiconductor substrate among the light incident on the semiconductor substrate 110 is included. The light of the long wavelength band not absorbed at 110 may be dispersed through the pyramidal uneven inclined surface, and may be reflected more efficiently, thereby generating more carriers in the semiconductor substrate 110. . Thereby, the short circuit current of the solar cell 1 can be improved further.

Hereinafter, the unevenness P1 having the first shape and the unevenness P2 having the second shape among the back surfaces of the semiconductor substrate 110 will be described in detail with reference to FIG. 3.

FIG. 3A is an enlarged view of a cross section K1 of a region S1 overlapping the buffer layer 150 in the rear surface of the semiconductor substrate 110, and FIG. 3B is a view of the buffer layer 150. FIG. 2 is an enlarged view of the cross section K2 of the region SE in contact with the emitter portion 121 of the rear surface of the semiconductor substrate 110 except for the overlapping region S1.

As shown in FIG. 3A, the side cross-sectional shape of the uneven surface P1 having the first shape formed in the region S1 overlapping with the buffer layer 150 in the back surface of the semiconductor substrate 110 has a trapezoidal shape. 3, the emitter portion 121 of the back surface of the semiconductor substrate 110 except for the region S1 overlapping with the buffer layer 150 in the solar cell 1 according to the present invention. The side cross-sectional shape of the concave-convex (P2) having a second shape formed in the area (SE) in contact with) may include a pyramid shape.

In addition, although not shown in FIG. 3, as shown in FIGS. 1 and 2, the uneven surface P2 having the second shape, that is, the uneven surface P2 having the pyramid shape may be formed on the front surface of the semiconductor substrate 110. Can be.

Here, the width WPT of the flat surface PT formed at the top portion of the unevenness P1 having the first shape may be between 1 and 20 μm. The width WPT of the flat surface PT may vary depending on the time of the damage etching. That is, when the damage etching time is short, the width WPT of the flat surface PT of the trapezoidal irregularities formed in the region S1 overlapping with the buffer layer 150 is relatively wide, and the damage etching time In this long case, the width WPT of the flat surface PT is formed relatively narrow.

Here, as shown in FIG. 3, the height h1 of the unevenness having the maximum height among the unevennesses P1 having the trapezoidal shape is the height h2 of the unevenness having the maximum height among the unevennesses P2 having the pyramid shape. May be less than).

For example, the height h1 of the unevenness having the maximum height among the unevennesses P1 having the trapezoidal shape is 5 μm or less, and the height h2 of the unevenness having the maximum height among the unevennesses P2 having the pyramid shape is 15 μm. It may be formed as follows.

In addition, the bottom shape B1 of the irregularities P1 having the trapezoidal shape may be the same as the bottom shape B2 of the unevenness P2 having the pyramid shape.

As described above, in the solar cell 1 according to the present invention, the first shape unevenness P1 formed in the region S1 overlapping with the buffer layer 150 is overlapped with the buffer layer 150 in the back surface of the semiconductor substrate 110. The second shape unevenness P2 formed in the region SE in contact with the emitter portion 121 of the back surface of the semiconductor substrate 110 except for the region S1 to be formed is clearly distinguished in terms of formation method, height, and structure. Can be.

As such, the emitter unit 121 may be disposed on the back surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150 and the region S1 overlapping the buffer layer 150. Due to the difference in each uneven structure formed in the contact area SE, the solar cell 1 according to the present invention can further improve the power generation efficiency.

1 and 2, the emitter unit 121 and the rear electric field unit 172 are in contact with each other, and the buffer layer 150 is spaced apart from the semiconductor substrate 110 to emit the emitter unit 121 and the rear electric field unit. Although the case where it is disposed on the bonding surface 172 has been described as an example, the emitter unit 121 and the rear electric field unit 172 are spaced apart from each other, and the buffer layer 150 is in contact with the semiconductor substrate 110 to emit the unit. Even when formed between the 121 and the rear electric field 172, the present invention can be applied as it is.

4 is a view for explaining a second embodiment of a solar cell according to the present invention.

In FIG. 4, except for differences in the positions of the emitter unit 121, the rear electric field unit 172, and the buffer layer 150, the remaining parts are the same as those described with reference to FIGS. 1 to 3, and thus descriptions thereof will be omitted. .

As shown in FIG. 4, in the second embodiment of the present invention, the buffer layer 150 may be disposed between the emitter portion 121 and the rear electric field portion 172 in contact with the semiconductor substrate 110.

In this case, as shown in FIG. 4, the unevenness P1 having the first shape among the rear surfaces of the semiconductor substrate 110 is formed in an area S1 where the rear surface of the semiconductor substrate 110 is in contact with the buffer layer 150. The unevenness P2 having the second shape may be a region in which the emitter portion 121 is in contact with the emitter portion 121 of the rear surface of the semiconductor substrate 110 except for the region S1, in which the rear surface of the semiconductor substrate 110 contacts the buffer layer 150. (SE) can be formed.

In addition, unlike FIG. 4, the unevenness P2 having the second shape may be formed in front of the rear surface of the rear surface of the semiconductor substrate 110 except for the region S1 in which the rear surface of the semiconductor substrate 110 and the buffer layer 150 contact each other. It may also be formed in the region SB in contact with the system unit 172.

As described in the first embodiment, the solar cell 1 according to the second embodiment of the present invention also has the side cross-sectional shape of the uneven surface P1 having the first shape includes a trapezoidal shape. The side cross-sectional shape of the concave-convex P2 having two shapes may include a pyramid shape, thereby improving the efficiency of the solar cell 1.

Until now, as shown in FIGS. 1 to 4, the region in which the unevenness P2 having the second shape is formed is the semiconductor substrate except for the region S1 where the back surface of the semiconductor substrate 110 and the buffer layer 150 are in contact with each other. Although the case of the area SE that is in contact with the emitter part 121 among the rear surfaces of the 110 has been described as an example, as shown in FIG. 5, the unevenness P2 having the second shape is formed by the rear surface of the semiconductor substrate 110. It may be formed in the region SB of the back surface of the semiconductor substrate 110 except for the region S1 of the buffer layer 150, which is in contact with the rear field unit 172.

5 is a view for explaining a third embodiment of a solar cell according to the present invention.

In FIG. 5, except for the difference of the region in which the unevenness P2 having the second shape is formed, the remaining parts are the same as those described with reference to FIGS. 1 to 3, and thus description thereof will be omitted.

As shown in FIG. 5, in the solar cell 1 according to the present invention, the unevenness P1 having the first shape is formed in the region S1 overlapping the buffer layer 150 among the back surfaces of the semiconductor substrate 110. In the region SB of the back surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150, the unevenness P2 having a second shape different from the first shape is formed in the region SB that is in contact with the rear electric field part 172. This can be formed. As such, the region SB in which the unevenness P2 having the second shape is formed in the rear surface of the semiconductor substrate 110 may overlap the surface where the second electrode 142 and the rear electric field part 172 are joined. .

In this case, as shown in FIG. 5, an uneven surface P1 having a first shape may be formed in a region SE that contacts the emitter unit 121 of the back surface of the semiconductor substrate 110.

Accordingly, a trapezoidal unevenness P1 having a trapezoidal shape is formed in the region S1 overlapping the buffer layer 150 and the region SE in contact with the emitter portion 121 of the back surface of the semiconductor substrate 110. An uneven surface P2 having a pyramid shape may be formed in a region SB of the back surface of the semiconductor substrate 110 except for the back surface electric field unit 172. Even in such a case, as described above, the short-circuit current of the solar cell 1 can be further improved.

In addition, the solar cell 1 according to the present invention may be formed as shown in FIG. 6 below, including both the case of FIGS. 2 and 5.

6 is a diagram for explaining a fourth embodiment of the solar cell 1 according to the present invention.

Except for the difference with respect to the region in which the unevenness P2 having the second shape is formed in FIG. 6, the remaining parts are the same as those described with reference to FIGS. 1 to 3, and thus description thereof will be omitted.

As shown in FIG. 6, in the solar cell 1 according to the present invention, the unevenness P1 having the first shape is formed in the region S1 overlapping with the buffer layer 150 in the rear surface of the semiconductor substrate 110. The first and second regions SE of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150 are in contact with the emitter unit 121 and the region SB in contact with the rear electric field unit 172. Concave-convex P2 having a second shape different from the shape may be formed.

Accordingly, the irregularities P1 having a trapezoidal shape are formed in the region S1 overlapping the buffer layer 150 in the rear surface of the semiconductor substrate 110, and the semiconductor substrate except for the region S1 overlapping the buffer layer 150 ( The unevenness P2 having a pyramid shape may be formed in an area SB in contact with the rear electric field part 172 and an area SE in contact with the emitter part 121 among the rear surfaces of the 110.

In this case, both the region SB in contact with the rear electric field part 172 and the region SE in contact with the emitter part 121 of the back surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150. Since the unevenness P2 having the pyramid shape is formed in the above, the short-circuit current can be further improved than the solar cell 1 described with reference to FIGS. 1 to 5.

In addition, the surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150 is formed in the region S1 overlapping the buffer layer 150 so far. As an example, only the case where the unevenness P2 having a pyramid shape is formed in at least one of the region SB in contact with the electric field part 172 and the region SE in contact with the emitter part 121 is described.

Alternatively, the semiconductor substrate in at least one of the regions of the back surface of the semiconductor substrate 110 except the region S1 overlapping the buffer layer 150 and in contact with the emitter portion 121 or the back surface electric field portion 172. Since the surface area per unit area of the back surface of the (110) is formed to be larger than the surface area per unit area of the back surface of the semiconductor substrate 110 in the region S1 overlapping with the buffer layer 150 among the back surfaces of the semiconductor substrate 110. The same uneven shape may be variously changed.

7 and 8 are views for explaining another example of the shape of the unevenness shown in FIGS.

In detail, FIG. 8A is an enlarged view of an enlarged portion K1 'in FIG. 7 and FIG. 8B is an enlarged view of an enlarged portion K2' in FIG.

In FIG. 7 and FIG. 8, descriptions of parts overlapping with those described above with reference to FIGS. 1 through 6 are the same as before, and thus only portions different from those described above will be described.

The rear surface of the semiconductor substrate 110 in at least one of the regions in contact with the emitter portion 121 or the backside electric field portion 172 of the rear surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150. Since the surface area per unit area of the semiconductor substrate 110 may be larger than the surface area per unit area of the rear surface of the semiconductor substrate 110 in the region S1 overlapping the buffer layer 150 among the rear surfaces of the semiconductor substrate 110. An uneven surface P1 ′ having a pyramid shape is formed in a region S1 overlapping the buffer layer 150 among the rear surfaces, and an emitter portion in the rear surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150. Unevenness P2 ′ having a shape in which a plurality of small unevennesses are combined on a pyramidal inclined surface may be formed in at least one of the regions SE and SB contacting the 121 or the electric field part 172. have.

For example, as illustrated in FIGS. 7 and 8A, in the region S1 overlapping with the buffer layer 150, the unevenness P1 ′ having a pyramid shape is formed in the back surface of the semiconductor substrate 110. As shown in FIGS. 7 and 8B, a pyramid is formed in the region SE that contacts the emitter portion 121 of the back surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150. Concave-convex (P2 ') having a form in which a plurality of small concave-convex irregularities are combined on the inclined surface of the shape may be formed.

Here, the unevenness P1 ′ having a pyramid shape formed in the region S1 overlapping the buffer layer 150 among the back surface of the semiconductor substrate 110 is formed on the back surface of the semiconductor substrate 110. While performing damage damage etching (saw damage etching), it may be formed by increasing the time of the wet etching or by increasing the concentration of the etching solution.

In addition, a plurality of small unevennesses are coupled to a pyramid-shaped inclined surface formed in a region SE that contacts the emitter portion 121 of the back surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150. The unevenness P2 ′ may be additionally dry-etched, for example, only in the region SE to be in contact with the emitter portion 121 of the back surface of the semiconductor substrate 110 except for the region S1 to overlap the buffer layer 150. It may be formed by further performing reactive ion etching (RIE).

In this manner, the surface area per unit area of the back surface of the semiconductor substrate 110 in the region of the back surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150 is in contact with the emitter portion 121. The surface area per unit area of the rear surface of the semiconductor substrate 110 in the region S1 overlapping with the buffer layer 150 may be greater than the rear surface of the bottom surface.

Accordingly, the junction surface of the semiconductor substrate 110 and the emitter portion 121 except for the region S1 overlapping the buffer layer 150 among the rear surfaces of the semiconductor substrate 110, or the semiconductor substrate 110 and the rear electric field portion 172. ), The bonding areas SE and SB of the bonding surface can be made larger, and the bonding surface of the emitter portion 121 and the first electrode 141 or the rear electric field portion 172 and the second electrode 142 can be made larger. That can be done than the junction area of the total face of the. As a result, the carrier can be collected more efficiently through the emitter unit 121 and the rear electric field unit 172, and the short circuit current of the solar cell 1 can be further improved.

Therefore, the light of the long wavelength band which is not absorbed by the semiconductor substrate 110 among the light incident on the semiconductor substrate 110 can be more efficiently dispersed through the inclined surface having the finer concavo-convex shape, and can be reflected more efficiently. In addition, there is an effect of generating more carriers in the semiconductor substrate 110. Thereby, the short circuit current of the solar cell 1 can be improved further.

7 and 8 illustrate, as an example, a region in which the emitter unit 121 is in contact with the emitter unit 121 of the rear surface of the semiconductor substrate 110 except for the region S1 where the surface area per unit area of the rear surface of the semiconductor substrate 110 overlaps the buffer layer 150. However, the same may be applied to FIGS. 4 to 6.

That is, the surface area per unit area of the back surface of the semiconductor substrate 110 in the region of the back surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150 is in contact with the back surface electric field portion 172. The surface area per unit area of the rear surface of the semiconductor substrate 110 in the region S1 overlapping the buffer layer 150 may be greater than the rear surface of the semiconductor substrate 110.

For example, irregularities formed in FIG. 8B may be provided in a region of the rear surface of the semiconductor substrate 110 except for the region S1 overlapping with the buffer layer 150 and in contact with the rear electric field unit 172.

In addition, unlike before, the side cross-sectional shape of the concave-convex shape having the first shape includes a trapezoidal shape, and the side cross-sectional shape of the concave-convex shape having the second shape has a shape in which a plurality of small concave-convex concave-convex surfaces are combined with a trapezoidal inclined surface. It may also include.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of right.

Claims (16)

A semiconductor substrate containing impurities of a first conductivity type;
An emitter portion disposed on a rear surface of the semiconductor substrate to form a pn junction with the semiconductor substrate and having a second conductivity type opposite to the first conductivity type;
A rear electric field unit disposed on a rear surface of the semiconductor substrate and containing a higher concentration of impurities of the first conductivity type than the semiconductor substrate;
A first electrode formed on the emitter portion;
A second electrode formed on the rear electric field part; And
And a buffer layer disposed between the first electrode and the second electrode of a rear surface of the substrate,
The surface area per unit area of the back surface of the semiconductor substrate in at least one of the regions in contact with the emitter portion or the backside electric field in the back surface of the semiconductor substrate except the region overlapping the buffer layer overlaps the buffer layer in the back surface of the semiconductor substrate. A solar cell larger than the surface area per unit area of the backside of the semiconductor substrate in the region of being. The method of claim 1,
Unevenness having a first shape is formed in a region overlapping the buffer layer among the back surface of the semiconductor substrate, and at least one of a region in contact with the emitter portion or the backside electric field portion in the backside of the semiconductor substrate except for the region overlapping the buffer layer. A solar cell having irregularities having a second shape different from the first shape in one region. 3. The method of claim 2,
The unevenness having the first shape includes a flat surface at the top portion, and the unevenness having the second shape does not include the flat surface at the top portion. 3. The method of claim 2,
The side cross-sectional shape of the unevenness having the first shape includes a trapezoidal shape, and the side cross-sectional shape of the unevenness having the second shape includes a pyramid shape. 3. The method of claim 2,
The flat surface formed on the top portion of the unevenness having the first shape has a width of 1 to 20 μm. 5. The method of claim 4,
The maximum height among the irregularities having a trapezoidal shape is less than the height of the irregularities having a maximum height among the irregularities having a pyramidal shape. The method according to claim 6,
The maximum height of the irregularities having a trapezoidal shape is 5μm, the maximum height of the irregularities having a pyramidal shape is 15μm. 5. The method of claim 4,
The bottom shape of the irregularities having the trapezoidal shape is the same as the bottom shape of the irregularities having the pyramid shape. 3. The method of claim 2,
And a region in which the unevenness having the second shape is formed in the rear surface of the semiconductor substrate overlaps the bonding surface of the first electrode and the emitter portion. 3. The method of claim 2,
A region of the back surface of the semiconductor substrate in which the unevenness having the second shape is formed is overlapped with the junction surface of the second electrode and the rear electric field. The method of claim 1,
And the emitter portion and the rear electric field portion are in contact with each other, and the buffer layer is disposed on a junction surface of the emitter portion and the rear electric field portion in contact with each other. The method of claim 1,
The buffer layer is a solar cell comprising a non-conductive insulating material. The method of claim 1,
The buffer layer includes at least one of silicon oxide (SiOx) and silicon nitride (SiNx). The method of claim 1,
The emitter unit and the rear electric field unit includes crystalline silicon or amorphous silicon. 3. The method of claim 2,
The side cross-sectional shape of the concave-convex shape having the first shape includes a pyramid shape, and the side cross-sectional shape of the concave-convex shape having the second shape includes a form in which a plurality of small concave-convex concave-convex surfaces are combined with an inclined surface of the pyramid shape. . 3. The method of claim 2,
The side cross-sectional shape of the concave-convex shape having the first shape includes a trapezoidal shape, and the side cross-sectional shape of the concave-convex shape having the second shape includes a form in which a plurality of small concave-convex concave-convexities are combined on an inclined surface of the trapezoidal shape. .

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