KR20140015931A - Receiver for data communication - Google Patents

Abstract

The present invention relates to a receiver for data communication whereby the receiver has a jitter tolerance reinforcement circuit to accurately sample the aligned data aligned by an edge of a recovery clock which makes an input data edge fluctuate by a jitter. An embodiment of the present invention includes: a clock data recovery circuit for outputting a first recovery clock which coincides with a phase of input data by recovering a clock of the input data randomly inputted through an input stage and a second recovery clock which has a 90° phase difference from the phase of the first recovery clock; and a jitter tolerance reinforcement circuit which is connected to an output stage of the clock data recovery circuit to receive the input data, first recovery clock and second recovery clock, generating aligned data by aligning the edge of the input data with the edge of the first recovery clock and sampling the aligned data using the second recovery clock.

Description

 [0001] RECEIVER FOR DATA COMMUNICATION [0002]

The present invention relates to a data communication receiver, and more particularly, to a data communication receiver including a jitter tolerance enhancing circuit capable of accurately sampling alignment data obtained by aligning an edge of input data shaken by jitter to an edge of a recovered clock .

Recently, the most important performance indicator of the receiver (Rx) is the jitter tolerance of the clock and data recovery (CDR) circuit. Jitter tolerance is a number that confirms whether the clock data recovery circuit of the jitter versus input data restores data with a small error rate.

This jitter tolerance is closely related to the bandwidth of the clock data recovery circuit. That is, when the bandwidth size of the clock data recovery circuit is increased, the jitter passage characteristic is improved and the jitter tolerance is increased. However, in this case, there is a disadvantage that the jitter of the output data increases. Conversely, as the bandwidth size of the clock data recovery circuit becomes smaller, the jitter of the input data is reduced by the loop of the clock data recovery circuit, and a relatively clean clock signal is restored. However, in this case, it is difficult to accurately sample the output data shaken by the jitter of the input data.

Thus, a technique for enhancing jitter tolerance is required in the design of a receiver.

It is an object of the present invention to provide a receiver for data communication including a jitter tolerance enhancement circuit capable of correctly sampling alignment data derived by aligning an edge of input data shaken by jitter to an edge of a restored recovered clock.

According to another aspect of the present invention, there is provided a receiver for data communication, which receives input data randomly as an input and restores a clock to output a first restoration clock coinciding with a phase of the input data, A clock data restoration circuit for outputting a second restoration clock having a phase difference of 90 degrees with the clock; And an output terminal connected to the output terminal of the clock data restoration circuit for receiving the input data, the first restoration clock, and the second restoration clock, and generating an alignment data by aligning an edge of the input data with an edge of the first restoration clock, And a jitter tolerance enhancing circuit for sampling the alignment data using the second restoration clock.

The jitter tolerance enhancing circuit receives the input data, the first restoration clock, and the second restoration clock, and generates a plurality of multi-phase signals having a delay of -NΔ to + NΔ (N is a natural number) from the input data A delay line portion; And a sense amplifier for receiving the first restoration clock as data and receiving a first group of phase signals of the plurality of the multiple phase signals as a clock and sampling the first restoration clock as a phase signal of the first group, Flop; XOR gates for detecting signal switching points among the sampled values in the sense-complicated flip-flop and outputting an alignment point detection signal; An encoder for coding the alignment point detection signal; And a second group of phase signals input to the sense-complementary flip-flop, excluding the first group of phase signals, so that the second group of phase signals have the same delay as the first group of phase signals A first copying unit for processing the first copying unit; A selection unit for receiving the second group of phase signals from the first copy unit and selecting and outputting one sorting data according to the alignment point detection signal output from the encoder; A second replica unit for receiving and passing the second restoration clock having passed through the delay line unit and the first replica unit; And a sampler for sampling the alignment data in response to the second restoration clock received from the second copy unit and outputting sampled data as output data.

The delay line unit may be configured to align the first restoration clock and the second restoration clock with the intermediate phase signal among the plurality of the multiple phase signals.

(-3Δ) to Data (+3Δ), the Data (-3Δ) is a first phase signal, the Data (-2Δ) is a second phase signal, the Data (-) is a third phase signal, Data (0) is a fourth phase signal, Data (+ DELTA) is a fifth phase signal, Data (+ 3) is a seventh phase signal, the sense-embedded flip-flop is arranged between the i-th phase signal and the i + 2-phase signal (i = 1, 3, 5) (J is 2, 4, 6) between the phase of the i-th phase signal and the phase of the (i + 2) -th phase signal when a difference between the two sampling values occurs, Data and the edge of the first restoration clock can be matched.

Wherein the encoder is capable of retaining a previous alignment point detection signal of the XOR gates when the first reconstruction clock is faster than the first phase signal or slower than the seventh phase signal and no edge of the first reconstruction clock is detected have.

The first copying unit may be implemented as the sense-complicated flip-flop.

The second copying unit may be implemented with the configuration of the selection unit.

The receiver for data communication according to the embodiment of the present invention includes a jitter tolerance enhancement circuit to align the edges of the input data to the edges of the first restoration clock for each edge of each input data to compensate for jitter per edge of each input data It is possible to accurately sample the sorting data.

 In addition, the data communication receiver according to the embodiment of the present invention implements the jitter tolerance enhancement circuit in a feedforward structure leading to a delay line portion, a sense-complied flip-flop, XOR gates, an encoder, a selector and a sampler Thus, it is possible to prevent the occurrence of errors in the output data by effectively aligning the edges of the input data with the clean first clone clock and effectively removing the jitter having a very fast frequency.

1 is a block diagram of a receiver for data communication according to an embodiment of the present invention.
2 is an alignment graph of data and clock of the jitter tolerance enhancing circuit of FIG.
FIG. 3 is a diagram showing an EYE diagram of input data, alignment data, and sampled data of the jitter tolerance enhancement circuit of FIG. 1;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a receiver for data communication according to an embodiment of the present invention. FIG. 2 is an alignment graph of data and a clock of the jitter tolerance enhancing circuit of FIG. 1, ≪ / RTI > FIG. 7 is a diagram showing an EYE diagram of data, alignment data, and sampled data.

Referring to FIG. 1, a data communication receiver 100 according to an embodiment of the present invention includes a clock data recovery circuit (CDR) 110 and a jitter tolerance enhancing circuit 120.

The clock data restoring circuit 110 receives the random input data Data_In as an input and restores the clock to output clocks CLK_0 and CLK_90 which are restored to the output stage.

The input data Data_In may be jittered data and the recovered clocks CLK_0 and CLK_90 may have a jitter smaller than the jitter of the input data Data_In through the clock data recovery circuit 110. Specifically, the restored clocks CLK_0 and CLK_90 are generated by a first restoration clock CLK_0 and a second restoration clock CLK_90 having a phase difference of 90 degrees from the first restoration clock CLK_0. Respectively.

The first restoration clock CLK_0 is aligned with the phase of the input data Data_In by the operation of the clock data restoring circuit 110 and is aligned with the edge of the input data Data_In, , And the second restoration clock (CLK_90 DEG) is delayed by 90 DEG relative to the phase of the input data (Data_In) by the operation of the clock data restoration circuit 110 and aligned.

The input data (Data_In) includes jitter and can not be fixed and can be shaken. Thus, a clean signal is required to align the shaky input data (Data_In). This signal is a first restoration clock (CLK_0 °) restored by the clock data restoring circuit 110 and the shaken input data (Data_In) can be aligned using the restored first restoration clock (CLK_0 °).

On the other hand, the clock data recovery circuit 110 removes jitter included in the input data Data_In and generates a clean first and second restoration clocks CLK_0 and CLK_90 relative to the input data Data_In, As shown in FIG.

The jitter tolerance enhancing circuit 120 is connected to the output terminal of the clock data recovery circuit 110 and arranges the shaking input data Data_In using the first recovery clock CLK_0 ° and outputs the alignment data to the second restoration clock CLK 90 deg.). The jitter tolerance enhancing circuit 120 includes a delay line unit 121, a sense-amplitude flip flop 122, XOR gates 123, an encoder An encoder 124, a first copying unit 125, a selecting unit 126, a second copying unit 127 and a sampler 128.

The delay line unit 121 includes input data Data_In input to the input terminal of the clock data recovery circuit 110 and a first recovery clock CLK_0 ° output to the output terminal of the clock data recovery circuit 110, And receives the restoration clock (CLK 90 °).

2, the delay line unit 121 includes a plurality of multi-phase signals Data (-3Δ) to Data (Data_In) having a delay from input data (Data_In) to -NΔΔ to + NΔ The delay line unit 121 does not generate a delay exactly like a delay locked loop (DLL), and thus generates 1 UI (Unit: The delay line unit 121 generates a plurality of multi-phase signals Data (-3) through Data (+ 3) so as to have a delay of less than Interval The total delay time of the plurality of multi-phase signals Data (-3Δ) to Data (+3Δ) can not exceed 1 UI even if PVT changes due to a margin before Data (+ 3Δ) Of the plurality of multi-phase signals Data (-3Δ) to Data (+3Δ) if the total delay time of the multi-phase signals (Data (-3Δ) to Data (+3Δ) First blessing (-3 DELTA) is the first phase signal, and Data (-2 DELTA) is the first phase signal, Data (-3 DELTA) is the first phase signal, and Data Data (+) is a fifth phase signal, Data (+ 2) is a sixth phase signal, Data (-) is a third phase signal, Data (+ 3Δ) is referred to as a seventh phase signal. In the present invention, the number of the plurality of multi-phase signals is set to seven, but the number may be set to be equal to or less than seven.

The delay line unit 121 receives the first restoration clock CLK_0 and the second restoration clock CLK_90 from among the plurality of the plurality of phase signals Data (+ 3Δ) to Data (-3Δ) Is set to be aligned with the fourth phase signal Data (0), which is a phase signal. This is to select multiple phases in the range of -3Δ to +3 ΔΔ based on the phase of the fourth phase signal (Data (0)). The range of -3 △ to + 3 △ can cover the range of 1 UI. Accordingly, when the edge (switching point) of the input data Data_In is shaken by the jitter, a clean first restoration clock of the plurality of multi-phase signals Data (-3Δ) to Data (+3Δ) Phase signal corresponding to the edge of the first clock signal CLK_ 0 ° and align the input data Data_In with a clean first restoration clock CLK_ 0 °.

The sense-complicated flip-flop 122 receives a first group of phase signals (odd-numbered phase (0)) of the plurality of multi-phase signals Data (-3Δ) The third phase signal Data (-?), The fifth phase signal Data (+?), The seventh phase signal Data (+3 (3) ) And the first restoration clock (CLK_0 °).

Specifically, the sense-embedded flip-flop 122 receives the first restoration clock CLK_0 ° as data and outputs a first phase signal (Data (-3Δ)) as the first group of phase signals, The third phase signal Data (- DELTA), the fifth phase signal Data (+ DELTA), and the seventh phase signal Data (+ 3 DELTA) as clocks and outputs the first restoration clock signal CLK_0 The first phase signal Data (-3Δ), the third phase signal Data (- Δ), the fifth phase signal Data (+ Δ), and the seventh phase signal Data (+ 3 DELTA)), which is a circuit for detecting an alternate point (signal switching point) among the values sampled through the XOR gates 123, and passes through the encoder 124 an alignment point detection signal do.

For example, the sense-embedded flip-flop 122 has an edge of the first restoration clock (CLK_0) between the i-th phase signal and the i + 2 phase signal (i = 1, 3, 5) (J = 2, 4, 6) between the phase of the i-th phase signal and the phase of the (i + 2) -th phase signal to generate the input data Data_In, And the edge of the first restoration clock (CLK_0).

For example, the sense-embedded flip-flop 122 may perform a first restoration operation between the phase of the third phase signal Data (- DELTA) and the phase of the fifth phase signal Data (+ DELTA) If there is a difference between the two sampling values due to the edge of the clock CLK_0 °, a fourth phase between the phase of the third phase signal Data (- DELTA) and the phase of the fifth phase signal Data (+ DELTA) The phase of the signal Data (0) is selected to match the edge of the input data Data_In with the first restoration clock CLK_0.

The sense-embedded flip-flop 122 outputs a first restoration clock CLK_0 between the phase of the first phase signal Data (-3?) And the phase of the third phase signal Data (-?) And a difference between the two sampling values is generated, a second phase signal ((-)) between the phase of the first phase signal Data (-3Δ) and the phase of the third phase signal Data Data (-2?) Is selected so that the edges of the input data Data_In and the first restoration clock CLK_0 are aligned.

As described above, the first group of phase signals (Data (-3Δ)), the third group of phase signals (Data (-)), the fifth group of signals (Data (Alignment point detection signal) processed by the first restoration clock signal (Data (+ 3Δ)) and the first restoration clock signal CLK_0 ° is a second group of phase signals (even-numbered phase signals) 2?), The fourth phase signal Data (0), and the sixth phase signal Data (+ 2?).

The encoder 124 codes the alignment point detection signal processed through the XOR gates 124 to be inputted to the selection unit 126. [ The encoder 124 may determine that the first restoration clock CLK_0 ° is faster than the first phase signal Data -3Δ or slower than the seventh phase signal Data 3 + (CLK_0) is not detected, it serves as a register for retaining the previous alignment point detection signal of the XOR gate 123 as it is.

The first copying unit 125 is connected to the sense-embedded flip-flop 122 and the sense-complementary flip-flop 122 among the plurality of the multi-phase signals Data (-3?) To Data (+3?) Output from the delay line unit 121 The second phase signal Data (-2?), The fourth phase signal Data (0), and the sixth phase signal Data (+ 2?), Which are the second group of phase signals that have not passed through the XOR gates 123, ) Includes the sense-embedded flip-flop 122 and the XOR gates 123 (Data-3) of the plurality of multi-phase signals Data (-3Δ) to Data The third phase signal Data (-?), The fifth phase signal Data (+?), The seventh phase signal Data Delay processing is performed so as to have the same delay time as the signal (Data (+ 3 DELTA)). This is because the second phase signal Data (-2Δ), the fourth phase signal Data (0) and the sixth phase signal Data (+ 2Δ), which are the second group of phase signals, The first phase signal Data (-3Δ), the third phase signal Data (--Δ), and the fifth phase signal Data (-3Δ), which are the first group of phase signals, Is input to the selection unit 126 without the adjustment of the phase signal (Data (+ DELTA)) and the seventh phase signal (Data (+ 3 DELTA)) and the delay time and is not the edge of the input data Data_In for jitter compensation The second phase signal (Data (-2)), the fourth phase signal (Data (0)) and the sixth phase signal (Data (+ 2Δ)), which are the phase signals of the second group after jitter has already passed, And can be selected. That is, the first copying unit 125 generates the first group of phase signals Data (-3 (-)) in the sense-complicated flip flop 122 and the XOR gates 123, The delay time corresponding to the delay time in which the phase signal Data (- DELTA), the fifth phase signal Data (+ DELTA) and the seventh phase signal Data (+ 3 DELTA) The second phase signal Data (-2Δ), the fourth phase signal Data (0), and the sixth phase signal Data (+ 2Δ). To this end, the first copying unit 125 has a similar structure to the sense-embedded flip-flop 122 and the XOR gates 123 and is configured to have a similar PVT (Pressure, Volume, Temperature) change. For example, the first copying unit 125 may be implemented as a sense-complicated flip-flop.

The selector 126 is a second phase signal Data (-2Δ), a fourth phase signal Data (0), The sixth phase signal (Data (+ 2Δ)) is input and outputs one alignment data according to the alignment point detection signal output from the encoder 124.

The second copying unit 127 receives and passes the second restoring clock CLK 90 ° that has passed through the delay line unit 121 and the first copying unit 125. The second restoration clock (CLK_90) is a clock for sampling alignment data arranged using the first restoration clock (CLK_0), and the second restoration clock (CLK_90) And has the same configuration as that of the selector 126 to match with that input to the sampler 128 through the receiver.

The sampler 128 samples the aligned data in response to the second restoration clock (CLK_90) input from the second replica 127 and outputs the sampled data JTE_OUT as output data.

3, the window size of the alignment data (Compensated Data) passing through the jitter tolerance enhancing circuit 120 is larger than the window size of the dirty data having the jitter by eliminating the jitter, The sampled data (sampled data) is output as clean output data by sampling the alignment data (Compensated Data).

As described above, the data communication receiver 100 according to an exemplary embodiment of the present invention includes the jitter tolerance enhancing circuit 120 so that the edge of the input data Data_In for each edge of each input data Data_In is divided into a first restoration clock CLK_0), it is possible to accurately sample the alignment data obtained by compensating the jitter for each input data (Data_In) edge.

The receiver 100 for data communication according to an embodiment of the present invention includes a jitter tolerance enhancing circuit 120 as a delay line unit 121, a sense-complied flip-flop 122, XOR gates 123, The input data Data_In is implemented by a feedforward structure that leads to the encoder 124, the selector 126 and the sampler 128 so that the edges of the input data Data_In are immediately aligned with the clean first clone clock CLK_ 0 °, It is possible to effectively prevent the occurrence of errors in the output data by effectively removing jitter having a high frequency.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation and that those skilled in the art will understand that various modifications and equivalent arrangements may be made therein It will be possible.

100: Receiver for data communication 110: Clock data recovery circuit
120: jitter tolerance enhancing circuit 121: delay line unit
122: sense-ampiple flip flop 123: XOR gates
124: Encoder 125:
126: selection unit 127: second copy unit
128: sampler

Claims (7)

A clock recovery circuit for receiving the input data randomly and restoring the clock and outputting a first restoration clock coinciding with the phase of the input data and a second restoration clock having a phase difference of 90 ° with the first restoration clock, Circuit; And
Is connected to an output terminal of the clock data recovery circuit and receives the input data, the first recovery clock, and the second recovery clock to align the edge of the input data with the edge of the first recovery clock to generate alignment data, and the alignment And a jitter tolerance enhancement circuit for sampling data using the second recovery clock. The method of claim 1,
The jitter tolerance enhancing circuit
A delay line unit that receives the input data, the first restoration clock, and the second restoration clock and generates a plurality of multi-phase signals having a delay of -NΔ to + NΔ (N is a natural number) from the input data;
And a sense amplifier for receiving the first restoration clock as data and receiving a first group of phase signals of the plurality of the multiple phase signals as a clock and sampling the first restoration clock as a phase signal of the first group, Flop;
XOR gates for detecting signal switching points among the sampled values in the sense-complicated flip-flop and outputting an alignment point detection signal;
An encoder for coding the alignment point detection signal;
And a second group of phase signals input to the sense-complementary flip-flop, excluding the first group of phase signals, so that the second group of phase signals have the same delay as the first group of phase signals A first copying unit for processing the first copying unit;
A selection unit for receiving the second group of phase signals from the first copy unit and selecting and outputting one sorting data according to the alignment point detection signal output from the encoder;
A second replica unit for receiving and passing the second restoration clock having passed through the delay line unit and the first replica unit; And
And a sampler for sampling the sorting data in response to the second restoration clock received from the second replica and outputting the sampled data as output data. 3. The method of claim 2,
Wherein the delay line unit sets the first restoration clock and the second restoration clock to be aligned with an intermediate phase signal among the plurality of the plurality of phase signals. 3. The method of claim 2,
The plurality of multi-phase signals are Data (-3?) To Data (+3?),
The data (-3Δ) is a first phase signal, the Data (-2Δ) is a second phase signal, the Data (--Δ) is a third phase signal, the Data (0) Data (+ DELTA) is a fifth phase signal, Data (+ 2 DELTA) is a sixth phase signal, and Data (+ 3 DELTA)
The sense-complicated flip-flop has an edge of the first restoration clock between the i-th phase signal and the i + 2-th phase signal (i = 1, 3, 5) (J is 2, 4, 6) between the phase of the i-th phase signal and the phase of the (i + 2) -th phase signal to match the input data with the edge of the first recovery clock And a receiver for data communication. 5. The method of claim 4,
The encoder maintains a previous alignment point detection signal of the XOR gates when the first restoration clock is earlier than the first phase signal or slower than the seventh phase signal and no edge of the first restoration clock is detected And a receiver for data communication. 3. The method of claim 2,
Wherein the first replica unit is implemented with the sense-complicated flip-flop. 3. The method of claim 2,
And the second replica is implemented with the configuration of the selector.

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