KR20140012608A - Programming non-volatile memory with bit line voltage step up - Google Patents

Abstract

Threshold voltage of nonvolatile memory device 196 using a programming technique in which the bit line voltage for storage elements having target data states 402, 404, 406 is stepped up at the same rate as the step up in the program voltage. The distributions A, B, C are narrowed and / or the programming time is reduced. Step-up of the bit line voltage is performed at different times in the programming pass, depending on their target data states 402, 404, 406, for different subsets of the storage elements. The start and stop of the step up of the bit line voltage Vbc may be set based on the fixed program pulse number or adaptive based on the programming process. Variants include using fixed bit line steps, variable bit langney steps, data state-dependent bit line steps, the option not to step up bit lines for one or more data states, and the option to add additional bit line biases. do.

Description

Programming Non-Volatile Memory Using Bit Line Voltage Step-Up {PROGRAMMING NON-VOLATILE MEMORY WITH BIT LINE VOLTAGE STEP UP}

The present invention relates to a nonvolatile memory.

Semiconductor memories are becoming increasingly common in various electronic devices. For example, nonvolatile semiconductor memory is used in cell phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. EEPROMs and flash memories are, among others, the most widely used nonvolatile semiconductor memories. In contrast to traditional full-featured EEPROMs, using flash memory (also a kind of EEPROM), the contents of an entire memory array or the contents of a portion of memory can be erased in one-step. Can be.

Traditional EEPROM and flash memories both use floating gates that are located above the channel region in a semiconductor substrate and are isolated from the channel region. The floating gate is located between the source and drain regions. The control gate is provided over the floating gate and insulated from the floating gate. The threshold voltage V _th of the transistor is thus controlled by the amount of charge retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to allow conduction between the source and drain of the transistor is controlled by the level of charge on the floating gate.

Some EEPROM and flash memory devices have a floating gate that is used to store two charge ranges, so that the memory device is programmed / erased between two states, for example an erased state and a programmed state. Can be. Such flash memory devices are sometimes referred to as binary flash memory devices because each memory element can store one bit of data.

Multi-state (also referred to as multi-level) flash memory devices are implemented by identifying a plurality of distinctly allowed / valid programmed threshold voltage ranges. Each individual threshold voltage range corresponds to a predetermined value for the set of data bits encoded at the memory device. For example, each memory device can store two bits of data when the device can be located in one of four discrete charge bands corresponding to four distinct threshold voltage ranges. .

In particular, as memory devices shrink in size, techniques are needed to accurately program threshold voltage ranges while reducing programming time.

1 is a block diagram of a nonvolatile memory system using single row / column decoders and read / write circuits.
FIG. 2 is a block diagram illustrating one embodiment of the sense block 100 of FIG. 1.
3 shows blocks of NAND flash memory cells in memory array 155 of FIG. 1.
4A shows an example threshold voltage distribution and one-pass programming, referred to as a "one-pass write" programming technique.
4B and 4C show exemplary threshold voltage distribution and two-pass programming, referred to as "two-pass write" programming.
5A shows an example threshold voltage distribution and 1-pass write programming, where up to two programming speeds may be used in a “quick pass write (QPW)” programming option.
FIG. 5B shows an example threshold voltage distribution for the A-state during two-pass programming, in a first programming pass, up to two programming speeds may be used with the QPW programming option.
5C shows an example threshold voltage distribution for the A-state during two-pass programming, in a second programming pass, up to two programming speeds may be used with the QPW programming option.
6A, 6B, and 6C illustrate first, second, and third programming of a three pass programming operation, referred to as a “three pass write” programming technique, in which a middle or lower middle-middle (LM) verify voltage is used. Show the paths respectively.
FIG. 6D illustrates a second programming pass of a two-pass programming operation, referred to as a “two-pass write” programming technique, in which FIG. 6A shows a first programming pass, and up to two programming speeds may be used with the QPW programming option. Illustrated.
7A shows a two-pass programming operation for a set of storage elements in word line order back-and-forth.
7B shows a three-pass programming operation for a set of storage elements in word-line order back-to-back.
8 shows the relationship between the highest Vpgm needed to program the storage element and the bit line voltage of the storage element.
9A illustrates a programming technique in which the bit line voltage is stepped up.
FIG. 9B illustrates the data states undergoing verify operations as a function of the number of program pulses, as an example of the programming technique of FIG. 9A.
FIG. 10 illustrates the program-verify operations as a function of the number of program pulses, for the sequence 960 of FIG. 9B.
11A shows the step-up of the bit line voltage as a function of the number of program pulses for different data states, where a common stem size is used for all data states.
11B shows a trigger condition for initiating a bit line step up loop for A-state storage elements.
11C shows a trigger condition for stopping the bit line step up loop for the A-state storage elements.
FIG. 12A shows the programming rate as a function of the number of program pulses for A-state storage elements, according to FIG. 11A.
FIG. 12B shows the programming rate as a function of the number of program pulses for B-state storage elements, according to FIG. 11A.
FIG. 12C shows the programming speed as a function of the number of program pulses for the C-state storage elements, according to FIG. 11A.
Figure 13 shows the step up of the bit line voltage as a function of the number of program pulses for different data states, where for all data states, smaller step size, then larger step size, then smaller step size Is used.
Figure 14 shows the step up of the bit line voltage as a function of the number of program pulses for different data states, where a larger step size is used for lower data states, and smaller steps for the highest data state. Size is used.
Figure 15 shows the step up of the bit line voltage as a function of the number of program pulses for different data states, a common step size is used for all data states, and additional bit line voltages are added based on the threshold voltage level. do.

Provided are a method and a non-volatile storage system for accurately programming threshold voltage ranges while reducing programming time.

During a programming operation, there is a tradeoff between reducing programming time and achieving narrow threshold voltage ranges for different data states. The programming speed can be increased by using a larger program pulse step size. However, this results in a large overshoot beyond the verify level, resulting in a wide threshold voltage (Vth) range. On the other hand, if a smaller program pulse step size is used, a narrow Vth range is achieved at the expense of increased programming time. Another technique is a double verify technique, which verifies storage elements at two separate verify levels for each state. When the Vth of the storage element exceeds the lower verify level, its programming speed is slowed down by applying bit line bias. Without the bit line bias, the Vth of the storage element increases by approximately the same amount as the step size of the program pulse for each program pulse. Using bit line bias, the Vth of the storage element is increased for each program pulse by an amount less than the step size of the program pulse. Thus, the storage element can be programmed at a reduced speed when its Vth exceeds the lower verify level of the target data state, and from further programming when the Vth exceeds the higher verify level of the target data state. It can be locked out.

In the dual verification technique, the distance between the lower and upper level of verification for each state is set to the point where the silicon is optimized for the Vth distribution and the narrowest Vth distribution. If the gap between the lower verify level and the upper verify level is too high, the Vth increases of the storage element will change back to a steady state value (e.g., equal to the program pulse step size), so the benefit of the double verify technique is not realized. Do not. On the other hand, if the gap between the lower verify level and the upper verify level is too small, Vth of many storage elements may jump over the gap in one program pulse and thus their programming speed does not slow down. In general, the optimum gap is a function of the program pulse step size. The larger the program pulse step size is optimal, because Vth jumps larger for each program pulse and therefore requires a larger gap to ensure that Vth goes beyond the upper verify level without jumping just above the gap using only one program pulse. The gap tends to increase.

In addition, with the double verify technique, as the memory devices scale down, the program noise becomes more severe. In a particular program pulse, even though multiple Vths of the storage elements jump by about the same amount as the program pulse step size, many storage elements have a much higher Vth jump. As a result, the optimum gaps for different storage elements are different and difficult to optimize.

In order to overcome these problems, a programming technique is provided that ensures that many of the storage elements are slow in programming so that the Vth distribution widths are narrowed. In this technique, the bit line voltage Vbl for the storage elements with a particular target data state is steped up with sequential program pulses over a range of a plurality of consecutive program pulses. Different ranges of program pulses may be used for each target data state, but the ranges may overlap. Bit line voltage step up may occur within a time period when a number of storage elements are close to completing programming to their target data state. During this period, the rate of increase of the Vth of these storage elements is effectively lowered, leading to a lower Vth distribution. In addition, the bit line voltages of all storage elements that are being programmed to a particular target data state are stepped up, so that all storage elements belonging to that target state that are not yet locked out are slow in programming.

Modifications to programming techniques include fixed bit line steps, variable bit line steps, data state-dependent bit line steps, the option to not step up bit lines for one or more data states, and additional bit line biases to bit line steps. This includes using additional options.

An exemplary memory system that can be used with the programming technique is discussed next. 1 is a block diagram of a nonvolatile memory system using single row / column decoders and read / write circuits. The figure shows a memory device 196 having read / write circuits for reading and programming a page of storage elements in parallel, according to one embodiment. Memory device 196 may include one or more memory die 198. The memory die 198 includes a two dimensional memory array 155 of storage elements, control circuit 110, and read / write circuits 165. Memory array 155 is discussed further with respect to FIG. 3.

In some embodiments, the array of storage elements can be three dimensional. Memory array 155 is addressable by word lines through row decoder 130 and by bit lines through column decoder 160. Read / write circuits 165 include a plurality of sense blocks 100 and allow a page of storage elements to be read or programmed in parallel. Generally, controller 150 is included in the same memory device 196 (eg, removable storage card) as the one or more memory dies 198. Commands and data are transferred between the host and the controller 150 via lines 120 and between the controller and one or more memory die 198 via lines 118.

The control circuit 110 performs memory operations on the memory array 155 in cooperation with the read / write circuits 165, the state machine 112, the on-chip address decoder 114, and Power control module 116. State machine 112 provides chip-level control over memory operations. The on-chip address decoder 114 provides an address interface between the address used by the host or memory controller and the hardware address used by the decoders 130, 160. The power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations.

In some implementations, some of the components of FIG. 1 can be combined. In various designs, one or more components other than memory array 155 may be considered (either alone or in combination) as management or control circuitry. For example, one or more control circuits include control circuit 110, state machine 112, decoders 114/160, power control 116, sense blocks 100 (processor 192 of FIG. 2). ), Read / write circuits 165, controller 150, and the like, or a combination thereof. The sense block 100 is further discussed with respect to FIG. 2.

In yet another embodiment, the nonvolatile memory system uses dual row / column decoders and read / write circuits. Access to the memory array 155 by various peripheral circuits is implemented in a symmetrical manner on the opposite sides of the array, reducing the density of access lines and circuits on each side in half. Thus, the row decoder is split into two row decoders and the column decoder is split into two column decoders. Similarly, read / write circuits include read / write circuits that connect to the bit lines from the bottom and read / write circuits that connect to the bit lines from the top of the array 155. Divided. In this way the density of the read / write modules is essentially reduced by half.

2 is a block diagram illustrating one embodiment of a sense block. The separate sense block 100 is divided into one or more core portions referred to as sense modules 180 or sense amplifiers, and a common portion referred to as management circuit 190. In one embodiment, there will be a separate sense module 180 for each bit line and one common management circuit 190 for a set of multiple (eg, 4 or 8) sense modules 180. . Each of the sense modules in the group communicates with an associated management circuit via a data bus 172. Thus, there are one or more management circuits in communication with the sensing modules of the set of storage elements.

The sensing module 180 includes a sensing circuit 170 that performs sensing by determining whether the conduction current in the connected bit line is above or below a predetermined threshold level. Sense module 180 also includes a bit line latch 182 that is used to set a voltage condition for the connected bit line. For example, a predetermined state latched in bit line latch 182 will result in the connected bit line being pulled to a state indicating program prohibition (eg, 1.5-3 V). For example, flag = 0 can inhibit programming, whereas flag = 1 does not inhibit programming.

The management circuitry 190 includes a processor 192, four exemplary sets of data latches 194-197 and an I / O interface 196 connected between the set of data latches 194 and the data bus 120. Include. One set of data latches may be provided for each sense module, and three data latches identified by QDL, UDL, and LDL may be provided for each set. The processor 192 determines operations stored in the sensed storage element and performs operations such as storing the determined data in a set of data latches. Each set of data latches 194-197 stores data bits determined by the processor 192 during a read operation, and data bits coming from the data bus 120 during a program operation (programmed in memory). Used to store recorded data). I / O interface 196 provides an interface between data latches 194-197 and data bus 120.

During reading, the operation of the system is under the control of state machine 112 which controls the supply of different control gate voltages to the addressed storage element. As step through various predetermined control gate voltages corresponding to the various memory states supported by the memory, the sensing module 180 may trip to one of these voltages and the bus 172. A corresponding output will be provided from the sensing module 180 to the processor 192 through. At that point, the processor 192 takes into account the information about the control gate voltage applied from the state machine via the tripping event (s) of the sense module and the input lines 193, resulting in Determine the memory state. It then computes binary encoding for the memory state and stores the resulting data bits in data latches 194-197. In another embodiment of the management circuit 190, the bit line latch 182 plays a double dudy as a latch for latching the output of the sense module 180 and also as a bit line latch as described above. do.

Some embodiments may include a plurality of processors 492. In one embodiment, each processor 492 will include an output line (not shown) such that each output line is wired-OR together. In some embodiments, the output lines are inverted before being connected to the wired-OR line. This configuration allows for a quick decision as to when the programming process is completed during the program verification process, because the state machine receiving the wired-OR determines when all the bits being programmed have reached the required level. Because you can decide. For example, when each bit has reached its required level, a logical zero for that bit will be sent to the wired-OR line (or data 1 will be reversed). When all the bits output data 0 (or when data 1 is inverted), the state machine knows to terminate the programming process. As each processor communicates with eight sense modules, the state machine needs to read the wired-OR line eight times, or logic is added to the processor 492 so that the state machine reads the wired-OR line only once. Accumulate the results of the associated bit lines as much as possible. Likewise, by correctly selecting logic levels, the global state machine can detect when the first bit changes its state and accordingly changes the algorithm.

During program or verify operations, the data to be programmed (write data) is stored from the data bus 120 in the set of data latches 194-197. The program operation includes a series of programming voltage pulses applied to the control gates of the addressed storage elements under the control of the state machine. Following each program pulse a read back (verification) is performed to determine if the storage element has been programmed to the desired memory state. In some cases, processor 192 monitors the read back memory state with respect to the required memory state. When the two states match, the processor 192 sets the bit line latch 182 to cause the bit line to be pulled into a state indicating program prohibition. Although the program pulses do not appear on the control gate, this prevents the storage element coupled to the bit line from being further programmed. In other embodiments, the processor initially loads the bit line latch 182, and the sense circuitry sets it to a prohibited value during the verify process.

Each set of data latches 194-197 may be implemented as a stack of data latches for each sense module. In one embodiment, there are three data latches per sense module 180. In some embodiments, the data latches are implemented as a shift register such that the parallel data stored therein is converted to serial data for the data bus 120 or vice versa. All data latches corresponding to the read / write block of the M storage elements can be linked together to form a block shift register, so that the data block can be input or output by serial transfer. In particular, the bank of read / write modules is adapted so that each of its set of data latches is capable of transferring data into or out of the data bus as if they were part of a shift register for the entire read / write block. Will shift sequentially.

The data latches identify when the associated storage element has reached a particular milepost in programming operations. For example, the latches may have a Vth of the storage element below (a) below the lower verify level (eg, VvaL, VvbL or VvcL in FIG. 4), (b) above the lower verify level in slow programming mode. It may be identified that it is higher, above target verification level, in higher, below target verification level (eg, Vva, Vvb or Vvc in FIG. 4), or (c) in prohibition or lock out mode. The data latches indicate whether the storage element currently stores one or more bits from one page of data. For example, LDL latches can be used to author a lower page of data. LDL latches are flipped (eg, from 0 to 1) when the lower page bit is stored in the associated storage element. ULD latches may be used to store an upper page of data, for example. The ULD latch is flipped when the upper page bits are stored in the associated storage element. This occurs when the associated storage element completes programming, for example when its Vth exceeds a target verify level such as Vva, Vvb, or Vvc. QDL latches can be flipped when the associated storage element is in slow programming mode.

3 shows blocks of NAND flash memory cells in memory array 155 of FIG. 1. The memory array can include many blocks. Each example block 300, 310 includes a number of NAND strings and respective bit lines (eg, BL0, BL1,...) That are shared between the blocks. Each NAND string is connected to one end of the drain select gate SGD, and the control gates of the drain select gates are connected through a common SGD line. The NAND strings are connected to a source select gate at their other end, which in turn is connected to a common source line 320. 64 word lines (eg, WL0-WL63) extend between the source select gates and the drain select gates.

In addition to NAND flash memory, other types of nonvolatile memory may also be used. For example, another type of memory cell useful in flash EEPROM systems uses nonconductive dielectric materials instead of conductive floating gates to store charge in a nonvolatile manner. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO”) is sandwiched between the surface of the semiconductor substrate and the conductive control gate over the memory cell channel. The cell is programmed by injecting electrons from the cell channel into nitride, where the electrons are trapped and stored in a confined region. This stored charge then changes the Vth of the channel portion of the cell in a detectable manner. The cell is erased by injecting hot holes into the nitride. Similar cells may be provided in a split-gate configuration in which the doped polysilicon gate extends over a portion of the memory cell channel to form individual select transistors.

In another technique, NROM cells are used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends across the channel between the source and drain diffusions. Charge for one data bit is localized in the dielectric layer adjacent to the drain, and charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by individually reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

4A shows an example Vth distribution and one-pass programming, referred to as a "one-pass write" programming technique. The programming pass will generally encompass a series of multiple program-verify operations performed starting from an initial Vpgm level for a set of storage elements and proceeding to a final Vpgm level until one or more respective verify levels are reached. Example Vth distributions for the storage element array are provided for the case where each storage element stores two data bits. The first Vth distribution 400 is provided for erased (E-state) storage elements. Three Vth distributions 402 404 and 406 represent each of the programmed states A, B and C. In one embodiment, the threshold voltages in the E-state distribution are negative and the threshold voltages in the A-, B-, and C-state distributions are positive.

The number of storage elements in a particular state may be determined by maintaining a count of storage elements whose Vth is determined to exceed a corresponding verify level.

Each individual Vth range corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the storage element and the Vth levels of the storage element depends on the data encoding technique adopted for the storage elements. In one embodiment, data values are assigned to the Vth ranges using gray code assignment and thus only one bit will be affected if the Vth of the floating gate is shifted to its neighboring physical state in error. One example is "11" to Vth range E (state E), "10" to Vth range A (state A), "00" to Vth range B (state b), and "01" to Vth range C Assign to (state C). However, in other embodiments, gray code is not used. Four states are shown, but other multi-state structures including more or less than four states may also be used.

Three read reference voltages Vra, Vrb, Vrc are also provided for reading data from the storage elements. By testing whether the Vth of a given storage element is above or below Vra, Vrb and Vrc, the system can determine the state (eg, programming condition) to which the storage element belongs.

In addition, three target verification reference voltages Vva, Vvb, Vvc are provided. When programming the storage elements to state A, the system will test whether the storage elements have a Vth equal to or greater than Vva. When programming the storage elements to state B, the system will test whether the storage elements have a threshold voltage equal to or greater than Vvb. When programming the storage elements to state C, the system will determine whether the storage elements have a Vth equal to or greater than Vvc.

In one embodiment, the storage elements can be programmed directly from the E-state into any programmed state (A, B or C), as known as full sequence programming. For example, a population of storage elements to be programmed may first be erased so that all storage elements in that population are in erased state E. A series of program pulses such as shown in FIG. 10 will then be used to program the storage elements directly into state A, B or C. Some storage elements are programmed from state E to state A, while other storage elements are programmed from state E to state B and / or from state E to state C.

4B and 4C illustrate exemplary threshold voltage distribution and two-pass programming, referred to as a "two-pass write" programming technique. In this approach, lower or higher verify levels are used for one or more data states. For example, VvaL and Vva are the low and high verify levels for A-state, respectively, VvbL and Vvb are the low and high verify levels for B-state, respectively, and VvcL and Vvc are each C- Low and high verify levels for the state. The lower verify level is an offset from the upper verify level. The verify level can indicate voltage or current.

During programming, if the Vth of an A-state storage element (which is intended to be programmed to A-state as a target state) is less than or equal to VvaL, the storage element is programmed in a fast programming mode. This can be accomplished by grounding the bit line. When Vva > Vth > VvaL, the storage element is programmed in slow programming mode, for example, by raising the associated bit line voltage to a level between ground and the complete inhibit or lockout level. This provides greater precision by preventing large step increases_ and thus a narrower Vth distribution. When Vth> Vva, the storage element is locked out from further programming. A B-state storage element (which is intended to be programmed to a B-state) may have a fast and slow programming mode: In one technique, the highest state, such as the C-state, is less advantageous than the other states, so The slow programming mode is not used for the same highest state: VvcL is shown to allow the slow programming mode for the C state.

In the example of eight-state programming, using the erase state and seven program states A-G, fast and slow programming modes can be used, for example, for states A-F.

In the first programming pass (FIG. 4B), the A-, B- and C-state storage elements are transferred from the E-state 400 to the A-, B-, and C-states (sub distributions 401, 403, 405, respectively). Is programmed to each of the lower verify levels (VvaL, VvbL or VvcL). In the second programming pass (FIG. 4C), the A-, B-, and C-state storage elements are finally distributed from the sub-distributions 401, 403, 405 using verify levels Vva, Vvb and Vvc, respectively. Programs 402, 404, 406, respectively.

5A shows an example threshold voltage distribution and 1-pass write programming, where up to two programming speeds can be used as a QPW program option. In general, for each target state, a verify level can be defined that triggers a slower programming speed for the storage element when it is exceeded. This verify level can be different from the verify level that signals the end of the programming pass. In this example, a single programming pass is used to program the A-state storage elements from the E-state distribution 500 to the A-state distribution 502, thereby passing the verify level Vva-speed, The verify level Vva-speed acts as a checkpoint to trigger a slower programming speed for each A-state storage element where Vva > Vth > Vva-speed, for example, by raising the associated bit line voltage. A-state storage elements with Vth ≦ Vva-speed are programmed at higher speeds, for example by keeping the bit line voltage grounded. All A-state storage elements (forming distribution 502) where Vth reaches Vva are locked out from further programming.

Similarly, a single programming pass is used to program the B-state storage elements from the E-state distribution 500 to the B-state distribution 504, thereby passing the verify level Vvb-speed, which is above the verify level Vvb-speed. Acts as a checkpoint to trigger a slower programming speed for each B-state storage element where Vvb > Vth > Vvb-speed. B-state storage elements for Vth≤Vvb-speed are programmed at higher speeds. All B-state storage elements (forming distribution 504) where Vth reaches Vvb are locked out from further programming.

In addition, a single programming pass is used to program the C-state storage elements from the E-state distribution 500 to the C-state distribution 506, thereby passing the verify level Vvc-speed, wherein the verify level Vvc-speed Acts as a checkpoint that triggers a slower programming speed for each C-state storage element where Vvc > Vth > Vvb-speed. C-state storage elements with Vth ≦ Vvc-speed are programmed at higher speeds. All C-state storage elements where Vth reaches Vvc (which forms distribution 506) are locked out from further programming.

Compared to the techniques of FIGS. 4A-4C, two programming passes are used in the "two-pass write" technique in this programming option with reference to up to two programming speeds. This is done to reduce the effects of interference effects from neighboring storage elements. In the first pass, all storage elements are programmed close to their final target Vth. Then, during the second pass, the storage elements are programmed to reach their final target Vth. Thus, the total Vth shift between the first path and the second path is smaller and thus the corresponding interference effect on neighboring storage elements is also smaller. Programming can be, for example, in the order shown in FIGS. 7A and 7B discussed below. During the second pass, the storage elements are already programmed close to their target, so when programming the storage elements, the storage elements are initially programmed slower naturally because the Vth of the storage elements is higher than their steady state values. This "pass write effect" helps to make the final Vth distribution more dense.

A programming option that can use up to two programming speeds can be referred to as a "quick pass write" (QPW) technique. QPW may be used independently in the first or second pass of a two pass technique, or both. For each pass we use QPW, sub-validation levels (Vva-speed, Vvb-speed, VVc-speed) are used that are below the verification level at which the programming pass ends and lockout occurs. This lower verify level acts as a checkpoint to slow programming, but does not trigger lockout of the storage device. In QPW, applying a bit line bias to the associated channel region of the storage device artificially slows the programming speed of the storage device. It should also be noted that the QPW-verification levels (Vva-speed, Vvb-speed, Vvc-speed) can be optimized independently. There is an optimal gap between Vva-speed and Vva that can achieve the maximum benefit of QPW in compacting the Vth distribution. The QPW-verify levels do not depend on the verify levels of the previous programming pass. The optimal gap mentioned may be the same or different for each target state. In QPW, there are several storage devices that can be programmed at only one speed-not two speeds-such as an A-state storage device whose Vth jumps just above Vva-speed to reach Vva using one programming pulse. It should also be noted that there may be. Such storage elements reach their target levels without experiencing slow programming. Thus, not all storage elements are programmed at two speeds in QPW. In general, however, most storage elements are programmed at two speeds.

5B shows an exemplary threshold voltage distribution for the A-state during two-stage programming during which a first programming pass, up to two programming speeds may be used with the QPW programming option. Although only one A-state is examined for clarity, other target data states can be similarly processed. In this case, the A-state storage elements pass Vva-speed in the first programming pass, so that the programming of the A-state storage elements is fast for the first part of the first programming pass and for the second part of the one programming pass. slow. Thus, in the first programming pass, the A-state storage elements transition from the E-state distribution 500 to the lower A-state distribution 501 defined by VvaL, thereby passing through Vva-speed, wherein the Vva -speed acts as a checkpoint to trigger a slower programming speed for each A-state storage device. Thus, the speed of the A-state storage elements slows down as they transition to the lower A-state distribution 501 and signals the end of the first programming pass for each A-state storage element where Vth> VvaL. In the second programming pass, the A-state storage elements are programmed from distribution 501 to the distribution 502 defined by Vva and the end of the second programming pass for each A-state storage element where Vth> Vva. Signal. As discussed below, the second programming pass may optionally also use the OPW.

5C shows an example threshold voltage distribution for the A-state during two-pass programming where up to two programming speeds can be used with the QPW programming option during the second programming pass. Again, only one A-state is examined for clarity, but other target data states can be similarly processed. In this case, the A-state storage elements pass the verify level Vva_speed1 (different from Vva_speed in FIG. 5) in the second programming pass. First, the A-state storage elements transition from the E-state distribution 500 to the lower A-state distribution 501 defined by VvaL and have a first programming for each A-state storage element where Vth> VvaL. Signal the end of a path. As illustrated in FIG. 5B, the first programming pass may optionally use QPW. In the second programming pass, the A-state storage elements first transition from distribution 501 to distribution 502 at high speed when Vth ≦ Vva_speed1 and then at low speed when Vth> Vva_speed1. The end of the second programming pass is signaled for each A-state storage element where Vth> Vva.

Steps 6a, 6b, and 6c are first, second, and third programming of a three-pass programming operation, referred to as a "three-pass write" programming technique, in which an intermediate or lower-middle state is used. Each step is shown. This programming technique reduces the effect of floating gate-to-floating gate coupling on any particular storage element by writing to adjacent storage elements for previous pages and then to a particular storage element for a particular page. . In one exemplary embodiment, the nonvolatile storage elements use two data states to store two bits of data per storage element. For example, the E-state is an erased state and states A, B, and C are program states. As before, E-state stores data 11, state A stores data 01, state B stores data 00, and state C stores data 10. Other encodings of data-to-physical data states can also be used. Each storage element stores two pages of data. For reference purposes, these data pages will be referred to as upper pages and lower pages. However, they may be labeled differently.

In the first programming step, a lower page is programmed for the selected word line WLn. For example, this may correspond to step “1” (discussed below) in FIG. 7B. If the lower page remains data 1, the storage element state remains in state E (distribution 600). If the data is programmed to zero, the threshold voltage of the storage elements on WLn is raised so that the storage elements are programmed to an intermediate (LM or lower intermediate) state (distribution 606). 6A thus shows the programming of storage elements from the E-state to the LM-state.

In one embodiment, after the storage element is programmed from the E-state to the LM-state, that neighboring storage element on the adjacent word line WLn + 1 in the NAND string will be programmed with respect to its lower page. This would have the effect of widening the Vth distribution 606 for the state LM for the storage elements on WLn. Apparent widening of this Vth distribution will be processed when programming the upper page. The E state distribution 600 will also be widened. After the first programming pass for WLn is performed, a similar first programming pass may be performed for WLn, as indicated by step “2” in FIG. 7B.

6B shows programming of the upper page with lower verify levels VvaL, VvaB, VvAc. For example, this may correspond to step “3” in FIG. 7B. Furthermore, in one embodiment, prior to upper page programming, a read operation is performed to determine which storage elements belong to the E-state and which storage elements belong to the LM-state. This read operation may be performed at read level Vra or at any other suitable voltage level between the E-state and LM-state Vth distributions. This step is performed in an implementation in which the lower page data of the latches are removed after programming the lower page on WLn, so a latch can be used for the lower page data for WLn + 1. In this case, before programming the upper page on WLn, a read is performed to determine the lower page data. In other implementations, such as when a binary cache is used that can store data for all pages of a word line across different programming passes of the word line, this read step is not necessary.

If the storage element is in the E-state and the upper page is 1, the storage element will remain in the E-state (distribution 600). If the storage element is in the E-state and its upper page data is zero, the Vth of the storage element will rise above VvaL (distribution 602). If the storage element is in LM-state 606 and the upper page data is zero, the Vth of the storage element will be programmed above VvbL (distribution 608). If the storage element is in LM-state 606 and the upper page data is 1, the Vth of the storage element will rise above VvcL (distribution 612). Since only upper page programming of neighboring storage elements will affect the apparent Vth of a given storage element, the depicted process reduces the floating gate-to-floating gate coupling effect. An example of alternating state coding moves from distribution 606 to state C when upper page data is zero, and to B-state when upper page data is one. After the second programming step is performed for WLn, the first programming step may be performed for WLn + 2 as indicated by step “4” in FIG. 7B, and as indicated as step “5” in FIG. 7B. A second programming step can be performed for WLn + 1.

6C provides a transition from distribution 602 to distribution 604 for the A-state, from distribution 608 to distribution 610 for the B-state, and from distribution 612 for the C-state. To provide a transition to distribution 614, programming the upper page with high verify levels Vva, Vvb, Vvc is shown. For example, this may correspond to step “6” in FIG. 7B.

Although this three-step programming example provides four data states and two data pages, this concept can be applied to other implementations having more or fewer states than four states and having more or fewer pages than two pages. have. For example, memory devices with 8 or 16 states per storage element are currently planned or in production.

In general, the programming speed may be adjusted for any of the programming passes of FIGS. 6A-6C. For example, in the second programming pass of FIG. 6B, we can set Vva-speed <VvaL as shown in FIG. 5B. Similarly, you can set Vva-speed <VvbL and Vvc-speed <VvcL. In this case, in the second programming pass, the A-state storage elements are programmed at high speed when Vth ≦ Vva-speed, and at low speed when Vva-speed <Vth ≦ VvaL. Likewise, B-state storage elements are programmed at high speed when Vth < Vvb-speed, and at slow speed when Vvb-speed < Vth &lt; Likewise, C-state storage elements are programmed at high speed when Vth &lt; Vvb-speed, and at slow speed when Vvc-speed &lt; Vth &lt;

In the example of the second programming step of FIG. 6C, VvaL <Vva_speed <Vva may be set as shown in FIG. 5C. Similarly, you can set VvaL <Vvb_speed <Vvb and VvcL <Vvc_speed <Vvc. In this case, in the third programming step, the A-state storage elements are programmed at high speed when VvaL <Vth ≦ Vva_speed, and Vva_speed <Vth ≦ Vva? It is programmed at a slow speed. Likewise, B-state storage elements are programmed at high speed when VvbL <Vth ≦ Vvb-speed, and at low speed when Vvb-speed <Vth ≦ Vvb. Likewise, C-state storage elements are programmed at high speed when VvcL <Vth ≦ Vvc_speed and at low speed when Vva-speed <Vth ≦ Vvc.

The previous examples for the second and third programming pass may be used alone or in combination.

FIG. 6D shows a second programming pass of a two-step programming operation, referred to as a “two-pass write” programming technique, where FIG. 6A shows the first programming pass, and where up to two programming speeds are QPW programming. Can be used as an option. In this further alternative example, verify levels Vva-speed, Vvb-speed, and Vvc-speed are used to trigger slow programming speed, as discussed in FIGS. 5A-5C. Specifically, A-state storage elements will be programmed at high speeds when their Vth &lt; Vva_speed and will be programmed at slow speeds when their Vva &gt; Vth > Vva-speed. Vth> Vva triggers a programming lockout condition. Are the B-state storage elements whose Vth≤Vvb_speed? They will be programmed at high speed and will be programmed at slow speed when their Vvb> Vth> Vvb-spped. Vth> Vvb triggers a programming lockout condition. C-state storage elements will be programmed at high speeds when their Vth ≤ Vvc-speed, and programmed at slow speeds when their Vvc> Vth> Vvc-speed. Vth <Vvc triggers a programming lockout condition.

7A illustrates a two-pass programming operation for a set of storage elements, in word line order back-to-back. The illustrated components may be a much larger subset of the storage elements, word lines and bit lines. In one possible programming operation, the storage elements (shown in square) on WLn are programmed in the first programming pass, as indicated by the circled " 1 ". Next ("2"), the storage elements on WLn + 1 are programmed in the first programming pass for that word line. In this example, when a word line is selected for programming, verify operations occur after each program pulse. During the verify operations for the selected word line, verify voltages are applied to the unselected word lines to turn on (conduct) the unselected storage elements so that a sense operation, such as a verify operation, occurs for the selected word line. Can be. Next ("3"), the storage elements on WLn are programmed in the second programming pass. Next (“4”), the storage elements on WLn + 2 are programmed in the first programming pass for that word line. Next ("5"), the storage elements on WLn + 1 are programmed to their respective final states in the second programming pass.

By programming word lines in a front-to-back fashion in multiple programming passes, the capacitive coupling-caused interference effect, which tends to increase and widen their Vth distributions, is reduced. In contrast, in single-pass programming, each word line is fully programmed before moving to the next word line.

The first and second programming passes may use any of the programming techniques discussed herein. 7B shows a three-pass programming operation for a set of storage elements, in word line order back-to-back. The initial programming pass of the lower page is performed before the first and second programming passes of the upper page. The first programming pass programs the lower data page, the second programming step programs the upper data page in the first programming pass, and the third programming pass completes the programming of the upper data page in the second programming pass. . At "1", the first programming pass is performed for WLn, at "2" the second programming pass is performed for WLn + 1, at "3", the second programming pass is performed for WLn, and "4" A first programming pass is performed for WLn + 2, a second programming pass is performed for WLn + 1 at "5", a third programming pass is performed for WLn at "6", and "7" A first programming pass is performed for WLn + 3, a second programming pass is performed for WLn + 2 at "8", a third programming pass is performed for WLn + 1 at "9", and so on.

In one possible technique, the first programming pass uses a verify level VvLM as shown in FIG. 6A and the second programming pass uses a subset of verify levels (VvaL, VvbL, VvcL) as shown in FIG. 6B. And the third programming pass uses a higher set of verify levels (Vva, Vvb, Vvc) as shown in FIG. 6C. The difference between the lower set of verify levels in the second programming pass and the higher set of verify levels in the third programming pass can be optimized for silicon to achieve the most compact set of Vth distributions.

The first, second and third programming passes may use any of the programming techniques discussed herein.

8 shows the relationship between the highest Vpgm needed to program the storage element and the bit line voltage of the storage element. The x-axis shows the increasing bit line voltage Vbl and the y-axis shows the highest Vpgm voltage required to complete the programming of the storage element.

As Vbl increases, the maximum required to complete the programming of the storage element (Vpgm also increases. In general, the degree of slow programming of the storage element is proportional to the product of Vbl and the constant k, where k is the slope of the line shown. A 1V increase in Vbl (eg, a bit line step size of ΔVbl = 1V) is an offset, requiring an increase greater than 1V of Vpgm (eg, a program pulse step size of ΔVpgm = 1V). Therefore, the constant is usually greater than 1. Therefore, increasing Vbl is a powerful tool for controlling the programming speed and narrowing the width of the Vth distribution, but Vbl is mainly limited by the Vsgd (drain-side select gate) margin window. (Vbl cannot be made too high.) When Vbl is higher, before Vsgd is required to turn on the drain-side select gate to program the storage elements. The pressure is also higher, but the higher Vsgd value carries the risk of boost potential leakage from the channel of forbidden storage elements that can cause program disturb.

The programming speed of the storage element depends on the electric field across its tunnel oxide, which is proportional to the difference between the voltage of the floating gate and the voltage of the channel in the substrate under the floating gate. Usually, the control gate voltage Vpgm is stepped up stepwise, and Vbl is fixed at 0V. To slow programming (dense the Vth distribution), a smaller Vpgm step size can be used. However, this increases the number of program pulses and verify operations, thereby increasing the overall programming time. Instead of changing the Vpgm step size, one can increase Vbl in lockstep with steps of Vpgm pulses to reduce the effective Vpgm step size (ΔVpgm-effective). ΔVpgm-effective = ΔVpgm- (k × ΔVbl), where k> 1 and ΔVpgm-effective <ΔVpgm. In general, the k value may be about 1.4. The larger ΔVbl results in a smaller ΔVpgm-effective. The advantage of this technique is that Vbl can be stepped up for different subsets of storage elements at different times, where each subset has a different target data state. Thus, different programming speeds can be achieved for a set of storage elements belonging to different target data states. On the other hand, if the Vpgm step size is reduced, this affects the programming speed of the entire programming storage elements. Compared to using an equivalent smaller Vpgm step size, stepping up Vbl at a time for a particular target data state reduces the total number of program pulses required to complete programming, The number of verify operations can remain the same, thus improving performance by reducing the overall programming time.

The lockstep increase of Vbl is, for example, that Vbl can be steped up with each program pulse for a given subset of storage elements having a common target data state and for which programming has not yet been locked out. Indicates. Vbl of the storage element whose programming is locked out is set to Vbl-lockout.

9A illustrates a programming technique in which the bit line voltage is stepped up. The programming pass begins at step 900 for storage elements of all target data states. Steps 902-912 are performed separately and partially simultaneously for storage elements of all target data states. Step 902 includes performing one or more program-verify operations without bit line step up during programming. In step 904, the first trigger condition is met. This may be based, for example, on the Vpgm level, a predetermined number of program pulses, or a bit scan, as discussed further below. The first trigger condition represents a condition for starting a bit line step up loop for a subset of storage elements having a common target data state. Step 906 includes performing one or more program-verify operations using bit line step up during programming. In step 908, the second trigger condition is satisfied. This may be based on, for example, the Vpgm level, a predetermined number of program pulses or a bit scan, as discussed below. The second trigger condition indicates a condition for stopping the bit line step up loop for a subset of storage elements having a common target data state. Step 910 includes performing one or more program-verify operations without bit line step up during programming. In this case, the bit line can be fixed at the maximum allowable level lower than the lockout level. Programming-verify operations for the storage elements of the associated target data state are terminated at step 912. In practice, storage elements that have reached the verify level are locked out from further programming so that other storage elements with a particular target data state may continue to be programmed, while some storage elements with a particular target data state may be locked out from programming. have. In some cases, step 910 is not performed as when all storage elements of the associated target data state are locked out in step 906. The programming technique of FIG. 9A is discussed in more detail below.

9B illustrates data states undergoing verify operations as a function of the number of program pulses, as an example of the programming technique of FIG. 9A. During programming, all storage elements are programmed together, but since the A-state verify level is lower than the B-state verify level and the B-state verify level is lower than the C-state verify level, the storage elements belonging to the lower target states are It reaches its target level earlier than for the storage elements in the state. Thus, to save programming time, the verify operation for the higher target state does not have to start from the first program pulse itself. In general, B-state verify operations may be skipped for some initial program pulses and C-state verify operations may be omitted for subsequent program pulses.

For example, when Vbl is not stepped up as described herein, but fixed at 0V during programming, and ΔVpgm = ΔVpgm-effective = 0.3V, an order 950 occurs. First, A-state storage elements are verified, then A-state storage elements and B-state storage elements are verified, then B-state storage elements and C-state storage elements are verified, and finally C- State storage elements are verified. This order consumes most of the programming time of the three orders 950, 960, 970 provided. In this particular example, it should be noted that, by chance, there is no set of programming pulses for which the A-, B-, and C- state storage elements are verified. This may not be the case if there are some changes in other Vpgm step size or other device parameters. That is, there may be one or more programming pulses in which A-, B-, and C- state storage elements are verified, as shown in sequences 960 and 970.

During programming, an order 960 occurs when Vbl is stepped up as described herein, for example, ΔVbl such that ΔVpgm = 0.4V and ΔVpgm-effective = 0.3V. Is selected. First, the A-state storage elements are verified, then the A- and B-state storage elements are verified, then the B- and C-state storage elements are verified, and finally the C-state storage elements are verified. This ordering reduces programming time compared to ordering 950. Compared with Vpgm = ΔVpgm-effective = 0.3V throughout the sequence 950, the storage elements are stored in sequence 960 since ΔVpgm = ΔVpgm-effective = 0.4V both before and after the bit line step up. Program faster in sequence 960 than in 950. However, since ΔVpgm-effective = 0.3V during programming of storage elements having a common target data state in both orders 950 and 960, the same Vth distribution widths can be achieved in both orders.

During programming, an order 970 occurs when Vbl is stepped up as described herein for all target data states except the highest target data state (eg, the C-state), where ΔVpgm = 0.4V, and DELTA Vbl is selected to be DELTA Vpgm-effective = 0.3V. First, A-state storage elements are verified, then A- and B- state storage elements are verified, then A-, B-, and C-state storage elements are verified, and then B- and C-state storage. The devices are verified, and finally the C-state storage elements are verified. Since ΔVpgm = ΔVpgm-effective = 0.4V for the C-state storage elements during the programming of the storage elements, this order further reduces programming time compared to the sequence 960, thus programming time of the C-state storage elements. Is reduced. In general, when more verify operations are performed for a given program pulse, the number of program pulses and associated setup time is shortened, thereby reducing programming time.

As mentioned, usually a wider Vth distribution can be tolerated for the best target data state, so programming time can be further shortened by not stepping up Vbl for the best target data state. Specifically, the upper tail of the Vth distribution will be higher when Vbl is not stepped up. However, this is not very important in terms of the Vth window defined as the gap between the lowest state upper tail and the highest state lower tail. Another advantage of not stepping up Vbl for the highest target data state is that the highest Vpgm needed to program the highest state storage elements is lower than when Vbl is stepped up. Higher Vpgm can cause increased program disturb for E-state storage elements. Thus, disabling the highest state bit line step up may be desirable in terms of program disturb.

Note that this example relates to a four-state memory device but that the concept can be extended to additional states, such as the 8 or 16 state.

FIG. 10 illustrates program-verify operations as a function of program pulse number for sequence 960 of FIG. 9B. Generally, program operation can involve applying a pulse train to a selected word line, where the pulse train includes one or more verify pulses after the program pulses. Each combination of the program pulse and the subsequent one or more verify pulses form a program-verify operation or iteration. Note that the program pulse may have any number of different waveform shapes. Although sinusoidal waves are shown, other shapes are possible, such as multilevel shapes or ramp shapes. Pulse trains generally include program pulses that increase stepwise in amplitude, using a fixed step size, but varying step sizes may also be used. In each programming pass of a multi-pass programming operation, a new pulse train can be applied starting at the initial Vpgm level and ending at the final Vpgm level below the maximum allowable Vpgm level. The initial Vpgm levels can be the same or different in different programming passes. The final Vpgm levels can also be the same or different in different programming passes. The step size may be the same or different in different programming passes. In some cases, a smaller step size is used in the final programming pass to reduce the Vth distribution width.

The pulse train 1000 is a series of program pulses 1005, 1010, 1015, 1020, 1025, 1030, 1035, 1040, 1045, 1050, 1055 applied to an associated set of nonvolatile storage elements and a selected word line for programming. 1060, 1065, 1070, 1075. Based on the target data states being verified, for example, one, two or three verify levels are provided after each program pulse. 0V can be applied to WLn between the program pulse and the verify pulse. For example, an A-state verify pulse (eg, waveform 1006) may be applied after each of the first, second and third program pulses 1005, 1010, 1015. A- and B-state verify pulses (eg, waveform 1021) may be applied next to each of the fourth, fifth, and sixth program pulses 1020, 1025, and 1030. A-, B- and C-state verify pulses (eg, waveform 1036) may be applied after each of the seventh and eighth program pulses 1035, 1040. The B- and C-state verify pulses (eg, waveform 1046) may be applied next to each of the ninth, tenth, and eleventh program pulses 1045, 1050, and 1055. Finally, a C-state verify pulse (eg, waveform 1061) may be applied next to each of the twelfth, thirteenth, fourteenth and fifteenth program pulses 1060, 1065, 1070 and 1075. .

11A shows the step up of the bit line voltage as a function of the number of program pulses for different data states, where a common step size is used for storage elements belonging to all data states. Waveforms 1100, 1102, and 1104 represent bit line voltages for the A-, B-, and C-states, respectively. In this example, Vbl is stepped up to V1, V2, V3, V4, V5 and Vbl-max (maximum permissible level) using the fixed step size DELTA Vbl. Vbl-lockout indicates the lockout bit line voltage, which is higher than Vbl-max. In some cases, all storage elements in a particular target state can be locked out before Vbl-max is reached and thus Vbl-max is a safeguard that can or may not be reached.

For storage elements in each target data state, the start of the bit line step up and / or the end of the bit line step up may be set based on different trigger conditions. In one non-adaptive technique, a fixed Vpgm pulse number is set for the start and end of the bit line step up control loop for each target data state. For example, the ROM fuse parameters of a memory device are BL-lamp-start-A = 2, BL-lamp-end-A = 7, BL-lamp-start-B = 5, BL-lamp-end-B = 10 BL-lamp-start-C = 8 and BL-lamp-end = 13. Each data state has its own bit line step up control loop. In this example, since the required Vth distribution width is the same for each data state, the number of program pulses in each bit line step up control loop is the same. If a wider Vth distribution width is acceptable, the bit line step up control loop may be smaller, with fewer program pulses.

The number of Vpgm pulses used to start and end the bit line step up may be selected such that relatively few data state storage elements reach the verification level and lock out before or after the bit line step up control loop for that data state. During the bit line step up control loop, the majority of storage elements will reach the verify level and lock out. Enabling a small number of storage elements to reach the verify level and lock out before or after the bit line step up control loop does not significantly widen the Vth distribution. However, this shortens the time that ΔVpgm-effective becomes low, and thus the overall programming time is not unnecessarily extended.

11B shows a trigger condition for initiating a bit line step up loop for A-state storage elements. In an exemplary programming pass, A-state storage elements are programmed using VvaL starting from E-state distribution 1110. After one or more program pulses, distribution 1112 represents A-state storage elements. Portion 1114 of distribution 1112 represents A-state storage elements where Vth> VvaL.

11C shows a trigger condition for stopping the bit line step up loop for the A-state storage elements. After one or more additional program pulses, distribution 1120 represents the A-state storage elements. Portion 1116 of distribution 1120 represents A-state storage elements where Vth <VvaL. The Vth distribution of the storage elements of the different target states that can be programmed simultaneously is not shown.

As an alternative to the non-adaptive technique described above, an adaptive technique may be used to set the start and / or end of the bit line step up loop. This allows the start and / or end time to be different for different sets of storage elements within the same memory device, such as on different word lines. Furthermore, for example, based on a change in performance over time, as the program-erase cycle accumulates, or based on different environmental conditions such as temperature changes, the start and / or end times for the same set of storage elements may be reduced. Can vary.

For example, instead of using a fixed program pulse number, the bit line step up loop can be started and / or terminated based on the minimum number of storage elements above or below a particular verify level. For example, the storage elements represented by region 1114 may be detected by a bit scan procedure in which the sense amplifier of each bit line is read to determine if Vth> VvaL for the associated storage element. When it is detected that the minimum number of bits, eg, the A-state storage elements, has exceeded VvaL, the bit line step up loop for the A-state may begin. Similarly, the bit line step up loop may stop when the number of A-state bits whose Vth is less than VvaL is less than a certain number (or when the number of A-state bits where Vth> VvaL exceeds a certain number). The specific number of bits during bit-scan, in which a bit line step up start or stop decision is made, can be controlled by other ROM fuse parameters. Similar decisions can be made for other states by performing bit-scan at their respective verify levels.

Forces a maximum allowed Vbl (e.g., Vbl-max in FIG. 11A) to prevent Vbl from stepping up to an excessively high level when other trigger conditions to stop the bit line step up have not yet been met. It is also possible.

In another technique, the bit line step up loop may be started for each data state after passing through the bit-scan and after completion of a certain number of additional program pulses. Similarly, the bit line step up may end for each data state after the bit-scan pass and after completion of a certain number of additional program pulses.

In another technique, the bit line step up loop for one data state may begin after passing a bit-scan for another lower data state and after completion of a certain number of additional program pulses. For example, a bit line step up loop for B-state storage elements may pass through a bit-scan at VvaL for A-state storage elements, and then (such as three program pulses according to FIG. 11A). ) Can be started after completion of a certain number of additional program pulses. Similar methodology can be used to stop the bit line step up. Using such a method, the start and stop of bit line step up can be made adaptive for all data states by performing bit-scan operations only for the lowest state.

Any combination of the above methods may also be used to determine when to start and / or end a bit line step up loop for any particular target data state.

In the examples provided, a four-state, two-bit implementation is shown per storage element memory device. However, the present concepts may be used for eight or sixteen state devices. However, it may be necessary to generate additional bit line voltages simultaneously.

FIG. 12A shows the programming rate according to the number of program pulses for A-state storage elements, consistent with FIG. 11A. As mentioned, in terms of the Vth change (ΔVth / pulse) of the storage element per program pulse, the programming speed or rate is a function of Vbl. If no bit line bias is applied (Vbl = 0V), then Vth / pulse = R2, i.e., a higher rate. If a constant bit line step up is applied at the same lockstep as Vpgm step up, then DELTA Vth / pulse = R1 <R2 (where R1 is the lower rate). In the example of FIG. 11A, the bit lines belonging to the A-state storage elements start stepping up at the second program pulse, so a transition from R2 to R1 occurs for the A-state storage elements at the second program pulse. do. Similarly, the bit line step up for the A-state storage elements is stopped at the eighth program pulse (the final step up is at the seventh program pulse); Thus, a transition from R1 to R2 occurs for the A-state storage elements at the eighth program pulse. In practice, ΔVth / pulse may gradually transition for one or more program pulses rather than show the step change shown for brevity. At the 9th programming pulse, the A-state storage elements are locked out and thus the programming speed drops to zero.

FIG. 12B shows the programming rate according to the number of program pulses for B-state storage elements, consistent with FIG. 11A. In the example of FIG. 11A, for the B-state storage elements, a transition from R2 to R1 occurs at the fifth program pulse, followed by a transition from R2 to R1 at the eleventh program pulse. At the 12th program pulse, the B-state storage elements are locked out, so the programming speed drops to zero.

FIG. 12C shows the programming rate according to the number of program pulses for the C-state storage elements, consistent with FIG. 11A. In the example of FIG. 11A, for the C-state storage elements, a transition from R2 to R1 occurs at the eighth program pulse, followed by a transition from R2 to R1 at the 14th program pulse. After the fifteenth program pulse, programming ends and thus the program rate for the C-state storage elements drops to zero.

Figure 13 shows the step up of the bit line voltage according to the number of program pulses for different data states, where for all data states a smaller step size, then a larger step size, and then a smaller step size Used. In the example of FIG. 11A, Vbl was stepped up using a fixed step size (ie at a fixed rate). In this technique, different bit line step up rates are used. It may be useful to use the first small bit line step up rate and then use the second larger bit line step up rate and then the third smaller bit line step up rate. The third bit line step up rate may be less than the second bit line step up rate and may be equal to the first bit line step up rate. This technique causes the slowest programming when most of the storage elements are reaching the target verify level and lockout conditions, depending on the Gaussian distribution. The original programmed Vth distribution for storage elements on a given word line is generally a Gaussian distribution in nature, so that most of the Vth of the storage elements occur near the center of the distribution while Vth of fewer cells are at the bottom of the Gaussian distribution. Or in the upper tails.

Thus, for a given target data state, most of the storage elements will be locked out close to the same number of program pulses, at the peak of the Gaussian distribution, and therefore now by using the highest bit line step up rate to make the programming as slow as possible A gain-to-cost ratio can be achieved. The advantage is to narrow the Vth distribution and the cost is an increase in programming time. Storage elements in the lower and upper tails of the Gaussian distribution will lock out at certain program pulse numbers where most of the storage elements are far from the program pulse to be locked out. In this case, the best gain-to-cost ratio can be achieved by a low (but nonzero) bit line step up rate during those particular program pulses. Storage elements at the very low and very high tails of the Gaussian distribution will lock out at different program pulse numbers farther than the program pulse to which most of the storage elements will be locked. In this case, the best gain-to-cost ratio can be achieved by not performing bit line step up during those other program pulses.

For example, waveforms 1300, 1302, and 1304 represent Vbl for A-, B-, and C-state storage elements, respectively. Each waveform includes bit line levels V1 ', V2', V3 ', V4', V5 'and Vbl-max. When Vbl is set to V1 'and V2', the step up rate or step size is relatively small. Likewise, the step up rate or step size is also relatively (and optionally, equally) small when Vbl is set to V5 'and Vbl-max. The step up rate or step size is relatively large when Vbl is set to V3 'and V4'.

Figure 14 shows the step up of the bit line voltage according to the number of program pulses for different data states, where a larger step size is used for the lower data states, and a smaller step for the highest data state. Size is used. This example is similar to that of FIG. 11A except that a smaller Vbl step size is used for the highest state (C-state in this example). In this case, Vbl is stepped up using the step size associated with each target data state, where each different step size is associated with at least two different respective target data states of the set of possible target data states. do. For example, one Vbl step up rate may be used for A- and B-state storage elements and another, lower Vbl step up rate may be used for C-state storage elements. The use of smaller Vbl step up rates results in faster programming at the expense of a wider Vth distribution.

Waveforms 1400, 1402, and 1404 represent Vbl for A-, B-, and C-state storage elements, respectively. Here, for the C-state, the Vbl levels of V1, V2, V3, V4, and V5 in waveform 1404 may be the same as those of FIG. 11A. In waveforms 1400 and 1402, Vbl levels of V1 ", V2", V3 ", and V4" are used for A- and B-states, respectively. As mentioned, the absence of bit line step up results in a wider Vth distribution for the highest state, which is generally an acceptable tradeoff to shorten programming time. On the other hand, a larger Vbl step up rate results in a denser Vth distribution but a longer programming time. This example uses between not using the bit line step up for the best state and using a larger bit line step up for the lower states (eg, A-, B-, and C-states). Provides a compromise of This results in a balance in that a somewhat narrower Vth distribution is provided for the best state compared to the case where no bit line step up is used. Programming time is longer if no Vbl step up is used for the best state, but shorter programming time if a larger Vbl step up is used for the best state.

Figure 15 shows the step up of the bit line voltage according to the number of program pulses for different data states, where a common step size is used for all data states, and additional bit line voltages are added based on the Vth level. do. In some programming techniques, an additional bit line voltage [Delta] is used to slow the programming, generally for all states except the highest state. This additional bit line voltage has not yet been locked out from programming and can be used for storage elements whose Vth is between the first verify level and the second verify level of each target data state. For example, referring to FIG. 4, for example, the first and second verify levels may be VvaL and Vva for the A-state, respectively, VvbL and Vvb for the B-state, and for the C-state, respectively. It may be VvcL and Vvc, respectively. In one possible implementation, the bit line step up starts at one program pulse and adds an additional bit line voltage starting at another program pulse. Similarly, the bit line step up may stop at one program pulse, while the additional bit line voltage stops at another program pulse. Bit line step up may be applied simultaneously to a subset of storage elements having a common target data state, while additional bit line voltages are applied to the individual storage elements via the bit line, regardless of the programming progress of the subset. . Applying an additional bit line voltage is accomplished by increasing Vbl by an additional fixed amount beyond the current step up level. This technique can increase the number of bit line voltages required at a given time.

For example, for A-state storage elements, waveforms 1500 and 1502 show bit line step up levels, respectively, with or without additional bit line voltages added. Note that additional bit line voltage added may also be applied before or after the bit line step up. For the B-state storage elements, waveforms 1504 and 1506 show bit line step up levels with or without additional bit line voltages, respectively. For the C-state storage elements, waveforms 1508 and 1510 show bit line step up levels with or without additional bit line voltages, respectively. Vbl-max-new represents a new, higher Vbl that is acceptable. Alternatively, Vbl-max may be forced to cause the bit line step up to terminate early to prevent exceeding Vbl-max. That is, the maximum allowable Vbl can be forced for the sum of the bit line step up level and the additional bit line voltage.

In one embodiment, a method of programming a set of nonvolatile storage elements includes applying a set of program pulses to a set of nonvolatile storage elements, wherein each nonvolatile storage element in the set of nonvolatile storage elements is each one of: a. Associated with a bit line of, the set of nonvolatile storage elements includes different subsets of nonvolatile storage elements. Each subset includes one subset of non-volatile storage elements programmed to one verify level of each target data state, and each verify level Vva of each target data state of the plurality of target data states. , Vvb, Vvc). The method further includes determining when the first trigger condition is satisfied for a subset of nonvolatile storage elements during the set of program pulses. The method is characterized in that when the first trigger condition is met, the voltage of each bit line of one subset of non-volatile storage elements that has not yet been locked out from programming is obtained from each of the plurality of consecutive program pulses of the set of program pulses. Step up, at the same rate as the program pulse.

In another embodiment, a corresponding nonvolatile storage system includes a set of nonvolatile storage elements, wherein the set of nonvolatile storage elements includes different subsets of nonvolatile storage elements, and each subset includes: One subset of non-volatile storage elements programmed to one respective verify level of each target data state is programmed to each verify level of each target data state of the plurality of target data states. Each bit line is associated with a respective nonvolatile storage element. At least one control circuit (a) applies a set of program pulses to a set of nonvolatile storage elements, and (b) a first trigger condition is satisfied for a subset of nonvolatile storage elements during the set of program pulses And (c) when the first trigger condition is met, the voltage of each bit line of one subset of non-volatile storage elements not yet locked out from programming, the plurality of consecutive of the set of program pulses. Step up in lockstep with each program pulse of the program pulses.

In another embodiment, the nonvolatile storage system includes means for applying a set of program pulses to a set of nonvolatile storage elements, wherein each nonvolatile storage element in the set of nonvolatile storage elements is a respective bit line. In relation to, the set of nonvolatile storage elements includes different subsets of nonvolatile storage elements. Each subset includes one subset of non-volatile storage elements programmed to one verify level of each target data state, each verify level of each target data state of the plurality of target data states. It is programmed as (Vva, Vvb, Vvc). The nonvolatile storage system further includes means for determining when the first trigger condition is satisfied for a subset of nonvolatile storage elements during the set of program pulses. The nonvolatile storage system is configured to determine the voltage of each of the bit lines of one subset of nonvolatile storage elements that have not yet been locked out from programming when the first trigger condition is met, the plurality of consecutive program pulses of the set of program pulses. Means for steping up at the same rate as each program pulse of the two.

In another embodiment, a method of programming a set of nonvolatile storage elements includes applying a set of program pulses to a set of nonvolatile storage elements, wherein each nonvolatile storage element in the set of nonvolatile storage elements is each: Associated with a bit line of N, wherein the set of non-volatile storage elements comprises different subsets of non-volatile storage elements, and each subset is non-programmed at one respective verify level of one respective target data state. Programmed to each verify level of each target data state of the plurality of target data states, including one subset of volatile storage elements. The method also steps the voltage of each bit line of one subset of non-volatile storage elements that has not yet been locked out from programming, at a rate equal to each program pulse of the plurality of consecutive program pulses of the set of program pulses. Up, determining when a trigger condition is met for a subset of non-volatile storage elements during the set of program pulses, and when the trigger condition is met, each of the one or more additional program pulses of the set of program pulses. Fixing the voltage with a program pulse of.

In another embodiment, a corresponding nonvolatile storage system includes a set of nonvolatile storage elements. The set of nonvolatile storage elements includes different subsets of nonvolatile storage elements, where each subset is a subset of a nonvolatile storage source that is programmed to one respective verify level of one respective target data state. A program is programmed to each verify level of each target data state of the plurality of target data states, including the set. Each bit line is associated with a respective nonvolatile storage element. At least one control circuit is configured to (a) apply a set of program pulses to a set of nonvolatile storage elements, and (b) apply the voltage of each bit line of one subset of nonvolatile storage elements that has not yet been locked out from programming. Step up at the same rate as each program pulse of the plurality of consecutive program pulses of the set of program pulses, and (c) when the trigger condition is satisfied for a subset of non-volatile storage elements during the set of program pulses. And (d) fixing the voltage with each program pulse of one or more additional program pulses of the set of program pulses when the trigger condition is met.

Corresponding methods, systems, and computer or processor readable storage devices for performing the methods provided herein are provided.

The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above. The disclosed embodiments are chosen so that they best explain the principles of the invention, so that those skilled in the art can best use the invention in various embodiments and with various modifications suitable for the particular application contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims (15)

A method of programming a set of nonvolatile storage elements,
Applying a set of program pulses 1005, 1010,... To a set of nonvolatile storage elements, wherein each nonvolatile storage element in the set of nonvolatile storage elements has its own bit line BL0. , BL1, ...), wherein the set of nonvolatile storage elements comprises different subsets of nonvolatile storage elements, each subset having one respective verify level of one respective target data state. Programmed to each verify level (Vva, Vvb, Vvc) of each target data state of the plurality of target data states (A, B, C), including one subset of non-volatile storage elements programmed into;
Determining when a first trigger condition is satisfied for a subset of the nonvolatile storage elements during the set of program pulses; And
When the first trigger condition is met, the voltage Vbl of each bit line of one subset of non-volatile reservoirs that has not yet been locked out from programming is determined by the plurality of consecutive program pulses of the set of program pulses. And steping up in lockstep with each program pulse. The method according to claim 1,
The set of nonvolatile storage elements is in communication with a common word line (WLn); And
And said set of program pulses are applied to said set of nonvolatile storage elements via said common word line. 3. The method according to claim 1 or 2,
And wherein said first trigger condition is satisfied based upon reaching a predetermined number of program pulses. 3. The method according to claim 1 or 2,
And the first trigger condition is satisfied based on when the threshold voltages of at least the minimum number of the nonvolatile storage elements in the one subset are verified to have reached each of the one verification level. How to program a set of things. 5. The method of claim 4,
The first trigger condition is satisfied when the threshold voltages of the at least minimum number of nonvolatile storage elements in the subset are verified to have reached each one verify level, and then the set of nonvolatile storage elements. A method of programming a set of nonvolatile storage elements, characterized in that a fixed number of program pulses are applied. The method according to any one of claims 1 to 5,
And fixing the voltage during each program pulse of the set of program pulses that precede the first trigger condition before the first trigger condition is satisfied. A method of programming a set of storage elements. The method according to any one of claims 1 to 6,
For a subset of non-volatile storage elements that have not yet been locked out from programming, wherein the threshold voltage is between the first verify level and the second verify level of each of the target data states, the voltage is added to a fixed amount ( additional fixed amount) further comprising the step of programming the set of non-volatile storage elements. The method according to any one of claims 1 to 7, wherein
The voltage is steped up using a step size associated with each one of the target data states, each different step size being associated with at least two different respective target data states of the plurality of target data states. Programming a set of non-volatile storage elements. The compound according to any one of claims 1 to 8, wherein
Wherein said voltage is stepped up at a first rate (R1) and thereafter at a second higher rate (R2) during said plurality of successive program pulses. How to program it. The method of claim 8,
The voltage is stepped up during the plurality of consecutive program pulses, subsequently at a third rate lower than the second rate. The method according to any one of claims 1 to 10,
Determining when a second trigger condition is satisfied for a subset of non-volatile storage elements during the set of program pulses; And
During each program pulse of the one or more additional program pulses of the set of program pulses, when the second trigger condition is met, further comprising locking the voltage below a lockout level (Vbl-lockout). Programming a set of non-volatile storage elements. 12. The device of claim 1, wherein different subsets of the nonvolatile storage elements are programmed to another respective verify level of another target data state that is higher than the respective target data state. Another subset of non-volatile storage elements,
Determining when another trigger condition is satisfied for another subset of the nonvolatile storage elements during the set of program pulses; And
When the another trigger condition is met, the voltage of each bit line of another subset of non-volatile storage elements that has not yet been locked out from programming is determined by each of the another plurality of consecutive program pulses of the set of program pulses. And steping up at a lock rate equal to a program pulse of wherein the another trigger condition is satisfied after the first trigger condition is satisfied. Way. 13. The method of claim 12,
The another trigger condition is satisfied based on when the first trigger condition is satisfied, and then applying a fixed number of program pulses to the set of nonvolatile storage elements is performed. How to program a set. A non-volatile storage system,
The set of nonvolatile storage elements 155 and the set of nonvolatile storage elements comprise different subsets of nonvolatile storage elements, each subset being one respective verify level of one respective target data state. Programmed to each verify level (Vva, Vvb, Vvc) of each target data state of the plurality of target data states (A, B, C), including one subset of non-volatile storage elements programmed into
Each bit line BL0, BL1, ... associated with each nonvolatile storage element; And
At least one control circuit, (a) applying a set of program pulses 1005, 1010, ... to a set of nonvolatile storage elements, and (b) the program pulse Determine when a first trigger condition is met for the subset of non-volatile storage elements during the set of values, and (c) when the first trigger condition is met, one subset that has not yet been locked out of programming And step-up the voltage Vbl of each of the bit lines of the non-volatile storage elements of the non-volatile storage elements at the same rate as each program pulse of the plurality of consecutive program pulses of the set of program pulses. 15. The method of claim 14,
And the first trigger condition is satisfied based on when the threshold voltages of at least the minimum number of the nonvolatile storage elements in the one subset are verified to have reached each of the respective verify levels.

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