CN108962313A - Memory operating method and storage operation device - Google Patents
Memory operating method and storage operation device Download PDFInfo
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- CN108962313A CN108962313A CN201710366000.7A CN201710366000A CN108962313A CN 108962313 A CN108962313 A CN 108962313A CN 201710366000 A CN201710366000 A CN 201710366000A CN 108962313 A CN108962313 A CN 108962313A
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- value
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- step cycle
- control voltage
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
Abstract
A kind of memory operating method and storage operation device.Memory operating method includes the following steps.It executes one first step cycle and executes one second step cycle.In the first step cycle, the one first control voltage for being applied to one first control line increases to one first end value by one first initial value, and the one second control voltage for being applied to one second control line is fixed on one second initial value.First end value is higher than the first initial value.In the second step cycle, the first control voltage for being applied to the first control line is fixed on a fixed value, and the second control voltage for being applied to second control line increases to one second end value by intermediate value in one.Second end value is higher than the second initial value.
Description
Technical field
The present invention relates to a kind of operating method and operating devices, and more particularly to a kind of memory operating method and storage
Device operating device.
Background technique
With the development of memory technology, various memories are continued to introduce new.Variable resistance type memory
(Resistive Random-Access Memory, ReRAM) and Ovonics unified memory (Phase-Change Memory, PCM)
For nonvolatile memory (non-volatile random-access memories).The running of variable resistance type memory
It is operated by changing the resistance of dielectric solid-state material.The running of Ovonics unified memory is then by changing phase (phase)
Mode operates.In variable resistance type memory and Ovonics unified memory, storage unit needs good write-in control ability
To avoid the problem that (over-writing) excessively is written.However, according to excessive operating procedure, it will influence operation speed
Degree.
Summary of the invention
The present invention is followed about a kind of memory operating method and storage operation device using one first stepping is executed
The mode of ring (first stepping loop) and one second step cycle (second stepping loop), so that operation
Speed is accelerated.
According to an aspect of the invention, it is proposed that a kind of memory operating method.Memory operating method includes the following steps.
It executes one first step cycle and executes one second step cycle.In the first step cycle, it is applied to one first control line
One first control voltage increases to one first end value by one first initial value, and is applied to one second control of one second control line
Voltage processed is fixed on one second initial value.First end value is higher than the first initial value.In the second step cycle, it is applied to first
First control voltage of control line is fixed on a fixed value, and is applied to the second control voltage of second control line by an intermediary
Value increases to one second end value.Second end value is higher than the second initial value.
According to another aspect of the invention, it is proposed that a kind of storage operation device.Storage operation device includes one first
Controller, a second controller and a processor.First controller is applied to one first control of one first control line to control
Voltage processed.Second controller is applied to one second control voltage of the second control line to control.Processor is to execute one
One step cycle (first stepping loop) and one second step cycle (second stepping loop).First
In step cycle, the one first control voltage for being applied to one first control line increases to one first finally by one first initial value
Value, and the one second control voltage for being applied to one second control line is fixed on one second initial value.First end value be higher than this
One initial value.In the second step cycle, the first control voltage for being applied to the first control line is fixed on a fixed value, and applies
In the second control line second control voltage by one in intermediate value increase to one second end value.Second end value is higher than the second starting
Value.
More preferably understand to have to the above-mentioned and other aspect of the present invention, hereafter spy enumerates embodiment, and cooperates institute's attached drawing
Detailed description are as follows for formula:
Detailed description of the invention
Fig. 1 is painted the schematic diagram of storage operation device.
Fig. 2A~2B is painted the flow chart of the memory operating method according to an embodiment.
Fig. 3 is the distribution map of total rifle number.
Fig. 4 is the distribution of impedance figure according to the present embodiment.
Fig. 5 A~5B is painted the flow chart of memory operating method according to another embodiment.
[symbol description]
100: storage operation device
110: the first controllers
120: second controller
130: processor
200: memory
C1, C2, C3, C4, C5, C6, C7: curve
CL1: the first control line
CL2: the second control line
CV1: the first control voltage
CV2: the second control voltage
S211, S212, S221, S222, S223, S224, S225, S231, S232, S233, S234, S235, S531: step
SL21, SL51: the first step cycle
SL22, SL52: the second step cycle
W1: window
Specific embodiment
Fig. 1 is please referred to, the schematic diagram of storage operation device 100 is painted.Storage operation device 100 is to operate one
Memory 200.Storage operation device 100 be, for example, a computer, a processing equipment, a circuit board, a circuit, a chip or
The storage device of storage arrays program code.Memory 200 is, for example, a variable resistance type memory (Resistive
Random-Access Memory, ReRAM) and Ovonics unified memory (Phase-Change Memory, PCM).Memory 200
Including several the first control line CL1 and several second control lines CL2.In one embodiment, each first control line CL1 can be
One bit line (bit line) or source line (source line), and each second control line CL2 can be a wordline.Another
In one embodiment, each first control line CL1 can be a wordline, and each second control line CL2 can be a bit line or one
Source electrode line.Storage operation device 100 includes one first controller 110, a second controller 120 and a processor 130.First
Controller 110 is to control the first control line CL1, and second controller 120 is to control the second control line CL2.
A~2B referring to figure 2. is painted the flow chart of the memory operating method according to an embodiment.Storage operation
Method is to execute the operation sequences such as FORM, SET or RESET.For these operation sequences, it is necessary to improve service speed, with
Meet various applications.In this embodiment, operating method includes two step cycles, e.g. one first step cycle (first
Stepping loop) SL21 and one second step cycle (second stepping loop) SL22.
In the first step cycle SL21, the first control voltage CV1 for being applied to the first control line CL1 is gradually increased, and is applied
The the second control voltage CV2 for being added on the second control line CL2 is then fixed.
In the second step cycle SL22, the first control voltage CV1 for being applied to the first control line CL1 is fixed, and is applied
It is then gradually increased in the second control voltage CV2 of the second control line CL2.
Second step cycle SL22 is implemented in after the first step cycle SL21.When the first step cycle SL21 is completed,
Process enters the second step cycle SL22, without later executing the first step cycle SL21.Just by executing the first step cycle
SL21 and the second step cycle SL22, service speed are effectively improved.
In more detail, memory operating method includes the following steps.In step S211,130 load store of processor
The relevant information of device 200, to define one first initial value of the first control voltage CV1.In step S212, processor 130
The relevant information of load store device 200, to define one second initial value of the second control voltage CV2.First initial value is to write
Entering (formation) electric current can be by the first control line CL1 of memory 200, without will cause excessively write-in (over-writing)
Appropriate value.In general, the first initial value close to but be less than memory 200 dynamic resistance value figure turning point (switch
point).For example, the first initial value is, for example, 2V.Similarly, the second initial value is that write-in (formation) electric current can pass through
Second control line CL2 of memory 200, the appropriate value without will cause excessively write-in (over-writing).In general, second
Initial value close to but be less than memory 200 dynamic resistance value figure turning point.For example, the second initial value is, for example, 2V.
Table 1 is please referred to, in the first step cycle SL21 and the second step cycle SL22, the first control voltage CV1 and the
Two control voltage CV2 are set according to table 1.
Table 1
Then, in step S221, the first control voltage CV1 of the first controller 110 setting and the setting of second controller 120
Second control voltage CV2.
In step S222, according to first control voltage CV1 and second control voltage CV2 to memory 200 carry out FORM,
The operation sequences such as SET, RESET.
Then, in step S223, processor 130 judges whether the operation sequences such as FORM, RESET, SET are completed.If
The operation sequences such as FORM, SET, RESET are completed, then terminate this process；If the operation sequences such as FORM, SET, RESET do not complete,
Then enter step S224.
In step S224, processor 130 judges whether the first control voltage CV1 has reached the first end value.Citing comes
It says, the first end value can be 5V.If the first control voltage CV1 reaches the first end value, S231 is entered step；If the first control
The first end value has not yet been reached in voltage CV1 processed, then enters step S225.
In step S225, the first control voltage CV1 is increased a predetermined value (e.g. 1V).Then, process is back to step
Rapid S221 and step S222, to execute the operation sequence of memory 200 again.First step cycle SL21 is repeatedly performed,
Until the programs such as FORM, SET, RESET be completed or first control voltage CV1 reach the first end value.
In step S231, the first controller 110 fixes the first control voltage CV1 for being applied to the first control line CL1
In fixed value, and second controller 120 increases the second control voltage CV2 for being applied to the second control line CL2.Second control voltage
CV2 increases by middle intermediate value.In this embodiment, fixed value is equal to the first end value.For example, the first end value is
5V, and fixed value is also 5V.Middle intermediate value is higher than the second initial value.Citing also says that the second initial value is 2V, and middle intermediate value is 3V.
In step S232, the first control voltage CVI of the first controller 110 setting and the setting of second controller 120 second
Control voltage CV2.
In step S233, according to the first control voltage CV1 and the second control voltage CV2, memory 200 is carried out
The operation sequences such as FORM, SET, RESET.
Then, in step S234, processor 130 judges whether the operation sequences such as FORM, RESET, SET are completed.If
FORM, SET, RESET are completed, then terminate this process；If FORM, SET, RESET are not yet completed, S235 is entered step.
In step S235, processor 130 judges whether the second control voltage CV2 reaches the second end value.For example,
Second end value can be 5V.If the second control voltage reaches the second end value, terminate this process；If the second control voltage is still
Not up to the second end value is then back to step S231.If process is back to step S231 and step S232, second controller 120
Increase by the second control voltage CV2 again, and according to the second control voltage CV2, operation sequence is executed again to memory 200.
Second step cycle SL22 is repeatedly performed, until the operation sequences such as FORM, SET, RESET are completed or
Two control voltage CV2 reach the second end value.
That is, in the first step cycle SL21, be applied to the first control voltage CV1 of the first control line CL1 by
First initial value increases to the first end value (being greater than the first initial value)；It is applied to the second control voltage of the second control line CL2
CV2 is fixed in the second initial value.In the second step cycle SL22, it is applied to the first control voltage of the first control line CL1
CV1 is fixed on fixed value (being equal to the first end value)；It is applied to the second of the second control line CL2 and controls voltage CV2 therefrom intermediate value
(being higher than the second initial value) increases to the second end value (being higher than middle intermediate value).
Table 2 is please referred to, illustrates an example of FROM program.In this example, memory 200 is by titanium nitride layer
(TiN) variable resistance type memory composed by-tungsten oxide layer (WOx)-titanium nitride layer (TiN), the first control line CL1 are bit line
(or source electrode line), the second control line CL2 are wordline.In the first step cycle SL21, bit-line voltage is gradually increased to 4V by 2V,
And word line voltage is fixed on 2V.In the second step cycle SL22, bit-line voltage is fixed on 4V, and word line voltage is gradually increased by 3V
Add to 4V.In this instance, total rifle number is 5.Compared to traditional FORM program, total rifle number is 9.Therefore, this operation speed
Degree is significantly improved.
Table 2
Table 3 is please referred to, illustrates an example of SET program.In this example, memory 200 is by titanium nitride layer
(TiN) variable resistance type memory composed by-tungsten oxide layer (WOx)-titanium nitride layer (TiN), the first control line CL1 are word
Line, the second control line CL2 are bit line (or source electrode line).In the first step cycle SL21, word line voltage is gradually increased to by 2V
5V, and bit-line voltage is fixed on 2V.In the second step cycle SL22, word line voltage is fixed on 5V, and bit-line voltage by 3V by
It is cumulative to add to 5V.In this instance, total rifle number is 7.Compared to traditional SET program, total rifle number is 16.Therefore, this behaviour
Making speed is significantly improved.
Table 3
Table 4 is please referred to, illustrates an example of RESET program.In this example, memory 200 is by titanium nitride layer
(TiN) variable resistance type memory composed by-tungsten oxide layer (WOx)-titanium nitride layer (TiN), the first control line CL1 are word
Line, the second control line CL2 are bit line (or source electrode line).In the first step cycle SL21, word line voltage is gradually increased to by 2V
5V, and bit-line voltage is fixed on 2V.In the second step cycle SL22, word line voltage is fixed on 5V, and bit-line voltage by 3V by
It is cumulative to add to 5V.In this instance, total rifle number is 7.Compared to traditional RESET program, total rifle number is 16.Therefore, this
Service speed is significantly improved.
Table 4
It referring to figure 3., is the distribution map of total rifle number.Fig. 3 is painted four curves C1, C2, C3, C4.Curve C1 indicates to pass
The distribution of the total rifle number for SET program of uniting, curve C2 indicate the distribution of total rifle number of tradition RESET program, and curve C3 indicates this hair
The distribution of total rifle number of bright SET program, curve C4 indicate the distribution of total rifle number of RESET program of the present invention.As shown in curve C1,
Parts of traditional SET program needs total rifle number more than 6 or more.As shown in curve C3, all SET programs of the present invention all only need
Total rifle number lower than 6.That is, the service speed of SET program of the invention is improved.
As shown in curve C2, traditional RESET program of part needs total rifle number more than 6 or more.As shown in curve C4, institute
The RESET program of the present invention having all only needs total rifle number lower than 6.That is, the service speed of RESET program of the invention
Improved.
Referring to figure 4., for according to the distribution of impedance figure of the present embodiment.It is three curves C5, C6, C7 that Fig. 4, which is drawn,.Curve C5
It indicating to execute the distribution of impedance after SET program of the present invention, curve C6 indicates to execute the distribution of impedance after RESET program of the present invention,
Curve C7 indicates to execute the distribution of impedance after FORM program of the present invention.One window (window) W1 is formed in curve C5 and curve C6
Between, SET state is significantly distinguished with RESET state.That is, even if total rifle number has reduced, SET program with
RESET program still has good result.
A~5B referring to figure 5. is painted the flow chart of memory operating method according to another embodiment.Please refer to table
5, in the first step cycle SL21 and the second step cycle SL22, first control voltage CV1 and second control voltage CV2 according to
Table 5 is set.
Table 5
In this embodiment, the first step cycle SL51 is similar to the first step cycle SL21, and something in common is not in weight
Multiple narration.In the step S531 of the second step cycle SL52, fixed value is less than the first end value.Fixed value can be according to the following formula
(1) it is calculated.
FX=FN- Δ ... ... ... ... ... ... ... ... (1)
FX is fixed value, and FN is the first end value, and Δ is 0~the first end value.
Alternatively, in another embodiment, the ratio of fixed value and the first end value can be higher than 0.8.Alternatively, in another reality
It applies in example, the difference of fixed value and the first end value can be greater than 0.1V.For example, the first end value is 5V, and fixed value is
4.5V。
Since the first control voltage CV1 of the second step cycle SL52 is fixed on lower than the first end value value (i.e. fixed value
Lower than the first end value), rewrite (over-writing) the case where can effectively be avoided by.
That is, that is to say, that in the first step cycle SL51, be applied to the first control of the first control line CL1
Voltage CV1 increases to the first end value (being greater than the first initial value) by the first initial value；It is applied to the second of the second control line CL2
Control voltage CV2 is fixed in the second initial value.In the second step cycle SL52, it is applied to the first of the first control line CL1
Control voltage CV1 is fixed on fixed value (less than the first end value)；It is applied to the second control voltage CV2 of the second control line CL2
Therefrom intermediate value (being higher than the second initial value) increases to the second end value (being higher than middle intermediate value).
According to above-mentioned various embodiments, by execute the first step cycle SL21, SL51 and the second step cycle SL22,
SL52, service speed can significantly improve.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
Describe in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in protection of the invention
Within the scope of.
Claims (10)
1. a kind of memory operating method, comprising:
One first step cycle is executed, wherein being applied to one first control of one first control line in first step cycle
Voltage increases to one first end value by one first initial value, which is higher than first initial value, and is applied to one
One second control voltage of the second control line is fixed on one second initial value；And
One second step cycle is executed, wherein being applied to the first control electricity of first control line in second step cycle
Pressing schedules a fixed value, and the second control voltage for being applied to second control line increases to one second most by intermediate value in one
Final value, second end value are higher than second initial value.
2. memory operating method as described in claim 1, wherein intermediate value is higher than second initial value in this.
3. memory operating method as described in claim 1, wherein the fixed value be equal to first end value or lower than this
One end value.
4. memory operating method as claimed in claim 3, wherein a ratio of the fixed value and first end value is higher than
0.8。
5. memory operating method as described in claim 1, wherein second step cycle is implemented in first step cycle
Later.
6. a kind of storage operation device, comprising:
One first controller, to control the one first control voltage for being applied to one first control line；
One second controller, to control the one second control voltage for being applied to the second control line；And
One processor, to execute one first step cycle and one second step cycle, wherein
In first step cycle, the one first control voltage for being applied to one first control line is increased to by one first initial value
One first end value, first end value are higher than first initial value, and are applied to one second control electricity of one second control line
Pressing schedules one second initial value；And
In second step cycle, the first control voltage for being applied to first control line is fixed on a fixed value, and applies
The second control voltage for being added on second control line increases to one second end value by intermediate value in one, which is higher than
Second initial value.
7. storage operation device as claimed in claim 6, wherein intermediate value is higher than second initial value in this.
8. storage operation device as claimed in claim 6, wherein the fixed value be equal to first end value or lower than this
One end value.
9. storage operation device as claimed in claim 8, wherein a ratio of the fixed value and first end value is higher than
0.8。
10. storage operation device as claimed in claim 6, wherein second step cycle is implemented in first step cycle
Later.
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| CN201710366000.7A CN108962313A (en) | 2017-05-23 | 2017-05-23 | Memory operating method and storage operation device |
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| CN201710366000.7A CN108962313A (en) | 2017-05-23 | 2017-05-23 | Memory operating method and storage operation device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111564168A (en) * | 2019-02-13 | 2020-08-21 | 旺宏电子股份有限公司 | Control method for progressive resistance characteristic of resistive memory element |
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