CN103943148B - Flash memory and its reset signal output method - Google Patents
Flash memory and its reset signal output method Download PDFInfo
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- CN103943148B CN103943148B CN201410214734.XA CN201410214734A CN103943148B CN 103943148 B CN103943148 B CN 103943148B CN 201410214734 A CN201410214734 A CN 201410214734A CN 103943148 B CN103943148 B CN 103943148B
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Abstract
The present invention provides a kind of flash memory and its reset signal output method, the flash memory has controller and the memorizer by controller access, wherein, flash memory is additionally provided with reset signal output pin, the reset pin of controller is connected with reset signal output pin, reset circuit is provided with reset pin, reset circuit includes first resistor, first switch, second switch and the second resistance being sequentially connected in series, first switch is opened and closed by controller control with second switch, and reset signal output pin is connected between first switch and second switch.The method is before flash memory initialization terminates, controller control first switch disconnects, and control second switch closure, reset signal output pin exports low level signal, after flash memory initialization terminates, controller control first switch closure, and second switch disconnection is controlled, reset signal output pin output high level signal.The present invention can ensure that the synchronous communication of embedded controller and flash memory.
Description
Technical field
The present invention relates to integrated circuit fields, specifically a kind of flash memory and this flash memory are answered
Position signal output method.
Background technology
Present portable electric appts, MP3 music players, mobile phone, panel computer etc. are in a large number using embedded
Chip, embedded chip can be considered as an embedded system, and which includes an embedded controller and non-volatile memories
Device, is usually used flash memory (flash) as nonvolatile memory.Existing SPI flash memories are a kind of little Rong
Amount, the nonvolatile semiconductor memory member for encapsulating simple, easy to use, repeatable burning, its memory capacity by 1MB to 16MB,
But production cost is raised with the increase of capacity rapidly.
Existing SPI flash memories need to quickly respond to the read-write requests of embedded Control, generally its storage organization
For NOR Flash, therefore also referred to as SPI NOR Flash.When embedded chip starts, embedded controller will be stored in
Program in SPI NOR Flash is read in embedded controller, and the operation in random access memory (RAM).With embedded
The function of formula chip is stronger and stronger, needs the data being stored in inside SPI NOR Flash except increasingly huger program,
Also increasing Voice ＆ Video data.The capacity of existing SPI NOR Flash is increasingly difficult to meet this trend will
Ask.
NAND Flash are a kind of Large Copacity, low cost, the nonvolatile semiconductor memory member of repeatable burning, but NAND
Flash access modes are complicated, need powerful error correcting capability, and data storage management difficulty is big, and storage mode is complicated.In order to meet
Huge program and data capacity requirement.Existing some embedded chips substituted for existing SPI using NAND Flash
Nonvolatile semiconductor memory members of the NOR Flash as embedded chip, but therefore the production cost of embedded chip be significantly increased,
The development difficulty of embedded chip is also increasing.
In order to solve the contradiction of memory capacity and cost, people have developed a kind of SPI for being referred to as SPI NAND Flash and dodge
Fast memorizer, NAND Flash and controller is packaged together, and is applied in embedded chip.But because NAND Flash
Management difficulty it is big, initialization time length and be difficult to determine, add the limitation of SPI communication agreement, the control of embedded chip
Device processed is generally difficult to determine the time for reading SPI NAND Flash for the first time that the synchronous difficulty of realization startup is very big, so as to limit
The range of application of SPI NAND Flash.
The content of the invention
The main object of the present invention is to provide one kind when embedded chip starts, and can be embedded into formula controller and synchronously visit
The flash memory asked.
It is a further object of the present invention to provide guaranteeing the embedded controller flash memory synchronous with flash memory
Reset signal output method.
In order to realize above-mentioned main purpose, the flash memory that the present invention is provided has controller and is visited by controller
The memorizer asked, wherein, flash memory is additionally provided with reset signal output pin, and the reset pin of controller is defeated with reset signal
Go out pin connection, in reset pin, be provided with reset circuit, first resistor that reset circuit includes being sequentially connected in series, first switch, the
Two switches and second resistance, first switch are opened and closed by controller control with second switch, and reset signal output pin is connected to
Between first switch and second switch.
From such scheme, after embedded system starts, in flash memory initialization procedure, controller control the
One switch and the break-make of second switch, make reset signal output pin export low level signal.Treat flash memory initialization knot
Shu Hou, controller control first switch and the break-make of second switch, make reset signal output pin export high level signal, are embedded in
Formula controller can determine the initialization end time of flash memory, so that it is guaranteed that flash memory can be embedded into formula control
Device synchronization of access processed.
Further scheme is, reset signal output pin is multiplexing pins, and the termination pin with flash memory or
Write-protect pin multiplexing.
As can be seen here, reset signal output pin and other functions pin multiplexing, do not increase the number of pins of flash memory
Amount, will not increase the production cost of flash memory.
Further scheme is that first switch is audion or field effect transistor, and first switch is audion or field effect
Pipe.
It can be seen that, controller realizes opening for first switch and second switch by controlling the break-make of audion or field effect transistor
Close, the open and close controlling of two switches is simple, accurate.
To realize above-mentioned another object, the present invention provides the reset signal output method of above-mentioned flash memory, including
Before flash memory initialization terminates, controller control first switch disconnects, and controls second switch closure, reset signal output
Pin exports low level signal, and after flash memory initialization terminates, controller control first switch is closed, and control second is opened
Shut-off is opened, reset signal output pin output high level signal.
From such scheme, the level signal of reset signal output pin output not phase before and after flash memory initialization
Together, embedded controller may determine that whether flash memory initializes and finishes according to the signal for receiving, and treat flash memory
Initialization accesses flash memory after finishing, so that it is guaranteed that embedded controller and flash memory work asynchronously.
Further scheme is, after flash memory initialization terminates and into after normal operating conditions, controller control
First switch is disconnected with second switch, reset signal output pin output high-impedance state signal.
As can be seen here, controller can accurately judge that flash according to the signal sent by the flash memory for being received
The working condition of memorizer, is conducive to access of the embedded controller to flash memory.
Description of the drawings
Fig. 1 is flash memory embodiment packaging pin structure chart of the present invention.
Fig. 2 is the inside electrical schematic diagram of flash memory embodiment of the present invention.
Fig. 3 is the electrical schematic diagram of reset circuit in flash memory embodiment of the present invention.
Fig. 4 is the equivalent circuit diagram in the case where reset state is started of reset circuit in flash memory embodiment of the present invention.
Fig. 5 is the equivalent circuit diagram in the case where reset state is terminated of reset circuit in flash memory embodiment of the present invention.
Fig. 6 is the equivalent circuit diagram in normal operation of reset circuit in flash memory embodiment of the present invention.
Fig. 7 is the structure chart that flash memory embodiment of the present invention is electrically connected with embedded controller.
Fig. 8 is the sequential of the output signal of the multiple pins of reset signal output method embodiment of flash memory of the present invention
Figure.
Below in conjunction with drawings and Examples, the invention will be further described.
Specific embodiment
The flash memory of the present invention is mainly used in embedded system, and embedded system is embedded chip, its tool
There are embedded controller and flash memory, embedded controller can control the work of flash memory, and read sudden strain of a muscle
The data stored by fast memorizer, and work asynchronously with flash memory.
Referring to Fig. 1 and Fig. 2, the flash memory 10 of the present invention has controller 11 and memorizer 12, and memorizer 12 is
Nand Flash, are a kind of nonvolatile memories, and controller 11 is by the access of controlling bus, address bus and data/address bus
Memorizer 12, reading are stored in the data in memorizer 12 or write data to memorizer 12.
The housing of flash memory 10 is externally provided with eight packaging pins, is chip select pin CSB1, communication clock pin respectively
CLK1, data-out pin SDI1, data output pins SDO1, write-protect pin WPB1, reset stop multiplexing pins HOLDB1,
Power pins VDD1 and grounding pin GND1, eight packaging pins of flash memory 10 and the embedded control of embedded chip
The corresponding pin connection of device processed, so that embedded controller accesses flash memory 10.In the present embodiment, the termination multiplexing that resets is drawn
Foot HOLDB1 both can be used as reset signal output pin as multiplexing pins, and was used as pin is stopped, embedded
Controller can send signal to termination multiplexing pins HOLDB1 that reset in different phase or reception carrys out Self-resetting termination multiplexing and draws
The signal of foot HOLDB1.
The controller 11 of flash memory 10 also is provided with eight pins, is chip select pin CSB, communication clock pin respectively
CLK, data-out pin SDI, data output pins SDO, write-protect pin WPB, reset stop multiplexing pins HOLDB, power supply
Pin VDD and grounding pin GND, wherein termination multiplexing pins HOLDB that reset are also multiplexing pins, both made as reset pin
With, and use as pin is stopped.
As it is clear from fig. 2 that each pin of controller 11 and the connection of 10 corresponding pin of flash memory, i.e. controller 11
Chip select pin CSB be connected with chip select pin CSB1 of flash memory 10, the clock pins CLK of controller 11 is stored with flash
The clock pins CLK1 connections of device 10, the data-out pin SDI of controller 11 and the data-out pin of flash memory 10
SDI1 connects, and 11 data output pins SDO of controller is connected with the data output pins SDO1 of flash memory 10, controller 11
Write-protect pin WPB be connected with the write-protect pin WPB1 of flash memory 10, the reset of controller 11 stops multiplexing pins
HOLDB stops multiplexing pins HOLDB1 with the reset of flash memory 10 and is connected.
In order to ensure flash memory 10 accurately exports reset signal to embedded controller, in the reset of controller 11
Only reset circuit is provided with multiplexing pins HOLDB.As shown in figure 3, reset circuit include resistance R1, as three poles of switching device
Pipe T1, audion T2 and resistance R2, the first termination power vd D of resistance R1, the second end is connected to audion T1, audion T1
It is connected in series with audion T2, and audion T1, T2 controls break-make by controller 11.The reset of flash memory 10 stops multiple
The junction of audion T1 and audion T2 is connected to pin HOLDB1.The first end of resistance R2 is connected with audion T2, the
Two ends are grounded.Certainly, audion T1, T2 of the invention can be substituted using field effect transistor.
In electric and initialization procedure on flash memory 10, the control audion T1 cut-offs of controller 11, and control three
Pole pipe T2 is turned on, and now the equivalent circuit of reset circuit is as shown in figure 4, switch the equivalent audion T1 of S1 used in Fig. 4, using opening
Close the equivalent audion T2 of S2.As seen from Figure 4, before the initialization of flash memory 10 terminates, switch S1 is off, and switchs S2
It is in the conduction state, therefore the level signal of the termination multiplexing pins HOLDB1 output that resets is low level signal.
After the initialization of flash memory 10 terminates, reset circuit is entered and terminates reset state, now equivalent circuit such as Fig. 5
It is shown.The control audion T1 conductings of controller 11, and audion T2 cut-offs are controlled, equivalent to switch S1 closures, switch S2 disconnects,
Power vd D stops multiplexing pins HOLDB1 by switch S1 and exports high level signal, therefore the termination multiplexing pins that reset to resetting
The level signal of HOLDB1 outputs is high level signal.
After the initialization of flash memory 10 terminates and when entering normal operating conditions, the control audion T1 of controller 11,
T2 ends simultaneously, as shown in fig. 6, switch S1 is disconnected with switch S2, now resetting stops the electricity of multiplexing pins HOLDB1 output
Ordinary mail number is high-impedance state signal.It can be seen that, the reset of flash memory 10 stops multiplexing pins HOLDB1 at the beginning of flash memory 10
Before beginningization terminates, initialization terminate after and the level signal that exports into after normal operating conditions differ, embedded Control
Device may determine that the current state of flash memory 10 according to the level signal for receiving, and be easy to synchronous with flash memory 10 logical
Letter.
Preferably, resistance R1 is differed with the resistance value of resistance R2, and for example, the resistance of resistance R1 is 100 kilo-ohms, resistance R2
Resistance be 10 kilo-ohms, it is ensured that reset and stop high level signal and low level signal, the high-impedance state of the output of multiplexing pins HOLDB1
The level of signal has significantly difference, and embedded controller just can accurately judge that the different work shape of flash memory 10
State.
Certainly, during practical application, the resistance of resistance R1 can be more than the resistance of the resistance, or resistance R1 of resistance R2
Less than the resistance of resistance R2, or, the resistance of resistance R1 is equal with the resistance of resistance R2.Also, the resistance of resistance R1, R2 can be with
Determined according to the actual parameter of reset circuit, controller 11, supply voltage VDD.
Referring to Fig. 7, embedded chip 20 includes embedded controller 21 and flash memory 10, embedded controller bag
Include reset signal input pin RSTB, clock signal output pin MCLK, data output pins MSDO, data-out pin
MSDI, write-protect output pin MPWB and gating output pin MCSB.Wherein, reset signal pin RSTB and flash memory
10 reset stops the clock pins of the connection of multiplexing pins HOLDB1, clock signal output pin MCLK and flash memory 10
CLK1 connects, and data output pins MSDO is connected with the data-out pin SDI1 of flash memory 10, data-out pin
MSDI is connected with the data output pins SDO1 of flash memory 10, the write-protect of write-protect pin MPWB and flash memory 10
Pin WPB1 connects, and gating output pin MCSB is connected with chip select pin CSB1 of flash memory 10, and reset signal input is drawn
Foot RSTB is connected to one end of electric capacity C1, the other end ground connection of electric capacity C1.
The reset signal output procedure of flash memory 10 is illustrated with reference to Fig. 8.The initialization of flash memory 10 terminates
Before, which is in startup reset state, and output pin MCLK is equal for the gating output pin MCSB of embedded controller 21, clock signal
For high level signal, data-out pin MSDI, data output pins MSDO are high-impedance state, and write-protect output pin MWPB is
Low level signal.Now, as reset circuit breaker in middle S1 disconnects, and S2 closures are switched, the reset of flash memory 10 stops
Multiplexing pins HOLDB1 export low level signal, and the reset signal input pin RSTB of embedded controller 21 receives low level
Signal.With when, flash memory 10 carries out initial work to memorizer 12, until the initial work of memorizer 12 terminates,
After flash memory 10 is ready to communicate with embedded controller 21, flash memory 10 is entered and terminates reset state.
Terminating reset state, due to switching S1 closures, and switching S2 disconnections, the reset of flash memory 10 is stopping multiplexing
Pin HOLDB1 exports high level signal, and electric capacity C1 starts to charge up, the level signal that reset signal input pin RSTB is received by
High level VDD is risen to gradually, the control embedded controller 21 of flash memory 10 enters init state.
After embedded controller 21 enters init state, embedded controller 21 carries out initial work, including matching somebody with somebody
Put communication sequential of flash memory 10 etc..Then, embedded controller 21 starts the data for reading flash memory 10, that is, enter
Row simultaneously operating.After embedded controller 21 reads log-on data from flash memory 10, embedded chip 20 is entered
Normal operating conditions.So far, the start-up course of embedded chip 20 is completed.
It can be seen that, flash memory 10 is starting reset state, is terminating what is exported under reset state and normal operating conditions
Signal is differed, and embedded controller 21 can judge the working condition of flash memory 10, flash according to the chip for receiving
Memorizer 10 resets after terminating immediately into normal operating conditions, it is ensured that embedded controller 21 is synchronous with flash memory 10
Communication.
Certainly, above-described embodiment is only the preferred embodiment of the present invention, can also have more changes during practical application,
For example reset signal output pin not singly can with stop pin multiplexing, can with write-protect pin WPB pin multiplexings；Or
Person, flash memory can have data-out pin, a data output pins, it is possibility to have multiple data-out pins, many
Individual data output pins；Or, flash memory works in normal operation, it is also possible to close switch S1, i.e., multiple
Position signal output pin output high level signal, such change have no effect on the enforcement of the present invention.
Finally it is emphasized that the invention is not restricted to above-mentioned embodiment, such as flash memory, control implement body pin
Change, in reset circuit the change such as change of resistance value of two resistance should also be included in the protection of the claims in the present invention
In the range of.
Claims (10)
1. flash memory, including：
Controller and the memorizer by the controller access；
It is characterized in that：
The flash memory is additionally provided with reset signal output pin, and the reset pin of the controller is defeated with the reset signal
Go out pin connection；
Be provided with reset circuit in the reset pin, first resistor that the reset circuit includes being sequentially connected in series, first switch,
Two switches and second resistance, the first switch are opened and closed by controller control with the second switch, the letter that resets
Number output pin is connected between the first switch and the second switch.
2. flash memory according to claim 1, it is characterised in that：
The reset signal output pin is multiplexing pins.
3. flash memory according to claim 2, it is characterised in that：
The termination pin or write-protect pin multiplexing of the reset signal output pin and the flash memory.
4. the flash memory according to any one of claims 1 to 3, it is characterised in that：
Resistance value of the resistance value of the first resistor more than or less than the second resistance.
5. the flash memory according to any one of claims 1 to 3, it is characterised in that：
The first resistor is connected with power supply, the second resistance ground connection.
6. the flash memory according to any one of claims 1 to 3, it is characterised in that：
The first switch is audion or field effect transistor, and the second switch is audion or field effect transistor.
7. the reset signal output method of flash memory, the flash memory have controller and memorizer, reset signal
Output pin, the reset pin of the controller are connected with the reset signal output pin, and are provided with the reset pin
Reset circuit, the reset circuit include first resistor, first switch, second switch and the second resistance being sequentially connected in series；
It is characterized in that：The method includes
Before the flash memory initialization terminates, the controller controls the first switch and disconnects, and controls described second
Switch closure, the reset signal output pin export low level signal；
After the flash memory initialization terminates, the controller controls the first switch closure, and controls described second
Switch off, the reset signal output pin exports high level signal.
8. the reset signal output method of flash memory according to claim 7, it is characterised in that：
After the flash memory initialization terminates and into after normal operating conditions, the controller controls the first switch
Disconnect with the second switch, the reset signal output pin exports high-impedance state signal.
9. the reset signal output method of the flash memory according to claim 7 or 8, it is characterised in that：
During the reset signal output pin is multiplexing pins, and the reset signal output pin and the flash memory
Only pin or write-protect pin multiplexing.
10. the reset signal output method of the flash memory according to claim 7 or 8, it is characterised in that：
The first resistor is connected with power supply, the second resistance ground connection.
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| CN201410214734.XA CN103943148B (en) | 2014-05-20 | 2014-05-20 | Flash memory and its reset signal output method |
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| CN103366827B (en) * | 2013-06-26 | 2017-02-08 | 上海华虹宏力半导体制造有限公司 | Storage device and method for testing storage device through testing machine |
| JP6946773B2 (en) * | 2017-06-20 | 2021-10-06 | セイコーエプソン株式会社 | Real-time clock modules, electronic devices, mobiles and information processing systems |
| KR102504180B1 (en) * | 2018-03-22 | 2023-02-28 | 에스케이하이닉스 주식회사 | Semiconductor system for conducting a reset operation |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201146049Y (en) * | 2008-01-23 | 2008-11-05 | 青岛海信电器股份有限公司 | Hardware circuit capable of being compatible a plurality of memories and electrical installation with the same |
| CN203870983U (en) * | 2014-05-20 | 2014-10-08 | 建荣集成电路科技(珠海)有限公司 | Flash memory |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201146049Y (en) * | 2008-01-23 | 2008-11-05 | 青岛海信电器股份有限公司 | Hardware circuit capable of being compatible a plurality of memories and electrical installation with the same |
| CN203870983U (en) * | 2014-05-20 | 2014-10-08 | 建荣集成电路科技(珠海)有限公司 | Flash memory |
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Effective date of registration: 20220318 Address after: Rooms 1306-1309, 13 / F, 19 science Avenue West, Hong Kong Science Park, Shatin, New Territories, China Patentee after: BUILDWIN INTERNATIONAL (ZHUHAI) LTD. Address before: 519015 3rd Floor, Stereo Science and Technology Building, 184 Bailian Road, Jida, Zhuhai City, Guangdong Province Patentee before: BUILDWIN INTERNATIONAL (ZHUHAI) Ltd. |