CN103943148A - Flash memory and reset signal output method thereof - Google Patents
Flash memory and reset signal output method thereof Download PDFInfo
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- CN103943148A CN103943148A CN201410214734.XA CN201410214734A CN103943148A CN 103943148 A CN103943148 A CN 103943148A CN 201410214734 A CN201410214734 A CN 201410214734A CN 103943148 A CN103943148 A CN 103943148A
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Abstract
The invention provides a flash memory and a reset signal output method thereof. The flash memory comprises a controller, a memory body accessed by the controller, and a reset signal output pin, wherein a reset pin of the controller is connected with the reset signal output pin; a reset circuit is arranged inside the reset pin, and comprises a first resistor, a first switch, a second switch and a second resistor, which are sequentially connected with one another in series; the first switch and the second switch are controlled to be on and off by the controller; the reset signal output pin is connected to the first switch and the second switch. The method comprises the following steps: before initialization of the flash memory is ended, the controller controls the first switch to be off and controls the second switch to be on, and the reset signal output pin outputs a low-level signal; after initialization of the flash memory is ended, the controller controls the first switch to be on and controls the second switch to be off, and the reset signal output pin outputs a high-level signal. Synchronous communication of the embedded controller and the flash memory can be ensured.
Description
Technical field
The present invention relates to integrated circuit fields, particularly, is the reset signal output method of a kind of flash memory and this flash memory.
Background technology
Present portable electric appts, such as a large amount of embedded chips that use such as MP3 music player, mobile phone, panel computer, embedded chip can be considered as an embedded system, it comprises an embedded controller and nonvolatile memory, conventionally uses flash memory (flash) as nonvolatile memory.Existing SPI flash memory is a kind of low capacity, encapsulate simple, easy to use, can to repeat burning nonvolatile semiconductor memory member, and by 1MB to 16MB not etc., but production cost raises rapidly along with the increase of capacity its memory capacity.
Existing SPI flash memory need to quickly respond to the read-write requests of embedded Control, and its storage organization is NOR Flash conventionally, therefore also referred to as SPI NOR Flash.When embedded chip starts, embedded controller reads the program being stored in SPI NOR Flash in embedded controller, and operation in random access memory (RAM).Along with the function of embedded chip from strength to strength, need to leave the data of SPI NOR Flash the inside in except more and more huger program, also have increasing Voice & Video data.The capacity of existing SPI NOR Flash more and more difficulty meets this trend requirement.
NAND Flash is a kind of large capacity, low cost, can repeats the nonvolatile semiconductor memory member of burning, but NAND Flash access mode complexity needs powerful error correcting capability, and data storage management difficulty is large, storage mode complexity.In order to meet huge program and data capacity demand.More existing embedded chips adopt NAND Flash to replace the nonvolatile semiconductor memory member of existing SPI NOR Flash as embedded chip, but therefore and significantly the production cost that embeds chip increase, and the development difficulty of embedded chip is also increasing.
In order to solve the contradiction of memory capacity and cost, people have researched and developed the SPI flash memory of a kind of SPI of being called NAND Flash, NAND Flash and controller are packaged together, and are applied in embedded chip.But because the management difficulty of NAND Flash is large, initialization time is grown and is difficult to determine, add the limitation of SPI communication protocol, the controller of embedded chip is difficult to determine the time of reading for the first time SPI NAND Flash conventionally, realize the synchronous difficulty of startup very large, thereby limited the range of application of SPI NAND Flash.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of in the time that embedded chip starts, and can be embedded into the flash memory of formula controller synchronization of access.
Another object of the present invention is to provide the reset signal output method of the flash memory of guaranteeing that embedded controller synchronizes with flash memory.
In order to realize above-mentioned fundamental purpose, flash memory provided by the invention has controller and by the storer of controller access, wherein, flash memory is also provided with reset signal output pin, the reset pin of controller is connected with reset signal output pin, in reset pin, be provided with reset circuit, reset circuit comprises the first resistance, the first switch, second switch and second resistance of series connection successively, the first switch and second switch are opened and closed by controller control, and reset signal output pin is connected between the first switch and second switch.
From such scheme, after embedded system starts, in flash memory initialization procedure, the break-make of controller control the first switch and second switch, makes reset signal output pin output low level signal.After flash memory initialization finishes, the break-make of controller control the first switch and second switch, make reset signal output pin output high level signal, embedded controller can determine the initialization end time of flash memory, thereby guarantees that flash memory can be embedded into formula controller synchronization of access.
Further scheme is, reset signal output pin is multiplexing pins, and with termination pin or the write-protect pin multiplexing of flash memory.
As can be seen here, reset signal output pin and other functional pins are multiplexing, do not increase the pin number of flash memory, can not increase the production cost of flash memory.
Further scheme is, the first switch is triode or field effect transistor, and the first switch is triode or field effect transistor.
Visible, controller is realized the switching of the first switch and second switch by controlling the break-make of triode or field effect transistor, and the open and close controlling of two switches is simple, accurate.
For realizing another above-mentioned object, the invention provides the reset signal output method of above-mentioned flash memory, before comprising that flash memory initialization finishes, controller control the first switch disconnects, and controls second switch closure, reset signal output pin output low level signal, after flash memory initialization finishes, controller control the first switch closure, and control second switch disconnection, reset signal output pin output high level signal.
From such scheme, before and after flash memory initialization, the level signal of reset signal output pin output is not identical, embedded controller can judge flash memory according to the signal receiving, and whether initialization is complete, treat to access flash memory after flash memory initialization, thereby guarantee synchronousing working of embedded controller and flash memory.
Further scheme is, flash memory initialization finishes rear and enters after normal operating conditions, and controller control the first switch and second switch disconnect, reset signal output pin output high-impedance state signal.
As can be seen here, the signal that controller sends according to received flash memory can accurately judge the duty of flash memory, is conducive to the access of embedded controller to flash memory.
Brief description of the drawings
Fig. 1 is flash memory embodiment packaging pin structural drawing of the present invention.
Fig. 2 is the internal electrical schematic diagram of flash memory embodiment of the present invention.
Fig. 3 is the electrical schematic diagram of reset circuit in flash memory embodiment of the present invention.
Fig. 4 is the equivalent circuit diagram under startup reset mode of reset circuit in flash memory embodiment of the present invention.
Fig. 5 is the equivalent circuit diagram under end reset mode of reset circuit in flash memory embodiment of the present invention.
Fig. 6 is the equivalent circuit diagram in normal operation of reset circuit in flash memory embodiment of the present invention.
Fig. 7 is the structural drawing that flash memory embodiment of the present invention is electrically connected with embedded controller.
Fig. 8 is the sequential chart of the output signal of the multiple pins of reset signal output method embodiment of flash memory of the present invention.
Below in conjunction with drawings and Examples, the invention will be further described.
Embodiment
Flash memory of the present invention is mainly used in embedded system, embedded system is embedded chip, it has embedded controller and flash memory, embedded controller can be controlled the work of flash memory, and read the data that flash memory is stored, and synchronous working with flash memory.
Referring to Fig. 1 and Fig. 2, flash memory 10 of the present invention has controller 11 and storer 12, storer 12 is Nand Flash, it is a kind of nonvolatile memory, controller 11 is by control bus, address bus and data bus reference-to storage 12, reads the data that are stored in storer 12 or to storer 12 data writings.
The housing of flash memory 10 is provided with eight packaging pins outward; respectively that sheet selects pin CSB1, communication clock pin CLK1, data input pin SDI1, data output pin SDO1, write-protect pin WPB1, resets and end multiplexing pins HOLDB1, power pins VDD1 and grounding pin GND1; eight packaging pins of flash memory 10 are connected with the corresponding pin of embedded controller of embedded chip, so that embedded controller access flash memory 10.In the present embodiment, reset and end multiplexing pins HOLDB1 as multiplexing pins, both having can be used as reset signal output pin uses, use as ending pin again, embedded controller can be ended multiplexing pins HOLDB1 and send signal or receive Self-resetting the signal of ending multiplexing pins HOLDB1 to resetting in different phase.
The controller 11 of flash memory 10 is also provided with eight pins; respectively that sheet selects pin CSB, communication clock pin CLK, data input pin SDI, data output pin SDO, write-protect pin WPB, resets and end multiplexing pins HOLDB, power pins VDD and grounding pin GND; the termination multiplexing pins that wherein resets HOLDB is also multiplexing pins; both used as reset pin, used as ending pin again.
As seen from Figure 2, each pin pin corresponding with flash memory 10 of controller 11 connects, the sheet that is controller 11 selects pin CSB and the sheet of flash memory 10 to select pin CSB1 to be connected, the clock pin CLK of controller 11 is connected with the clock pin CLK1 of flash memory 10, the data input pin SDI of controller 11 is connected with the data input pin SDI1 of flash memory 10, controller 11 data output pin SDO are connected with the data output pin SDO1 of flash memory 10, the write-protect pin WPB of controller 11 is connected with the write-protect pin WPB1 of flash memory 10, the reset of controller 11 is ended multiplexing pins HOLDB and is connected with the reset termination multiplexing pins HOLDB1 of flash memory 10.
In order to ensure flash memory 10, accurately to embedded controller output reset signal, the reset of controller 11 is ended to be provided with reset circuit in multiplexing pins HOLDB.As shown in Figure 3, reset circuit comprises resistance R 1, triode T1, triode T2 and resistance R 2 as switching device, the first termination power vd D of resistance R 1, the second end is connected to triode T1, triode T1 and triode T2 are connected in series, and triode T1, T2 control break-make by controller 11.The reset termination multiplexing pins HOLDB1 of flash memory 10 is connected to the junction of triode T1 and triode T2.The first end of resistance R 2 is connected with triode T2, the second end ground connection.Certainly, triode T1 of the present invention, T2 all can use field effect transistor to substitute.
Flash memory 10 power on and initialization procedure in, controller 11 is controlled triode T1 cut-off, and controls triode T2 conducting, and now the equivalent electrical circuit of reset circuit as shown in Figure 4, in Fig. 4, use the equivalent triode T1 of switch S 1, use the equivalent triode T2 of switch S 2.As seen from Figure 4, before flash memory 10 initialization finish, switch S 1 is in off-state, and switch S 2 is in conducting state, and the level signal of the termination multiplexing pins that therefore resets HOLDB1 output is low level signal.
After flash memory 10 initialization finish, reset circuit enters end reset mode, and now equivalent electrical circuit as shown in Figure 5.Controller 11 is controlled triode T1 conducting, and control triode T2 and end, be equivalent to switch S 1 closure, switch S 2 disconnects, power vd D passes through switch S 1 and ends multiplexing pins HOLDB1 output high level signal to resetting, and the level signal of the termination multiplexing pins that therefore resets HOLDB1 output is high level signal.
After flash memory 10 initialization finish and while entering normal operating conditions, controller 11 is controlled triode T1, T2 and is ended simultaneously, as shown in Figure 6, switch S 1 all disconnects with switch S 2, and the level signal of the termination multiplexing pins that now resets HOLDB1 output is high-impedance state signal.Visible, the reset of flash memory 10 end multiplexing pins HOLDB1 before flash memory 10 initialization finish, initialization finish after and enter normal operating conditions after the level signal exported not identical, embedded controller can judge according to the level signal receiving the state that flash memory 10 is current, is convenient to and flash memory 10 synchronous communications.
Preferably, resistance R 1 is not identical with the resistance value of resistance R 2, for example, the resistance of resistance R 1 is 100 kilo-ohms, the resistance of resistance R 2 is 10 kilo-ohms, the level of ending the high level signal of multiplexing pins HOLDB1 output and low level signal, high-impedance state signal of guaranteeing to reset has obvious difference, and embedded controller just can accurately judge the duty that flash memory 10 is different.
Certainly, when practical application, the resistance of resistance R 1 can be greater than the resistance of resistance R 2, can be also the resistance that the resistance of resistance R 1 is less than resistance R 2, or the resistance of resistance R 1 equates with the resistance of resistance R 2.And the resistance of resistance R 1, R2 can be determined according to the actual parameter of reset circuit, controller 11, supply voltage VDD.
Referring to Fig. 7; embedded chip 20 comprises embedded controller 21 and flash memory 10, and embedded controller comprises reset signal input pin RSTB, clock signal output pin MCLK, data output pin MSDO, data input pin MSDI, write-protect output pin MPWB and gating output pin MCSB.Wherein, reset signal pin RSTB ends multiplexing pins HOLDB1 with the reset of flash memory 10 and is connected, clock signal output pin MCLK is connected with the clock pin CLK1 of flash memory 10, data output pin MSDO is connected with the data input pin SDI1 of flash memory 10, data input pin MSDI is connected with the data output pin SDO1 of flash memory 10, write-protect pin MPWB is connected with the write-protect pin WPB1 of flash memory 10, gating output pin MCSB selects pin CSB1 to be connected with the sheet of flash memory 10, reset signal input pin RSTB is connected to one end of capacitor C 1, the other end ground connection of capacitor C 1.
The reset signal output procedure of flash memory 10 is described below in conjunction with Fig. 8.Before flash memory 10 initialization finish; it is in starting reset mode; gating output pin MCSB, the clock signal output pin MCLK of embedded controller 21 are high level signal; data input pin MSDI, data output pin MSDO are high-impedance state, and write-protect output pin MWPB is low level signal.Now, because switch S in reset circuit 1 disconnects, and switch S 2 closures, multiplexing pins HOLDB1 output low level signal is ended in the reset of flash memory 10, and the reset signal input pin RSTB of embedded controller 21 receives low level signal.With time, flash memory 10 carries out initial work to storer 12, until the initial work of storer 12 finishes, after flash memory 10 is ready to communicate by letter with embedded controller 21, flash memory 10 enters end reset mode.
Finishing reset mode, due to switch S 1 closure, and switch S 2 disconnects, multiplexing pins HOLDB1 output high level signal is ended in the reset of flash memory 10, capacitor C 1 starts charging, the level signal that reset signal input pin RSTB receives rises to high level VDD gradually, and flash memory 10 is controlled embedded controller 21 and entered init state.
Enter after init state at embedded controller 21, embedded controller 21 carries out initial work, comprises the communication sequential of configuring flash memory 10 etc.Then, embedded controller 21 starts to read the data of flash memory 10, carries out synchronous operation.Read after log-on data from flash memory 10 at embedded controller 21, embedded chip 20 enters normal operating conditions.So far, the start-up course of embedded chip 20 completes.
Visible, the signal that flash memory 10 is exported under startup reset mode, end reset mode and normal operating conditions is not identical, embedded controller 21 can judge according to the chip receiving the duty of flash memory 10, flash memory 10 enters normal operating conditions after resetting and finishing immediately, guarantees the synchronous communication of embedded controller 21 and flash memory 10.
Certainly, above-described embodiment is only the preferred embodiment of the present invention, when practical application, can also have more variation, for example reset signal output pin not singly can with end pin multiplexing, can also with write-protect pin WPB pin multiplexing; Or flash memory can have a data input pin, data output pin, also can there be multiple data input pins, multiple data output pin; Or flash memory work in normal operation, also can be by switch S 1 closure, i.e. reset signal output pin output high level signal, such change does not affect enforcement of the present invention.
The variations such as the change of the resistance value of two resistance in the change of flash memory, the concrete pin of controller, reset circuit finally it is emphasized that and the invention is not restricted to above-mentioned embodiment, as also should being included in the protection domain of the claims in the present invention.
Claims (10)
1. flash memory, comprising:
Controller and by the storer of described controller access;
It is characterized in that:
Described flash memory is also provided with reset signal output pin, and the reset pin of described controller is connected with described reset signal output pin;
In described reset pin, be provided with reset circuit, described reset circuit comprises the first resistance, the first switch, second switch and second resistance of series connection successively, described the first switch and described second switch are opened and closed by described controller control, and described reset signal output pin is connected between described the first switch and described second switch.
2. flash memory according to claim 1, is characterized in that:
Described reset signal output pin is multiplexing pins.
3. flash memory according to claim 2, is characterized in that:
The termination pin of described reset signal output pin and described flash memory or write-protect pin multiplexing.
4. according to the flash memory described in claims 1 to 3 any one, it is characterized in that:
The resistance value of described the first resistance is greater than or less than the resistance value of described the second resistance.
5. according to the flash memory described in claims 1 to 3 any one, it is characterized in that:
Described the first resistance is connected with power supply, described the second resistance eutral grounding.
6. according to the flash memory described in claims 1 to 3 any one, it is characterized in that:
Described the first switch is triode or field effect transistor, and described second switch is triode or field effect transistor.
7. the reset signal output method of flash memory, this flash memory has controller and storer, reset signal output pin, the reset pin of described controller is connected with described reset signal output pin, and in described reset pin, be provided with reset circuit, described reset circuit comprises the first resistance, the first switch, second switch and second resistance of series connection successively;
It is characterized in that: the method comprises
Before described flash memory initialization finishes, the first switch disconnects described in described controller control, and controls described second switch closure, described reset signal output pin output low level signal;
After described flash memory initialization finishes, the first switch closure described in described controller control, and control described second switch and disconnect, described reset signal output pin output high level signal.
8. the reset signal output method of flash memory according to claim 7, is characterized in that:
After described flash memory initialization finishes and enter after normal operating conditions, the first switch disconnects with described second switch described in described controller control, and described reset signal output pin is exported high-impedance state signal.
9. according to the reset signal output method of the flash memory described in claim 7 or 8, it is characterized in that:
Described reset signal output pin is multiplexing pins, and the termination pin of described reset signal output pin and described flash memory or write-protect pin multiplexing.
10. according to the reset signal output method of the flash memory described in claim 5 or 6, it is characterized in that:
Described the first resistance is connected with power supply, described the second resistance eutral grounding.
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| CN201410214734.XA CN103943148B (en) | 2014-05-20 | 2014-05-20 | Flash memory and its reset signal output method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103366827A (en) * | 2013-06-26 | 2013-10-23 | 上海宏力半导体制造有限公司 | Storage device and method for testing storage device through testing machine |
| CN109101076A (en) * | 2017-06-20 | 2018-12-28 | 精工爱普生株式会社 | Real-time clock module, electronic equipment, moving body and information processing system |
| CN110297533A (en) * | 2018-03-22 | 2019-10-01 | 爱思开海力士有限公司 | Semiconductor packages relevant to reset operation is executed and semiconductor system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201146049Y (en) * | 2008-01-23 | 2008-11-05 | 青岛海信电器股份有限公司 | Hardware circuit capable of being compatible a plurality of memories and electrical installation with the same |
| CN203870983U (en) * | 2014-05-20 | 2014-10-08 | 建荣集成电路科技(珠海)有限公司 | Flash memory |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103366827A (en) * | 2013-06-26 | 2013-10-23 | 上海宏力半导体制造有限公司 | Storage device and method for testing storage device through testing machine |
| CN109101076A (en) * | 2017-06-20 | 2018-12-28 | 精工爱普生株式会社 | Real-time clock module, electronic equipment, moving body and information processing system |
| CN110297533A (en) * | 2018-03-22 | 2019-10-01 | 爱思开海力士有限公司 | Semiconductor packages relevant to reset operation is executed and semiconductor system |
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Effective date of registration: 20220318 Address after: Rooms 1306-1309, 13 / F, 19 science Avenue West, Hong Kong Science Park, Shatin, New Territories, China Patentee after: BUILDWIN INTERNATIONAL (ZHUHAI) LTD. Address before: 519015 3rd Floor, Stereo Science and Technology Building, 184 Bailian Road, Jida, Zhuhai City, Guangdong Province Patentee before: BUILDWIN INTERNATIONAL (ZHUHAI) Ltd. |