KR20140008173A - Semiconductor package and method for manufacturing the same - Google Patents

Semiconductor package and method for manufacturing the same Download PDF

Info

Publication number
KR20140008173A
KR20140008173A KR1020120075573A KR20120075573A KR20140008173A KR 20140008173 A KR20140008173 A KR 20140008173A KR 1020120075573 A KR1020120075573 A KR 1020120075573A KR 20120075573 A KR20120075573 A KR 20120075573A KR 20140008173 A KR20140008173 A KR 20140008173A
Authority
KR
South Korea
Prior art keywords
redistribution
insulating layer
forming
bonding pad
buried
Prior art date
Application number
KR1020120075573A
Other languages
Korean (ko)
Inventor
배한준
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020120075573A priority Critical patent/KR20140008173A/en
Publication of KR20140008173A publication Critical patent/KR20140008173A/en

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a semiconductor package and a method for manufacturing the same. The semiconductor package according to the present invention comprises a semiconductor chip having a bonding pad; an insulation layer on the top of the semiconductor chip having the bonding pad with a redistribution forming area for exposing the bonding pad; and a buried redistribution which is formed inside the insulation layer in the redistribution forming area and of which one end is connected to the exposed bonding pad.

Description

Semiconductor package and manufacturing method {SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME}

TECHNICAL FIELD The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package and a method for manufacturing the same in redistribution formation.

Electronic devices are becoming smaller and smaller according to the development of the semiconductor industry and the needs of users. In the semiconductor package, a wafer level package (WLP) in which the size of a semiconductor package is reduced to a chip level, or a system-in-package (SIP) including semiconductor chips performing various functions in a single semiconductor package. There is an increasing need for System In Package, which uses redistribution technology.

In particular, the redistribution is one end of which is electrically connected to the bonding pad of the semiconductor chip included in the semiconductor package. Conventionally, the redistribution is formed on the lower insulating layer exposing the bonding pad. An upper insulating layer is applied on the lower insulating layer to expose one end thereof opposite the other.

However, the conventional rewiring has the following problems.

First, the redistribution line is formed on the lower insulating layer, and the upper insulating layer is formed on the lower insulating layer on which the redistribution line is formed. Adhesion is a problem. That is, the adhesion between the redistribution line and the insulating layer is not good, there is a problem that adversely affects the reliability of the semiconductor package.

Second, the redistribution is usually formed by a plating process. In this case, an undercut is generated in the redistribution during a wet etching process for removing a portion of the seed layer in which the plating layer is not formed. Fine pitch design is difficult.

The present invention provides a semiconductor package having improved reliability for a semiconductor package and a method of manufacturing the same by increasing the adhesion between the redistribution and the insulating layer.

In addition, the present invention provides a semiconductor package and a method of manufacturing the same for easy fine pitch design of redistribution.

A semiconductor package according to an embodiment of the present invention includes an insulating layer having a semiconductor chip having a bonding pad, a redistribution forming region formed on a semiconductor chip including the bonding pad, and exposing the bonding pad. A buried redistribution formed in an insulating layer of the substrate, one end of which is connected to the exposed bonding pad.

The redistribution forming area may include a hole exposing the bonding pad and a line-shaped groove connected to the hole.

The insulating layer is characterized by consisting of a photosensitive polymer.

The buried redistribution has a laminated structure of a seed layer and a plating layer formed on the surface of the redistribution formation region of the insulating layer.

In a method of manufacturing a semiconductor package according to an embodiment of the present invention, forming an insulating layer made of a photosensitive polymer on a semiconductor chip having a bonding pad, and cultivating exposing and developing the insulating layer to expose the bonding pad of the semiconductor chip. Forming a line forming region and forming a buried redistribution line of which one end is connected to the exposed bonding pad in the redistribution forming region.

The forming of the redistribution forming area may include performing primary exposure on the insulating layer such that the insulating layer portion disposed on the bonding pad is completely exposed, and an insulating layer connected to the first exposed insulating layer portion. Performing secondary exposure on the insulating layer on which the primary exposure has been performed so that the portion is partially exposed and developing the insulating layer so that the portions of the primary and secondary exposed insulating layers are removed. It is done.

The secondary exposure may be performed at an exposure amount smaller than that of the primary exposure.

The redistribution forming region may include a hole exposing the bonding pad and a line-shaped groove connected to the hole.

The forming of the buried redistribution may include forming a seed layer on the surface of the insulating layer having the redistribution forming region, and forming a photoresist pattern on the seed layer to expose the seed layer of the redistribution forming region. And forming a plating layer so as to fill the redistribution forming region on the exposed seed layer portion, and removing the photoresist pattern and the seed layer portion below it.

After forming the buried redistribution, the buried redistribution and the insulating layer further comprises the step of forming a capping layer exposing a portion of the buried redistribution.

The forming of the insulating layer and the forming of the buried redistribution may be performed at a wafer level.

And forming the insulating layer at the wafer level or after forming the buried redistribution, sawing at the chip level.

According to the present invention, after defining a region in which the redistribution is to be formed in the insulating layer and forming the redistribution in a buried type in the limited redistribution region, the adhesion of the redistribution with the insulating layer can be increased, and thus, the semiconductor The reliability of the package can be improved.

In addition, the present invention by forming a redistribution in the redistribution region in a buried type, it is possible to prevent the occurrence of undercut to the redistribution in the wet etching process for removing the seed layer portion is not formed plating layer, accordingly, cultivation Fine pitch design of lines can be implemented.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
2 is a plan view illustrating multi-layered interconnections of semiconductor packages according to an embodiment of the present invention.
3 to 8 are cross-sectional views of processes for describing a method of manufacturing a semiconductor package according to an embodiment of the present invention.
9 is a perspective view illustrating an electronic device having a semiconductor package according to the present invention.
10 is a system block diagram of an electronic device to which the semiconductor package according to the present invention is applied.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. 2 is a plan view illustrating multi-layered interconnections of a semiconductor package according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a semiconductor package according to an embodiment of the present invention includes a semiconductor chip 10, an insulating layer 40, a redistribution 50, and a capping layer 60.

The semiconductor chip 10 has an upper surface and a lower surface, and includes a bonding pad 20 disposed on the upper surface. In addition, although not shown, the semiconductor chip 10 includes a circuit portion formed therein. The circuit unit includes a circuit that operates by receiving external power and a signal, for example, a data storage unit for storing data, a data processing unit for processing data, and the like. The bonding pad 20 may be electrically connected to the circuit unit, and may be formed of aluminum (Al), copper (Cu), or the like.

The insulating layer 40 is formed on the semiconductor chip 10 including the bonding pads 20. In particular, the insulating layer 40 has a redistribution forming region 30 exposing the bonding pads 20. The insulating layer 40 is formed of, for example, a photosensitive polymer including at least one selected from the group consisting of polyimide, polybenzooxazole, benzocyclobutene, and the like. .

The redistribution forming region 30 is a first redistribution forming region 32, which is a region exposing the bonding pad 20, and a second redistribution forming region disposed outside the first redistribution forming region 32. It consists of 34. For example, a hole H exposing a bonding pad 20 is formed in the first redistribution formation region 32, and one end of the hole H is exposed in the second redistribution formation region 34. This is connected and the groove | channel T which has a line shape is formed.

The redistribution 50 is buried in the redistribution formation region 30 of the insulating layer 40, one end of which is electrically connected to the bonding pad 20 through a hole H. The opposite end D is electrically connected to an external connection terminal. The redistribution 50 includes a seed layer 44 formed on the surface of the redistribution formation region 30 and a plating layer 46 formed to fill the redistribution formation region 30 on the seed layer 44. do. Copper (Cu) is generally used as the seed layer 44 or the plating layer 46, and silver (Ag), gold (Au), nickel (Ni), palladium (Pd), platinum (Pt), or Alloys of these metals can be used.

The capping layer 60 is formed on the insulating layer 40 including the redistribution 50. In particular, the capping layer 60 is formed to expose the other end D of the redistribution line 50 serving as an external connection terminal.

As shown in FIG. 2, the redistribution line 50 may be arranged in multiple layers, for example, the first wiring 300 and the second wiring 400.

The first wire 300 includes one end connected to the first pad 320 and the other end connected to the external connection terminal, and is formed in a first insulating layer (not shown). In addition, a connection terminal, for example, a solder ball, for connecting to an external connection terminal may be disposed at the other end of the first wiring 300.

The second wiring 400 crossing the first wiring 300 is disposed. The second wiring 400 is buried in the second insulating layer 410 coated on the first insulating layer, and has one end connected to the second pad 420 and the other end connected to the external connection terminal. It may include. An external connection terminal, for example, a solder ball may be disposed at the other end of the second wiring 400. The second insulating layer 410 may include a cross region where the first wire 300 and the second wire 400 cross and a non-cross region except for the cross region. The first and second pads 320 and 420 may be disposed in or below the first insulating layer, but penetrate the first insulating layer. The first and second pads 320 and 420 may be a means for transmitting an input / output signal of the semiconductor chip 10.

As described above, the semiconductor package according to the embodiment of the present invention is formed buried in the redistribution forming region, unlike the conventional one in which the redistribution is formed on the insulating layer. Therefore, the redistribution in the present invention increases the adhesion to the insulating layer, and accordingly, the semiconductor package of the present invention has improved reliability.

In addition, the redistribution in the present invention does not generate an undercut during the wet etching process for removing the seed layer portion in which the plating layer is not formed, and thus, the present invention can implement a semiconductor package capable of fine pitch design of redistribution.

2 to 6 are cross-sectional views of processes for describing a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 2, an insulating layer 40 is coated on the top surface of the semiconductor chip 10 having a top surface and a bottom surface and a bonding pad 20 is formed on the top surface. Then, after the first exposure mask 100 is disposed on the insulating layer 40, the insulating layer 40 is first exposed.

Here, the semiconductor chip 10, although not shown, includes a circuit portion formed therein. The circuit unit includes a circuit that operates by receiving external power and a signal, for example, a data storage unit for storing data, a data processing unit for processing data, and the like. The bonding pad 20 may be electrically connected to the circuit unit, and may be formed of aluminum (Al), copper (Cu), or the like.

The insulating layer 40 is formed of, for example, a photosensitive polymer including at least one selected from the group consisting of polyimide, polybenzoxazole, benzocyclobutene, and the like. As the coating method of the insulating layer 40, any one of rotational coating using a spinner, spray coating using a spray coater, dipping, printing, and roll coating may be used.

The first exposure mask 100 has a first light transmitting region 102 exposing a portion of the insulating layer 40 on the bonding pad 20. Preferably, the first light-transmitting region 102 is provided in a hole shape. Accordingly, in the first exposure process using the first exposure mask 100, only a portion of the insulating layer 40 on the bonding pad 20 is exposed. In this case, the first exposure process is performed at an exposure amount for completely exposing a portion of the insulating layer 40 on the bonding pad 20.

Referring to FIG. 3, after the first exposure mask 100 is removed, the second exposure mask 200 having the second light-transmitting region 202 at a predetermined position is formed on the upper portion of the insulating layer 40. After disposing in the substrate, the insulating layer 40 on which the primary exposure has been performed is subjected to secondary exposure.

Here, the second light transmitting region 202 of the second exposure mask 200 is formed in a portion extending outwardly while being connected to the first light transmitting region 102. For example, the second light-transmitting region 202 is provided in a line shape, one end of which contacts the first light-transmitting region 102 of the first exposure mask 100 and extends outward.

On the other hand, in the secondary exposure, the focal length or the exposure energy is adjusted to be smaller than the exposure amount at the time of the first exposure, and preferably the exposure amount is about 1/2 or less, so that the insulating layer 40 Only partial thickness of the surface should be partially exposed.

Referring to FIG. 4, a developing process is performed on the insulating layer 40 exposed to the first and second exposures. In this case, a hole H exposing the bonding pad 20 is formed in a region where the first exposed insulating layer 40 is developed, and the hole is formed in a region where the second exposed insulating layer 40 is developed. A groove T having one end connected to (H) and having a line shape is formed, and as a result, the redistribution forming region 30 is defined in the insulating layer 40.

Here, in the present embodiment, as the insulating layer 40, a positive photosensitive polymer from which the photosensitive part is removed is used. However, the present invention is not limited thereto, and a negative photosensitive polymer may be used. to be.

Referring to FIG. 5, the seed layer 44 for electroplating is formed on the surface of the insulating layer 40 including the redistribution forming region 30 formed of the hole H and the groove T. Referring to FIG. Then, a photoresist pattern 48 is formed on the seed layer 44 to selectively expose the region where the plating layer is to be formed, that is, the redistribution forming region 30. Here, copper (Cu) is generally used as the seed layer 44, and silver (Ag), gold (Au), nickel (Ni), palladium (Pd), platinum (Pt), or a combination of these metals. Alloys can be used.

Subsequently, the redistribution forming region 30 is formed on the portion of the seed layer 44 exposed from the photoresist pattern 48, that is, the portion of the seed layer 44 of the redistribution forming region 30 by performing an electroplating process. The plating layer 46 is formed to a thickness that completely fills the holes H and the grooves T thereof. Here, copper (Cu) is generally used as the plating layer 46, and silver (Ag), gold (Au), nickel (Ni), palladium (Pd), platinum (Pt), or an alloy of these metals. This can be used.

Referring to FIG. 6, after the photoresist pattern 48 is removed, the portion of the seed layer 44 exposed by the photoresist pattern 48 is removed by wet etching, and the buried redistribution 50 according to the present invention is performed. To complete. At this time, since the redistribution 50 is buried in the redistribution formation region 30 of the insulating layer 40, undercut does not occur in the process of removing the seed layer 44.

Referring to FIG. 7, the capping layer 60 exposing the other end D of the redistribution line 50 facing one end connected to the bonding pad 20 on the insulating layer 40 including the redistribution line 50. ). Subsequently, although not shown, an external connection terminal such as a solder ball is attached to the other end D of the exposed redistribution 50 to complete the manufacture of the semiconductor package according to the present invention.

Meanwhile, the above-described process of forming the buried redistribution 50 of the present invention may be performed at the wafer level. In this case, the process of applying the insulating layer 40 at the wafer level to the buried redistribution ( After the process of forming 50), the wafer is sawed at the semiconductor chip level to complete the manufacture of the semiconductor package according to the embodiment of the present invention.

In the method for manufacturing a semiconductor package according to the embodiment of the present invention described above, by selectively exposing and developing the insulating layer applied on the semiconductor chip, forming a hole on the bonding pad of the semiconductor chip, while being connected to the hole And forming a line-shaped groove in a portion extending outwardly thereof, and then forming a redistribution line in the hole and the groove. Therefore, according to the method of manufacturing a semiconductor package of the present invention, by forming the redistribution lines in the holes and the grooves, the adhesiveness with the insulating layer of the redistribution lines can be increased, thereby improving the reliability of the semiconductor package. . In addition, in the method of manufacturing a semiconductor package of the present invention, by forming the redistribution in a buried type, it is possible to prevent the occurrence of undercut in the redistribution during the wet etching process for removing the seed layer portion where the plating layer is not formed. Fine pitch design is possible.

In addition, this invention can apply this invention also to all types of semiconductor packages which use redistribution.

The semiconductor package described above may be applied to various package modules.

8 is a perspective view illustrating an electronic device having a semiconductor package according to an embodiment of the present disclosure.

As illustrated, the multilayer semiconductor package according to an embodiment of the present invention may be applied to an electronic device 1000 such as a mobile phone. Since the semiconductor package according to the present exemplary embodiment is excellent in terms of size reduction and electrical characteristics, it is advantageous to reduce the thickness of the electronic device 1000 that simultaneously implements various functions.

The electronic device is not limited to the mobile phone shown in Fig. 8, but may be a portable electronic device, a laptop computer, a portable computer, a portable multimedia player (PMP), an MP3 player, a camcorder, a web tablet ), A wireless telephone, a navigation system, a personal digital assistant (PDA), and the like.

9 is a block diagram illustrating an example of an electronic device including a semiconductor package according to the present invention.

As shown, the electronic system 1300 may include a controller 1310, an input / output device 1320, and a memory device 1330. The controller 1310, the input / output device 1320, and the memory device 1330 may be coupled through a bus 1350.

The bus 1350 may be a path through which data flows. For example, the controller 1310 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing the same functions.

The controller 1310 and the memory device 1330 may include a semiconductor package according to the present invention. The input / output device 1320 may include at least one selected from a keypad, a keyboard, and a display device. The storage device 1330 is a device for storing data.

The storage device 1330 may store data and / or instructions that may be executed by the controller 1310. The storage device 1330 may include a volatile storage element and / or a non-volatile storage element. Alternatively, the storage device 1330 may be formed of a flash memory. For example, a flash memory to which the technique of the present invention is applied can be mounted on an information processing system such as a mobile device or a desktop computer. Such a flash memory may consist of a semiconductor disk device (SSD). In this case, the electronic system 1300 can stably store a large amount of data in the flash memory system.

The electronic system 1300 may further include an interface 1340 for transferring data to or receiving data from the communication network. The interface 1340 may be in a wired or wireless form. For example, the interface 1340 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1300 may be further provided with an application chip set, a camera image processor (CIS), and an input / output device. Self-explanatory to those who have learned.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited to the drawing.

10: semiconductor chip 20: bonding pad
30: rewiring forming area 40: insulating layer
44: seed layer 46: plating layer
48: photoresist pattern 50: rewiring
100: first exposure mask 102: first light transmission region
200: second exposure mask 202: second transmissive area

Claims (13)

A semiconductor chip having a bonding pad;
An insulating layer formed on the semiconductor chip including the bonding pad and having a redistribution formation region exposing the bonding pad; And
A buried redistribution line formed in the insulating layer of the redistribution formation region, one end of which is connected to the exposed bonding pads;
≪ / RTI > The method of claim 1,
The redistribution forming region may include a hole exposing the bonding pad and a line-shaped groove connected to the hole. The method of claim 1,
The insulating layer is a semiconductor package, characterized in that made of a photosensitive polymer. The method of claim 1,
The buried redistribution has a stacked structure of a seed layer and a plating layer formed on the surface of the redistribution formation region of the insulating layer. The method of claim 1,
And a capping layer formed on the buried redistribution and the insulating layer to expose a portion of the buried redistribution. Forming an insulating layer made of a photosensitive polymer on a semiconductor chip having a bonding pad;
Patterning the insulating layer to form a redistribution forming region exposing a bonding pad of the semiconductor chip; And
Forming a buried redistribution line in one end of which is connected to the exposed bonding pad;
Method of manufacturing a semiconductor package comprising a. The method according to claim 6,
Forming the redistribution forming region,
Performing primary exposure to the insulating layer such that a portion of the insulating layer disposed on the bonding pad is completely exposed;
Performing secondary exposure on the insulating layer on which the primary exposure has been performed so that the insulating layer portion connected to the primary exposed insulating layer portion is partially exposed; And
Developing the insulating layer such that the first and second exposed insulating layer portions are removed;
Method of manufacturing a semiconductor package comprising a. The method of claim 7, wherein
And the second exposure is performed at an exposure amount smaller than that of the first exposure. The method according to claim 6,
The redistribution forming region may include a hole exposing the bonding pad and a line-shaped groove connected to the hole. The method according to claim 6,
Forming the buried redistribution,
Forming a seed layer on a surface of the insulating layer having the redistribution forming region;
Forming a photoresist pattern on the seed layer that exposes the seed layer of the redistribution forming region;
Forming a plating layer to fill the redistribution forming region on the exposed seed layer portion; And
Removing the photoresist pattern and the seed layer portion thereunder;
Method of manufacturing a semiconductor package comprising a. The method according to claim 6,
After forming the buried redistribution,
And forming a capping layer on the buried redistribution and the insulating layer to expose a portion of the buried redistribution. The method of claim 1,
The forming of the insulating layer and the forming of the buried redistribution may be performed at a wafer level. 13. The method of claim 12,
And sawing at a chip level after forming the insulating layer at the wafer level or after forming the buried redistribution.
KR1020120075573A 2012-07-11 2012-07-11 Semiconductor package and method for manufacturing the same KR20140008173A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020120075573A KR20140008173A (en) 2012-07-11 2012-07-11 Semiconductor package and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120075573A KR20140008173A (en) 2012-07-11 2012-07-11 Semiconductor package and method for manufacturing the same

Publications (1)

Publication Number Publication Date
KR20140008173A true KR20140008173A (en) 2014-01-21

Family

ID=50142164

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020120075573A KR20140008173A (en) 2012-07-11 2012-07-11 Semiconductor package and method for manufacturing the same

Country Status (1)

Country Link
KR (1) KR20140008173A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9799619B2 (en) 2015-08-21 2017-10-24 Samsung Electronics Co., Ltd. Electronic device having a redistribution area
US10998266B2 (en) 2018-10-16 2021-05-04 SK Hynix Inc. Semiconductor devices including redistributed layer structures and methods of forming semiconductor devices including redistributed layer structures

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9799619B2 (en) 2015-08-21 2017-10-24 Samsung Electronics Co., Ltd. Electronic device having a redistribution area
US10998266B2 (en) 2018-10-16 2021-05-04 SK Hynix Inc. Semiconductor devices including redistributed layer structures and methods of forming semiconductor devices including redistributed layer structures

Similar Documents

Publication Publication Date Title
US11443970B2 (en) Methods of forming a package substrate
US10325882B2 (en) Method of manufacturing semiconductor package
CN104851842B (en) Semiconductor devices including embedded surface installing device and forming method thereof
KR101789765B1 (en) Semiconductor device and method of forming the same
KR20120016925A (en) Semiconductor package and method for manufacturing the same
CN105679681A (en) Integrated circuit package pad and methods of forming same
JP2016533651A (en) Method of embedding WLCSP components in e-WLB and e-PLB
CN104218024A (en) Bridge interconnection with layered interconnect structures
JPWO2007066409A1 (en) Semiconductor device and manufacturing method thereof
US10448508B2 (en) Printed circuit board and semiconductor package including the same
US20200266149A1 (en) Galvanic corrosion protection for semiconductor packages
US20150228594A1 (en) Via under the interconnect structures for semiconductor devices
JP2018523919A (en) Package on package (POP) structure with multiple dies
US10602621B1 (en) Method of manufacturing circuit board
US7906377B2 (en) Fabrication method of circuit board
US20070111499A1 (en) Wafer redistribution structure with metallic pillar and method for fabricating the same
JP7301919B2 (en) Circuit board with constrained solder interconnect pads
US9040419B2 (en) Semiconductor package and method for manufacturing the same
US20120056320A1 (en) Semiconductor device and manufacturing method of semiconductor device
CN101587842A (en) Chip packaging support plate and manufacture method thereof
KR20140008173A (en) Semiconductor package and method for manufacturing the same
TWI669034B (en) Printed circuit board structure and method of forming the same
CN104584206A (en) Solder on trace technology for interconnect attachment
KR20140028642A (en) Semiconductor chip and manufacturing method of the same
JP2010157544A (en) Semiconductor device, method of manufacturing the same, and electronic apparatus

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination