KR20130115875A - Solar cell and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A solar cell and a method for manufacturing the same are provided to prevent the change of the characteristic of a thin film by separating the edge of a semiconductor wafer. CONSTITUTION: A semiconductor layer is formed on the upper surface of a semiconductor wafer. The upper surface of the semiconductor wafer includes a separation groove line. A first electrode (400) is formed on the semiconductor layer. A second semiconductor layer is formed on the lower surface of the semiconductor wafer. A second electrode (700) is formed on the second semiconductor layer.

Description

Solar cell and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell, and more particularly, to a solar cell in which a substrate type solar cell and a thin film type solar cell are combined.

Solar cells are devices that convert light energy into electrical energy using the properties of semiconductors.

The solar cell has a PN junction structure in which a P (positive) type semiconductor and an N (negative) type semiconductor are bonded to each other.

When sunlight is incident on the solar cell of the structure, holes and electrons are generated in the semiconductor by energy of the incident sunlight, and at this time, the holes are generated by the electric field generated by the PN junction. (+) Is moved toward the P-type semiconductor and the electron (-) is moved to the N-type semiconductor to generate a potential to generate power.

Such a solar cell generally can be classified into a substrate type solar cell and a thin film type solar cell.

The substrate type solar cell is a solar cell manufactured using a semiconductor material such as silicon as a substrate, and the thin film type solar cell is a solar cell manufactured by forming a semiconductor in the form of a thin film on a substrate such as glass.

The substrate-type solar cell has an advantage that the efficiency is somewhat superior to the thin-film solar cell, the thin-film solar cell has the advantage that the manufacturing cost is reduced compared to the substrate-type solar cell.

Thus, a solar cell combining the substrate type solar cell and the thin film type solar cell has been proposed. Hereinafter, a conventional solar cell will be described with reference to the drawings.

1 is a cross-sectional view schematically showing a conventional solar cell combining a substrate type solar cell and a thin film type solar cell, and FIG. 2 is a perspective view schematically showing the solar cell shown in FIG. 1.

As can be seen in FIGS. 1 and 2, a conventional solar cell includes a semiconductor wafer 10, a first semiconductor layer 20, a first electrode 40, a second semiconductor layer 50, and a second electrode ( 70).

The first semiconductor layer 20 is formed in the form of a thin film on the upper surface of the remaining region except for the upper edge portion EA of the semiconductor wafer 10. The first semiconductor layer 20 may include the upper edge portion EA of the semiconductor wafer 10 by a deposition process using a mask (not shown) that covers the upper edge portion EA of the semiconductor wafer 10. It is formed on the upper surface of the remaining area.

The second semiconductor layer 50 is formed in the form of a thin film on the upper surface of the remaining region except for the edge of the lower surface of the semiconductor wafer 10. The second semiconductor layer 50 is formed by removing a lower edge EA of the semiconductor wafer 10 by a deposition process using a mask (not shown) covering the lower edge EA of the semiconductor wafer 10. It is formed on the upper surface of the remaining area.

The PN junction structure is formed by the combination of the semiconductor wafer 10, the first semiconductor layer 20, and the second semiconductor layer 50.

The reason why the first and second semiconductor layers 20 and 50 are formed by a deposition process using a mask is that each of the first and second semiconductor layers 20 and 50 has a semiconductor wafer 10 in view of process characteristics. In order to prevent such a short because it may extend along the side of the contact and may come in contact with each other.

The first electrode 40 is formed on the first semiconductor layer 20, and the second electrode 70 is formed on the second semiconductor layer 50, respectively, a positive electrode of the solar cell. Or (-) electrode.

When solar light is incident on the solar cell according to the related art, a carrier such as a hole or an electron is generated in the semiconductor wafer 10, and the generated carrier is the first carrier. The first electrode 40 is moved through the semiconductor layer 20, and the second electrode 70 is moved through the second semiconductor layer 50.

However, such a conventional solar cell is a portion corresponding to the mask because the first and second semiconductor layers 20 and 50 are formed after masking the edge portion EA of the semiconductor wafer 10 through a mask. As a result, a dead zone in which no photoelectric conversion is performed is formed at the edge of the semiconductor wafer 10, thereby degrading the photoelectric conversion efficiency.

In addition, the conventional solar cell has a disadvantage in that the film quality of each of the first and second semiconductor layers 20 and 50 formed in the region adjacent to the mask is not uniform due to the mask.

Disclosure of Invention The present invention has been made in view of the above-described problems, and a technical problem is to provide a solar cell and a method of manufacturing the same, which can improve photoelectric conversion efficiency.

A solar cell according to the present invention for achieving the above technical problem is a semiconductor wafer: a first semiconductor layer formed on the upper surface of the semiconductor wafer; A first electrode formed on the first semiconductor layer; A second semiconductor layer formed on the bottom surface of the semiconductor wafer; And a second electrode formed on the second semiconductor layer, wherein an upper surface of the semiconductor wafer includes a separation groove line on which the first semiconductor layer is formed.

The lower side surface of the semiconductor wafer is characterized in that the separation groove line is formed in which the second semiconductor layer is formed.

A portion of the side surface of the semiconductor wafer is exposed to the outside to electrically separate the first and second semiconductor layers formed in the separation groove line.

According to another aspect of the present invention, there is provided a solar cell including: a semiconductor wafer having an upper inclined surface that is inclined at an upper edge portion of each side; a first semiconductor layer formed on an upper surface of the semiconductor wafer and the upper inclined surface; A first electrode formed on the first semiconductor layer; A second semiconductor layer formed on the bottom surface of the semiconductor wafer; And a second electrode formed on the second semiconductor layer.

The semiconductor wafer further has a lower inclined surface formed to be inclined at lower edge portions of each side, and the second semiconductor layer is formed on the lower surface and the lower inclined surface of the semiconductor wafer.

The solar cell further includes a first conductive layer formed on an upper surface of the first semiconductor layer and a second conductive layer formed on a lower surface of the second semiconductor layer, wherein the first electrode is formed on an upper surface of the first conductive layer. And the second electrode is formed on an upper surface of the second conductive layer.

The solar cell is characterized in that an intrinsic semiconductor layer is further formed between at least one of the semiconductor wafer and the first semiconductor layer and between the semiconductor wafer and the second semiconductor layer.

The solar cell includes at least one semiconductor layer of the first semiconductor layer and the second semiconductor layer including a lightly doped semiconductor layer on the semiconductor wafer and a heavily doped semiconductor layer formed on the lightly doped semiconductor layer. It is characterized by.

According to an aspect of the present invention, there is provided a method of manufacturing a solar cell, the method including: forming a separation groove line at an edge portion of a semiconductor wafer; Forming a first semiconductor layer on an upper surface of the semiconductor wafer including the separation groove line, and forming a second semiconductor layer on the lower surface of the semiconductor wafer; Forming a first electrode on the first semiconductor layer, and forming a second electrode on the second semiconductor layer; And separating the edge portion of the semiconductor wafer from the semiconductor wafer by using the separation groove line.

The depth of the separation groove line is characterized in that 1/2 ~ 3/4 of the thickness of the semiconductor wafer.

The distance between the separation groove line and the side surface of the semiconductor wafer is characterized in that 1 ~ 2mm.

According to another aspect of the present invention, there is provided a method of manufacturing a solar cell, including: forming an upper separation groove line on an upper edge portion of a semiconductor wafer and forming a lower separation groove line on a lower edge portion of the semiconductor wafer; Forming a first semiconductor layer on an upper surface of the semiconductor wafer including the upper separation groove line, and forming a second semiconductor layer on a lower surface of the semiconductor wafer including the lower separation groove line; Forming a first electrode on the first semiconductor layer, and forming a second electrode on the second semiconductor layer; And separating the edge portion of the semiconductor wafer from the semiconductor wafer by using the upper and lower separation groove lines.

The upper separation groove line and the lower separation groove line may be overlapped with each other or staggered from each other.

The upper separation groove line and the lower separation groove line may be spaced apart by a distance of 1 to 2 mm from the side surface of the semiconductor wafer.

The separation groove line is formed to a predetermined depth so as to have a "V" shaped cross section by the laser.

In the process of separating the edge portion of the semiconductor wafer, the edge portion of the semiconductor wafer may be separated by vacuum suction or pressurization of the edge portion of the semiconductor wafer.

The method of manufacturing the solar cell may include forming a first conductive layer on an upper surface of the first semiconductor layer; And forming a second conductive layer on a lower surface of the second semiconductor layer, wherein the first electrode is formed on an upper surface of the first conductive layer, and the second electrode is an upper surface of the second conductive layer. Characterized in that formed.

The manufacturing method of the solar cell further comprises the step of forming an intrinsic semiconductor layer between at least one of the semiconductor wafer and the first semiconductor layer and between the semiconductor wafer and the second semiconductor layer.

The forming of at least one semiconductor layer of the first semiconductor layer and the second semiconductor layer may include forming a lightly doped semiconductor layer on the semiconductor wafer; And forming a highly doped semiconductor layer on the lightly doped semiconductor layer.

According to the solution of the said subject, the solar cell which concerns on this invention, and its manufacturing method have the following effects.

First, since the dead zone is not formed in the edge portion of the semiconductor wafer having a standard area, the photoelectric conversion efficiency of the solar cell can be improved.

Second, since the photoelectric conversion layer is formed on the upper side of the semiconductor wafer and a part of the separation groove line, the photoelectric conversion efficiency of the solar cell can be improved.

Third, the photoelectric conversion layer is formed on the upper and upper separation groove lines of the semiconductor wafer, and the photoelectric conversion layer is formed on the lower part and the lower separation groove line of the semiconductor wafer, thereby improving the photoelectric conversion efficiency of the solar cell. .

Fourth, the characteristic change of the thin film due to the process of separating the upper and lower surfaces of the solar cell by forming a separation groove line on the semiconductor wafer prior to thin film deposition and separating the edge portion of the semiconductor wafer through the physical separation process using the same. Can be prevented.

1 is a cross-sectional view schematically showing a conventional solar cell combining a substrate type solar cell and a thin film type solar cell.
FIG. 2 is a perspective view schematically showing the solar cell shown in FIG. 1.
3 is a schematic cross-sectional view of a solar cell according to a first embodiment of the present invention.
4 is a schematic cross-sectional view of a solar cell according to a second embodiment of the present invention.
5 is a schematic cross-sectional view of a solar cell according to a third embodiment of the present invention.
6 is a schematic cross-sectional view of a solar cell according to a fourth embodiment of the present invention.
7 is a schematic cross-sectional view of a solar cell according to a fifth embodiment of the present invention.
8A to 8F are cross-sectional views schematically illustrating a method of manufacturing a solar cell according to a first embodiment of the present invention.
9A to 9J are cross-sectional views schematically illustrating a method of manufacturing a solar cell according to a second embodiment of the present invention.
FIG. 10 is a cross-sectional view illustrating an embodiment of the physical separation process illustrated in FIG. 9J.
FIG. 11 is a cross-sectional view illustrating another embodiment of the physical separation process illustrated in FIG. 9J.
12A to 12H are cross-sectional views schematically illustrating a method of manufacturing a solar cell according to a third embodiment of the present invention.
13A to 13F are cross-sectional views schematically illustrating a method of manufacturing a solar cell according to a fourth embodiment of the present invention.
14A to 14F are cross-sectional views schematically illustrating a method of manufacturing a solar cell according to a fifth embodiment of the present invention.
15A to 15C are cross-sectional views schematically illustrating a method of manufacturing a solar cell according to a sixth embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic cross-sectional view of a solar cell according to a first embodiment of the present invention.

As can be seen in Figure 3, the solar cell according to the first embodiment of the present invention, the semiconductor wafer 100, the first semiconductor layer 200, the first electrode 400, the second semiconductor layer 500, and It comprises a second electrode 700.

The semiconductor wafer 100 has a predetermined electrically conductive polarity and may be formed of a silicon wafer. Specifically, the semiconductor wafer 100 may be made of an N-type silicon wafer or a P-type silicon wafer. The semiconductor wafer 100 has the same electrically conductive polarity as any one of the first semiconductor layer 200 and the second semiconductor layer 500.

The upper surface 102 and the lower surface 104 of the semiconductor wafer 100 may be formed in an uneven structure, but is not necessarily limited thereto. In the present specification, the upper surface 102 of the semiconductor wafer 100 refers to a surface on which sunlight directly enters, and the lower surface 104 of the semiconductor wafer 100 refers to a surface on which the sunlight does not directly enter.

The semiconductor wafer 100 has an inclined surface 106 provided at an upper edge portion of each side to have a predetermined slope. Here, the present invention is a basic process prior to the process of forming a thin film on the semiconductor wafer 100, the separation groove line forming process for forming a separation groove line of a predetermined depth along the upper edge portion of the semiconductor wafer 100 first After performing, a thin film for solar cells is formed on each of the top surface 102 and the bottom surface 104 of the semiconductor wafer 100 including the separation groove line, and then along the separation groove line through a physical separation (or cutting) process. The solar cell is completed by removing the edge portion of the semiconductor wafer 100.

The separation groove line forming process may be performed using a cutting wheel, a needle, or a laser. Accordingly, the inclined surface 106 is a part, that is, an inner part, of the separation groove line remaining in the upper edge portion of each side of the semiconductor wafer 100 even after the physical separation process.

The first semiconductor layer 200 is formed in the form of a thin film on the upper surface (or one surface) 102 and the inclined surface 106 of the semiconductor wafer 100. That is, the first semiconductor layer 200 may be formed by a plasma enhanced chemical vapor deposition (PECVD) process. Accordingly, the first semiconductor layer 200 extends to be electrically connected not only to the upper surface of the semiconductor wafer 100 but also to the inclined surface 106 of the semiconductor wafer 100 along its side in view of process characteristics.

The first semiconductor layer 200 may form a PN junction with the semiconductor wafer 100. Therefore, when the semiconductor wafer 100 is made of an N-type silicon wafer, the first semiconductor layer 200 may be made of a P-type semiconductor layer. In particular, the first semiconductor layer 200 may be made of P-type amorphous silicon doped with a Group III element such as boron (B).

In general, since the drift mobility of holes is lower than the drift mobility of electrons, in order to maximize the efficiency of collecting holes due to incident light, it is preferable to form a P-type semiconductor layer close to the light receiving surface. It is preferable that the first semiconductor layer 200 close to the surface is made of a P-type semiconductor layer.

The first electrode 400 is formed on the upper surface of the first semiconductor layer 200 to form a front surface of the solar cell. Therefore, the first electrode 400 is preferably formed in a pattern form so that solar light can be transmitted into the solar cell.

The first electrode 400 includes Ag, Al, Ag + Al, Ag + Mg, Ag + Mn, Ag + Sb, Ag + Zn, Ag + Mo, Ag + Ni, Ag + Cu, Ag + Al + Zn, or the like. The same conductivity may be made of a metal material. The first electrode 400 may be formed by a sputtering process using a mask or a metal organic chemical vapor deposition (MOCVD) process, or may be formed in a pattern form by a printing process.

The second semiconductor layer 500 is formed in the form of a thin film on the lower surface (or the other surface) of the semiconductor wafer 100. That is, the second semiconductor layer 500 may be formed by a plasma enhanced chemical vapor deposition (PECVD) process. Accordingly, the second semiconductor layer 500 is formed to extend to be electrically connected to not only the bottom surface of the semiconductor wafer 100 but also side portions of the semiconductor wafer 100 along the side surface thereof. However, the second semiconductor layer 500 formed on the side surface of the semiconductor wafer 100 is removed by the above-described physical separation process and remains only on the bottom surface of the semiconductor wafer 100.

The second semiconductor layer 500 may be formed to have a different electrical conduction polarity than the first semiconductor layer 200. That is, when the first semiconductor layer 200 is formed of a P-type semiconductor layer doped with a Group III element such as boron (B), the second semiconductor layer 500 is a Group 5 element such as phosphorus (P). It is made of a doped N-type semiconductor layer. In particular, the second semiconductor layer 500 may be made of N-type amorphous silicon.

The second electrode 700 is formed on the second semiconductor layer 500. Since the second electrode 700 is formed on the lower surface of the solar cell, the second electrode 700 may be formed on the entire upper surface of the second semiconductor layer 500. However, the second electrode 700 may also be formed in a pattern form so that the reflected sunlight may be incident on the bottom surface of the solar cell.

The second electrode 700 is formed by the same process as the first electrode 400, Ag, Al, Ag + Al, Ag + Mg, Ag + Mn, Ag + Sb, Ag + Zn, Ag + It may be made of a metal material such as Mo, Ag + Ni, Ag + Cu, Ag + Al + Zn.

As described above, in the solar cell according to the first embodiment of the present invention, since the photoelectric conversion layer, that is, the first semiconductor layer 200 is formed on the upper surface of the semiconductor wafer 100, the photoelectric conversion efficiency of the solar cell may be improved. Can be.

In addition, the solar cell according to the first embodiment of the present invention can improve the photoelectric conversion efficiency of the solar cell because the dead zone is not formed in the edge portion of the semiconductor wafer 100 having a standard area.

4 is a schematic cross-sectional view of a solar cell according to a second embodiment of the present invention.

As can be seen in Figure 4, the solar cell according to the second embodiment of the present invention, the semiconductor wafer 100, the first semiconductor layer 200, the first conductive layer 300, the first electrode 400, And a second semiconductor layer 500, a second conductive layer 600, and a second electrode 700.

The solar cell of the second embodiment is the same as the solar cell according to the first embodiment shown in FIG. 3 except that the first and second conductive layers 300 and 600 are further formed. Therefore, the same reference numerals are assigned to the same components, and repeated descriptions of the same components will be omitted.

The first and second conductive layers 300 and 600 may improve mobility of carriers such as holes or electrons generated in the semiconductor wafer 100 to the first electrode 400 or the second electrode 700. .

The first conductive layer 300 collects carriers, eg, holes, generated in the semiconductor wafer 100 and moves the collected carriers to the first electrode 400.

The first conductive layer 300 may be made of a transparent conductive material such as indium tin oxide (ITO), ZnOH, ZnO: B, ZnO: Al, SnO ₂ , SnO ₂ : F, or the like.

The first conductive layer 300 may be formed by a sputtering process or a metal organic chemical vapor deposition (MOCVD) process. Accordingly, the first conductive layer 300 may be formed to extend not only on the upper surface of the first semiconductor layer 200 but also on the side surface of the semiconductor wafer 100 along the side surface thereof. In this case, the first conductive layer 300 may be formed in a region corresponding to a part of the side surface or the entire side surface of the semiconductor wafer 100.

The first electrode 400 is formed on an upper surface of the first conductive layer 300 to form a front surface of the solar cell, and is formed in a pattern form in a predetermined form.

The second conductive layer 600 collects carriers, eg, electrons, generated in the semiconductor wafer 100 and moves the collected carriers to the second electrode 700.

The second conductive layer 600 may be made of a transparent conductive material such as indium tin oxide (ITO), ZnOH, ZnO: B, ZnO: Al, SnO ₂ , SnO ₂ : F, or the like. The second conductive layer 600 may be formed by a sputtering process or a metal organic chemical vapor deposition (MOCVD) process. Accordingly, the second conductive layer 600 may be formed to extend not only to the bottom surface of the second semiconductor layer 500 but also to side portions of the semiconductor wafer 100 along the side surface thereof. However, the second conductive layer 600 formed on the side surface of the semiconductor wafer 100 is removed by the above-described physical separation process so that only the bottom surface of the second semiconductor layer 500 remains.

The second electrode 700 is formed on the second conductive layer 600. Since the second electrode 700 is formed on the bottom surface of the solar cell, the second electrode 700 may be formed in the entire upper surface area of the second conductive layer 600 or may be formed in a pattern form.

As described above, in the solar cell according to the second embodiment of the present invention, the photoelectric conversion region, that is, the first semiconductor layer 200 is formed on a portion of the upper surface and the separation groove line of the semiconductor wafer 100, The mobility of the carrier is improved by the second conductive layers 300 and 600, thereby improving the photoelectric conversion efficiency of the solar cell.

FIG. 5 is a schematic cross-sectional view of a solar cell according to a third exemplary embodiment of the present invention, in which a first intrinsic semiconductor layer 150 is additionally formed between the semiconductor wafer 100 and the first semiconductor layer 200. It is the same as the solar cell according to the second embodiment shown in FIG. 4 except that the second intrinsic semiconductor layer 450 is further formed between the semiconductor wafer 100 and the second semiconductor layer 500. Therefore, the same reference numerals are assigned to the same components, and repeated descriptions of the same components will be omitted.

When the first semiconductor layer 200 or the second semiconductor layer 500 is formed on the surface of the semiconductor wafer 100 by using a high concentration of dopant gas, the surface of the semiconductor wafer 100 is formed by the high concentration of dopant gas. Defects may occur.

Therefore, in the third embodiment of the present invention illustrated in FIG. 5, after the first intrinsic semiconductor layer 150 is formed on the upper surface of the semiconductor wafer 100, the first intrinsic semiconductor layer 150 is formed on the first intrinsic semiconductor layer 150. The semiconductor layer 200 is formed to prevent defects from occurring on the upper surface of the semiconductor wafer 100. In addition, after the second intrinsic semiconductor layer 450 is formed on the bottom surface of the semiconductor wafer 100, the second semiconductor layer 500 is formed on the second intrinsic semiconductor layer 450 to thereby form the semiconductor wafer 100. ) Is to prevent the occurrence of defects.

Meanwhile, although FIG. 5 illustrates a state in which both the first intrinsic semiconductor layer 150 and the second intrinsic semiconductor layer 450 are formed, any one of the first intrinsic semiconductor layer 150 and the second intrinsic semiconductor layer 450 is shown. It is also possible to form only intrinsic semiconductor layers.

On the other hand, although FIG. 5 shows a state in which both the first conductive layer 300 and the second conductive layer 600 are formed, the first conductive layer 300 and the second conductive layer 600 are described with reference to FIG. 3. It may be omitted, such as the solar cell shown.

6 is a schematic cross-sectional view of a solar cell according to a fourth exemplary embodiment of the present invention, which is illustrated in FIG. 4 except that the structures of the first semiconductor layer 200 and the second semiconductor layer 500 are changed. The same as the solar cell according to the second embodiment. Therefore, the same reference numerals are assigned to the same components, and repeated descriptions of the same components will be omitted.

As can be seen in FIG. 6, according to the fourth embodiment of the present invention, the first semiconductor layer 200 is a lightly doped first semiconductor layer 200a and the lightly doped low concentration formed on the upper surface of the semiconductor wafer 100. And a heavily doped first semiconductor layer 200b formed on the first semiconductor layer 200a.

In addition, the second semiconductor layer 500 is a lightly doped second semiconductor layer 500a formed on the bottom surface of the semiconductor wafer 100 and a heavily doped second semiconductor layer 500a. It may be made of two semiconductor layers (500b).

In the present specification, low concentration and high concentration are relative concepts, and the low concentration doped first semiconductor layer 200a means that the concentration of the dopant is relatively smaller than that of the high concentration doped first semiconductor layer 200b.

The lightly doped first semiconductor layer 200a and the lightly doped second semiconductor layer 500a are respectively the first intrinsic semiconductor layer 150 and the second intrinsic in the second embodiment shown in FIG. It may play a role similar to that of the semiconductor layer 450.

That is, by first forming a low concentration doped first semiconductor layer 200a on the upper surface of the semiconductor wafer 100, and then forming the high concentration doped first semiconductor layer 200b, the semiconductor wafer 100 may be formed. Defects may be prevented from occurring on the upper surface of the semiconductor wafer, and a second lightly doped second semiconductor layer 500a may be first formed on the bottom surface of the semiconductor wafer 100, and then the second heavily doped second semiconductor layer ( By forming 500b), occurrence of defects on the lower surface of the semiconductor wafer 100 can be prevented.

Therefore, the dopant concentrations of the lightly doped first semiconductor layer 200a and the lightly doped second semiconductor layer 500a may be controlled to prevent defects on the surface of the semiconductor wafer 100.

The solar cell according to the fourth exemplary embodiment of the present invention illustrated in FIG. 6 has an advantage of superior productivity compared to the solar cell according to the third exemplary embodiment of the present invention illustrated in FIG. 5 described above.

That is, in the solar cell according to the third embodiment of the present invention illustrated in FIG. 5 described above, deposition equipment is added and the process is complicated to form the first intrinsic semiconductor layer 150 and the second intrinsic semiconductor layer 450. Although the productivity may decrease, the solar cell according to the fourth exemplary embodiment of the present invention shown in FIG. 6 includes a chamber containing the lightly doped first semiconductor layer 200a and the heavily doped first semiconductor layer 200b in one chamber. It can be carried out by an extension process in the inside, and also separately deposited because the lightly doped second semiconductor layer 500a and the heavily doped second semiconductor layer 500b can be performed in an extension process in one chamber. The advantage is that no equipment or process is added.

Meanwhile, in FIG. 6, the first semiconductor layer 200 includes a lightly doped first semiconductor layer 200a and a heavily doped first semiconductor layer 200b, and the second semiconductor layer 500 is lightly doped. Although the second semiconductor layer 500a and the heavily doped second semiconductor layer 500b are illustrated, only one of the semiconductor layers may be formed of a lightly doped semiconductor layer and a heavily doped semiconductor layer.

On the other hand, although FIG. 6 illustrates a state in which both the first conductive layer 300 and the second conductive layer 600 are formed, the first conductive layer 300 and the second conductive layer 600 are described with reference to FIG. 3. It may be omitted, such as the solar cell shown.

FIG. 7 is a schematic cross-sectional view of a solar cell according to a fifth exemplary embodiment of the present invention, wherein the semiconductor wafer 100 includes an upper inclined surface 106 provided at an upper corner of each side and a lower inclined surface provided at a lower edge of each side ( A solar cell according to the second exemplary embodiment shown in FIG. 4 described above is identical except that it has a portion 108). Therefore, the same reference numerals are assigned to the same components, and repeated descriptions of the same components will be omitted.

First, the present invention is a basic process prior to the process of forming a thin film on the semiconductor wafer 100, the separation forming the upper and lower surface separation groove line of a predetermined depth along each of the upper and rear edge portions of the semiconductor wafer 100 After performing the groove line forming process, a thin film for solar cells is formed on each of the upper surface 102 and the lower surface 104 of the semiconductor wafer 100 including the upper and lower surface separating groove lines, and then the upper surface is formed through a physical separation process. And removing the edge portion of the semiconductor wafer 100 along the lower isolation line.

The separation groove line forming process may be performed using a cutting wheel, a needle, or a laser. Accordingly, the upper inclined surface 106 is a portion, that is, an inner portion, of the upper isolation groove line remaining in the upper corner portion of each side of the semiconductor wafer 100 even after the physical separation process.

The first semiconductor layer 200 formed on the upper surface of the semiconductor wafer 100 including the upper inclined surface 106 has a process characteristic of not only the upper surface of the semiconductor wafer 100 but also the side surface of the semiconductor wafer 100. It extends to be electrically connected to the upper inclined surface 106. In addition, the first conductive layer 300 formed on the first semiconductor layer 200 also has an upper inclined surface 106 of the semiconductor wafer 100 along the side surface thereof as well as the top surface of the first semiconductor layer 200 due to process characteristics. E) is extended to be electrically connected.

In addition, the lower inclined surface 108 is a portion, that is, an inner portion, of the lower surface separation groove line remaining on the lower edge portion of each side of the semiconductor wafer 100 even after the physical separation process. The second semiconductor layer 500 formed on the bottom surface of the semiconductor wafer 100 including the lower inclined surface 108 may have the semiconductor wafer 100 along the side surface thereof as well as the bottom surface of the semiconductor wafer 100 due to process characteristics. It extends to be electrically connected to the lower inclined surface 108 of the.

In addition, the second conductive layer 600 formed on the second semiconductor layer 500 also has a lower inclined surface 108 of the semiconductor wafer 100 along its side as well as an upper surface of the second semiconductor layer 500 due to process characteristics. E) is extended to be electrically connected. In this case, a part of each side surface of the semiconductor wafer 100 is exposed to the outside to electrically separate the first and second semiconductor layers 200 and 500 formed on the upper and lower inclined surfaces of the semiconductor wafer 100.

Meanwhile, the solar cell according to the fifth embodiment of the present invention is formed between the semiconductor wafer 100 and the first semiconductor layer 200 in the same manner as the solar cell according to the third embodiment shown in FIG. 5 described above. The first intrinsic semiconductor layer 150 may be further formed, and the second intrinsic semiconductor layer 450 may be further formed between the semiconductor wafer 100 and the second semiconductor layer 500.

On the other hand, the solar cell according to the fifth embodiment of the present invention, like the solar cell according to the fourth embodiment shown in FIG. 6 described above, the first semiconductor layer 200 and the second semiconductor layer 500 The structure of may be changed. That is, the first semiconductor layer 200 is a lightly doped first semiconductor layer 200a formed on the upper surface of the semiconductor wafer 100 and a heavily doped first semiconductor layer 200a formed on the lightly doped first semiconductor layer 200a. It consists of 1 semiconductor layer 200b. In addition, the second semiconductor layer 500 is a lightly doped second semiconductor layer 500a formed on the bottom surface of the semiconductor wafer 100 and a heavily doped second semiconductor layer 500a. It may be made of two semiconductor layers (500b).

In addition, although FIG. 7 illustrates a state in which both the first conductive layer 300 and the second conductive layer 600 are formed, the first conductive layer 300 and the second conductive layer 600 are described with reference to FIG. 3. It may be omitted, such as the solar cell shown in.

8A to 8D are cross-sectional views schematically illustrating a method of manufacturing a solar cell according to a first embodiment of the present invention, which relates to the method of manufacturing the solar cell according to the first embodiment shown in FIG. will be.

First, as shown in FIG. 8A, a separation groove line 110 having a predetermined depth is formed on an upper edge portion of the semiconductor wafer 100 having a predetermined electrical polarity.

The semiconductor wafer 100 may be an N-type silicon wafer. In addition, the upper surface 102 and the lower surface 104 of the semiconductor wafer 100 may be formed in an uneven structure, but is not necessarily limited thereto.

The separation groove line 110 is formed to have a predetermined depth from an upper surface of the semiconductor wafer 100, and may have a cross section having a “V” shape. At this time, the center depth D of the separation groove line 110 from the upper surface of the semiconductor wafer 100 may be set in a range of 1/2 to 3/4 of the thickness of the semiconductor wafer 100.

When the center depth D of the separation groove line 110 is less than 1/2 of the thickness of the semiconductor wafer 100, it is difficult to remove the edge portion of the semiconductor wafer 100 during the physical separation process to be described later. On the other hand, when the center depth D of the separation groove line 110 is 3/4 or more of the thickness of the semiconductor wafer 100, the edge portion of the semiconductor wafer 100 may be easily removed during the thin film deposition process.

In addition, the distance L between the center of the separation groove line 110 and the side surface of the semiconductor wafer 100 may be set in the range of 1 to 2 mm. At this time, when the distance (L) between the center of the separation groove line 110 and the side surface of the semiconductor wafer 100 is 1mm or less, it is difficult to remove the edge portion of the semiconductor wafer 100 during the physical separation process to be described later. have. On the other hand, when the distance L between the center of the separation groove line 110 and the side surface of the semiconductor wafer 100 is 2 mm or more, the edge of the semiconductor wafer 100 removed by the physical separation process to be described later will be described. The area is increased to lower the photoelectric conversion efficiency of the solar cell.

Meanwhile, the area of the semiconductor substrate 100 has an area larger than the standard area by the area of the edge portion of the semiconductor wafer 100 to be removed along the separation groove line 110. That is, since the semiconductor substrate 100 is manufactured by cutting ingots having a predetermined size, the semiconductor substrate 100 is cut by reflecting the area of the edge portion of the semiconductor wafer 100 in the ingot cutting process. The semiconductor wafer 100 has an area larger than that of the edge portion of the semiconductor wafer 100.

The above-described separation groove line 110 may be formed by a separation groove line forming process using a cutting wheel, a needle, or a laser. Here, when the separation groove line 110 is formed by a laser, the laser 120 may be an infrared (IR) laser having a wavelength in the range of 1060 ± 10 nm and a frequency in the range of several tens of GHz. Can be.

After the above-described process of forming the separation groove line 110, a wet cleaning process of cleaning the semiconductor wafer 100 including the separation groove line 110 is performed. The wet cleaning process may include a first cleaning process using a SC (Standard Cleaning) 1 cleaning solution developed by the US RCA, and a second cleaning process using a SC2 cleaning solution.

The primary cleaning process removes particles generated by the separation groove line forming process according to the SC1 cleaning liquid in which ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and water (H ₂ O) are mixed at a predetermined ratio. do.

The secondary cleaning process is a transition metal contaminant produced by a separation groove line forming process according to an SC2 cleaning liquid in which hydrochloric acid (HCl)), hydrogen peroxide solution (H ₂ O ₂ ), and water (H ₂ O) are mixed at a predetermined ratio. Remove it.

Then, as shown in FIG. 8B, the first semiconductor layer 200 is formed on the upper surface of the semiconductor wafer 100 including the separation groove line 110.

In the process of forming the first semiconductor layer 200, a P-type semiconductor layer, for example, a P-type amorphous silicon layer, is formed on the upper surface of the semiconductor wafer 100 by using a plasma enhanced chemical vapor deposition (PECVD) process. It can be done in a process. Accordingly, the first semiconductor layer 200 is formed not only on the top surface of the semiconductor wafer 100 and the inclined surface inside the separation groove line 110 but also on the top surface portion of the semiconductor wafer 100 due to process characteristics.

Next, as shown in FIG. 8C, a first electrode 400 is formed on the first semiconductor layer 200. The first electrode 400 may be formed in a pattern form so that solar light may be transmitted into the solar cell.

The first electrode 400 may be formed of a metal material having excellent conductivity using a sputtering process using a mask, a metal organic chemical vapor deposition (MOCVD) process, or a printing process. For example, the first electrode 400 is Ag, Al, Ag + Al, Ag + Mg, Ag + Mn, Ag + Sb, Ag + Zn, Ag + Mo, Ag + Ni, Ag + Cu, Ag + It may be formed by a printing process using a paste of a metal material such as Al + Zn. In this case, the printing process may include screen printing, inkjet printing, gravure printing, gravure offset printing, reverse printing, flexo printing, Alternatively, the method may be a micro contact printing method. As such, when the printing process is used, the first electrode 400 may be formed in a pattern form so as to be spaced apart at predetermined intervals in a single process.

Next, as shown in FIG. 8D, the semiconductor wafer 100 on which the first electrode 400 is formed is inverted up and down, and then a second semiconductor layer 500 is formed on the bottom surface of the inverted semiconductor wafer 100.

In the process of forming the second semiconductor layer 500, an N-type semiconductor layer, for example, an N-type amorphous silicon layer is formed on the bottom surface of the semiconductor wafer 100 by using a plasma enhanced chemical vapor deposition (PECVD) process. It can be done in a process. Accordingly, the second semiconductor layer 500 is formed not only on the lower surface of the semiconductor wafer 100 but also on the lower surface portion of the semiconductor wafer 100 in view of process characteristics.

Next, as shown in FIG. 8E, a second electrode 700 is formed on the second semiconductor layer 500.

Since the second electrode 700 is formed on the bottom surface of the solar cell, the second electrode 700 may be formed on the bottom surface of the second semiconductor layer 500. However, the second electrode 700 may also be formed in a pattern form so that the reflected sunlight may be incident on the bottom surface of the solar cell. The second electrode 700 is formed by the same process as the first electrode 400, Ag, Al, Ag + Al, Ag + Mg, Ag + Mn, Ag + Sb, Ag + Zn, Ag It may be made of a metal material such as + Mo, Ag + Ni, Ag + Cu, Ag + Al + Zn.

Next, as shown in FIG. 8F, the upper and lower surfaces of the semiconductor wafer 100 are removed by removing the edge portions of the semiconductor wafer 100 along the separation groove line 110 (see FIG. 8E) using a physical separation process. Is electrically disconnected. By such a physical separation process, an inclined surface that is a part of the separation groove line is formed at the upper edge portion of each side of the semiconductor wafer 100. A photoelectric conversion region, that is, the first semiconductor layer 200 is formed on the inclined surface.

In the physical separation process, each edge portion of the semiconductor wafer 100 may be separated from the semiconductor wafer 100 by vacuum suction or pressurization of each edge portion of the semiconductor wafer 100.

As described above, in the method of manufacturing the solar cell according to the first embodiment of the present invention, after the separation groove line 110 is formed at the edge of the semiconductor wafer 100, the semiconductor wafer including the separation groove line 110 is provided. Forming a photoelectric conversion layer on the upper surface of the (100) and then removing the edge portion of the semiconductor wafer 100 along the separation groove line 110 through a physical separation process, the first and second generated in the conventional solar cell The fall of the film | membrane characteristic of a semiconductor layer can be prevented.

In addition, in the method of manufacturing a solar cell according to the first embodiment of the present invention, the edge portion of the semiconductor wafer 100 is removed by a physical separation process using the separation groove line 110, thereby the size of the semiconductor wafer 100. Is reduced, the dead zone is not formed in the edge portion of the semiconductor wafer 100 having a standard area by using the semiconductor wafer 100 having a size as large as the area to be removed by the separation groove line 110, the solar cell Can improve the photoelectric conversion efficiency.

9A to 9J are cross-sectional views schematically illustrating a method of manufacturing a solar cell according to a second embodiment of the present invention, which relates to a method of manufacturing a solar cell according to the second embodiment shown in FIG. 4. will be. A detailed description of the same process as that described above will be omitted.

First, as shown in FIG. 9A, a semiconductor wafer 100 having a predetermined electrical polarity is prepared.

Next, as shown in FIG. 9B, the separation groove line 110 is formed along the upper edge portion of the semiconductor wafer 100 using the separation groove line forming process. In this case, the separation groove line forming process may be performed using a cutting wheel, a needle, or a laser.

Next, as can be seen in Figure 9c, by performing the above-described wet cleaning process to clean the semiconductor wafer 100 including the separation groove line 110, particles and transition metal contaminants generated in the separation groove line forming process Remove it.

Next, as shown in FIG. 9D, the first semiconductor layer 200 is formed on the upper surface of the semiconductor wafer 100 including the separation groove line 110. In this case, the first semiconductor layer 200 is formed not only on the top surface of the semiconductor wafer 100 and the inclined surface inside the separation groove line 110, but also on the top surface portion of the semiconductor wafer 100.

Next, as shown in FIG. 9E, a first conductive layer 300 is formed on the first semiconductor layer 200.

The process of forming the first conductive layer 300 may be performed by using a sputtering process or a metal organic chemical vapor deposition (MOCVD) process, indium tin oxide (ITO), ZnOH, ZnO: B, ZnO: Al, SnO ₂ , SnO ₂ : F and the like to form a transparent conductive material layer. The first conductive layer 300 is formed not only on the upper surface of the first semiconductor layer 200 but also on the upper surface portion of the semiconductor wafer 100 along its side surface.

Next, as shown in FIG. 9F, a first electrode 400 is formed on the first conductive layer 300. The first electrode 400 may be formed in a pattern form so that solar light may be transmitted into the solar cell.

Next, as shown in FIG. 9G, the semiconductor wafer 100 on which the first electrode 400 is formed is inverted up and down, and then a second semiconductor layer 500 is formed on the bottom surface of the inverted semiconductor wafer 100. Accordingly, the second semiconductor layer 500 is formed not only on the lower surface of the semiconductor wafer 100 but also on the lower surface portion of the semiconductor wafer 100 in view of process characteristics. In this case, the second semiconductor layer 500 may overlap a portion of the first conductive layer 300 formed on the lower surface portion of the semiconductor wafer 100.

Next, as shown in FIG. 9H, a second conductive layer 600 is formed on the second semiconductor layer 500. The second conductive layer 600 may be formed using a sputtering process or a metal organic chemical vapor deposition (MOCVD) process, such as indium tin oxide (ITO), ZnOH, ZnO: B, ZnO: Al, and SnO _2. , SnO ₂ : F and the like to form a transparent conductive material layer. The second conductive layer 600 is formed not only on the upper surface of the second semiconductor layer 500 but also on the lower surface portion of the semiconductor wafer 100 along its side surface. In addition, the second conductive layer 600 may overlap a portion of the first conductive layer 300 formed on the lower surface portion of the semiconductor wafer 100.

Next, as shown in FIG. 9I, a second electrode 700 is formed on the second conductive layer 600.

Next, as shown in FIG. 9J, the upper and lower surfaces of the semiconductor wafer 100 are removed by removing the edge portions 130 of the semiconductor wafer 100 along the separation groove line 110 using a physical separation process. Isolate electrically. By the physical separation process, an inclined surface 106 that is a part of the separation groove line 110 is formed at the upper edge portion of each side of the semiconductor wafer 100. The first semiconductor layer 200 and the first conductive layer 300 are formed on the inclined surface 106.

As described above, the method of manufacturing the solar cell according to the second embodiment of the present invention not only provides the same effects as the first embodiment of the present invention described above, but also through the first and second conductive layers 300 and 600. By improving the mobility of the carrier, the efficiency of the solar cell can be further improved.

In the method of manufacturing the solar cell according to the second embodiment described above, the first conductive layer 300 and the second conductive layer 600 are both formed, but the present invention is not limited thereto. The first conductive layer 300 is not limited thereto. The formation process of each of the and second conductive layers 600 may be omitted.

FIG. 10 is a cross-sectional view illustrating an embodiment of the physical separation process illustrated in FIG. 9J.

A physical separation process according to an embodiment will be described in detail with reference to FIG. 10 as follows.

First, the semiconductor wafer 100 including the first and second electrodes 400 and 700 is mounted on the stage 800. In this case, the semiconductor wafer 100 is seated on the stage 800 in an upside down shape. In addition, the stage 800 is vacuum-adsorbed to fix the upper surface of the semiconductor wafer 100 including the first electrode 400 by using the first vacuum adsorption force.

Then, the vacuum suction frame 810 is aligned and arranged on the edge portion 130 of each side of the semiconductor wafer 100.

Then, by providing a second vacuum suction force lower than the first vacuum suction force to the suction nozzle 820 of the vacuum suction frame 810 to vacuum suction the edge portions 130 of each side of the semiconductor wafer 100, FIG. 9J. As shown in FIG. 2, the edge portions 130 of the sides of the semiconductor wafer 100 are cut. That is, when the suction nozzle 820 vacuum-adsorbs the edge portions 130 of the sides of the semiconductor wafer 100, the separation groove line 110 is formed on the semiconductor wafer 100 by the vacuum suction force of the suction nozzle 820. Cracks are generated along the edges, and the edge portions 130 of the sides of the semiconductor wafer 100 are cut and separated by the cracks.

FIG. 11 is a cross-sectional view illustrating another embodiment of the physical separation process illustrated in FIG. 9J.

Hereinafter, the physical separation process according to another embodiment will be described in detail with reference to FIG. 11.

First, the semiconductor wafer 100 including the first and second electrodes 400 and 700 is mounted on the stage 900. In this case, the stage 900 is vacuum-adsorbed and fixes the lower surface of the semiconductor wafer 100 including the second electrode 700 by using a vacuum suction force.

Then, the pressing frame 910 is aligned and arranged on the edge portion 130 of each side of the semiconductor wafer 100.

Then, by lowering the pressing frame 910 in accordance with the driving of the frame lifting means 920 for lifting the pressing frame 910 to press the edge portion 130 of each side of the semiconductor wafer 100 to a predetermined pressure, As illustrated in 9j, the edge portions 130 of the sides of the semiconductor wafer 100 are cut. That is, when the pressing frame 910 is lowered to press the edge portions 130 of the sides of the semiconductor wafer 100, cracks are generated along the separation groove line 110 by the pressing force of the pressing frame 910. By such cracks, the edge portions 130 of the sides of the semiconductor wafer 100 are cut and separated.

12A to 12H are cross-sectional views schematically illustrating a method of manufacturing a solar cell according to a third embodiment of the present invention, which relates to the method of manufacturing the solar cell according to the third embodiment shown in FIG. will be. A detailed description of the same process as that described above will be omitted.

First, as shown in FIG. 12A, a semiconductor wafer 100 having a predetermined electrical polarity is prepared, and the separation groove line 110 is formed along the upper edge portion of the semiconductor wafer 100 using the above-described separation groove line forming process. ), And the semiconductor wafer 100 including the separation groove line 110 is cleaned and dried through the above-described wet cleaning process.

Next, as shown in FIG. 12B, the first intrinsic semiconductor layer 150 is formed on the upper surface of the semiconductor wafer 100 including the separation groove line 110.

The first intrinsic semiconductor layer 150 may be formed by forming an intrinsic (I) -type amorphous silicon layer on the upper surface of the semiconductor wafer 100 by using a plasma enhanced chemical vapor deposition (PECVD) process. Accordingly, due to process characteristics, the first intrinsic semiconductor layer 150 is formed on the top surface of the semiconductor wafer 100 and the inclined surface of the inside of the separation groove line 110, as well as on the upper surface portion of the semiconductor wafer 100.

Next, as shown in FIG. 12C, a first semiconductor layer 200 is formed on the first intrinsic semiconductor layer 150. The process of forming the first semiconductor layer 200 may be performed using a plasma enhanced chemical vapor deposition (PECVD) process on a top surface of the first intrinsic semiconductor layer 150, for example, a P-type amorphous silicon layer. It can be made to the process of forming. Accordingly, the first semiconductor layer 200 is formed not only on the top surface of the first intrinsic semiconductor layer 150 and the inclined surface of the separation groove line 110, but also on the top surface of the semiconductor wafer 100 due to process characteristics. do.

Next, as shown in FIG. 12D, a first conductive layer 300 is formed on the first semiconductor layer 200, and the first electrode 400 is patterned on the first conductive layer 300. Form.

Next, as shown in FIG. 12E, the semiconductor wafer 100 on which the first electrode 400 is formed is inverted up and down, and then a second intrinsic semiconductor layer 450 is formed on the bottom surface of the inverted semiconductor wafer 100. do. The second intrinsic semiconductor layer 450 may be formed by forming an intrinsic (I) -type amorphous silicon layer on a lower surface of the semiconductor wafer 100 using a plasma enhanced chemical vapor deposition (PECVD) process. Accordingly, the second intrinsic semiconductor layer 450 is formed not only on the lower surface of the semiconductor wafer 100 but also on the lower surface portion of the semiconductor wafer 100 due to process characteristics.

Next, as shown in FIG. 12F, a second semiconductor layer 500 is formed on the second intrinsic semiconductor layer 450. The process of forming the second semiconductor layer 500 is an N-type semiconductor layer, for example, an N-type amorphous silicon layer, using a plasma enhanced chemical vapor deposition (PECVD) process on the upper surface of the second intrinsic semiconductor layer 450. It can be made to the process of forming. Accordingly, the second semiconductor layer 500 is formed not only on the upper surface of the second intrinsic semiconductor layer 450 but also on the lower surface portion of the semiconductor wafer 100 due to process characteristics.

Next, as shown in FIG. 12G, the second conductive layer 600 is formed on the second semiconductor layer 500, and the second electrode 700 is formed on the second conductive layer 600.

Next, as shown in FIG. 12H, by removing the edge portions 130 of the semiconductor wafer 100 along the separation groove line 110 using the physical separation process illustrated in FIG. 10 or 11 described above. The upper and lower surfaces of the semiconductor wafer 100 are electrically separated. By the physical separation process, an inclined surface 106 that is a part of the separation groove line 110 is formed at the upper edge portion of each side of the semiconductor wafer 100. The first semiconductor layer 200 and the first conductive layer 300 are formed on the inclined surface 106.

Meanwhile, in the method of manufacturing the solar cell according to the third embodiment described above, the first conductive layer 300 and the second conductive layer 600 are both formed, but the present invention is not limited thereto. The first conductive layer 300 is not limited thereto. The formation process of each of the and second conductive layers 600 may be omitted.

13A to 13F are cross-sectional views schematically illustrating a method of manufacturing a solar cell according to a fourth embodiment of the present invention, which relates to the method of manufacturing the solar cell according to the fourth embodiment shown in FIG. will be. A detailed description of the same process as that described above will be omitted.

First, as shown in FIG. 13A, a semiconductor wafer 100 having a predetermined electrical polarity is prepared, and a separation groove line 110 is formed along an upper edge portion of the semiconductor wafer 100 using a separation groove line forming process. Form.

Next, as shown in FIG. 13B, a lightly doped first semiconductor layer 200a is formed on the upper surface of the semiconductor wafer 100 including the isolation groove line 110, and the lightly doped first semiconductor is formed. The first semiconductor layer 200 is formed by forming the heavily doped first semiconductor layer 200b on the layer 200a. Each of the lightly doped first semiconductor layer 200a and the heavily doped first semiconductor layer 200b may be a semiconductor wafer (not only an inclined surface of an upper surface of the semiconductor wafer 100 and an interior of the separation groove line 110). It is also formed in the upper side portion of 100).

The lightly doped first semiconductor layer 200a and the heavily doped first semiconductor layer 200b may be performed by an extension process in one chamber. That is, the doped P-type semiconductor layer 200a and the highly doped P-type semiconductors, such as boron (B), are controlled in a plasma enhanced chemical vapor deposition (PECVD) chamber. The first P-type semiconductor layer 200b may be formed to extend.

Specifically, in a process for producing the first solar cell under mass production, a predetermined amount of B ₂ H ₆ gas is introduced into the chamber to form a P-type dopant atmosphere in the chamber, and then SiH ₄ and H ₂ gases are formed. Supplying to form the lightly doped P-type first semiconductor layer 200a, specifically, the lightly doped P-type amorphous silicon layer. Subsequently, B ₂ H ₆ gas is supplied as a dopant gas together with SiH ₄ and H ₂ gases to form the first heavily doped P-type semiconductor layer 200b, specifically, the heavily doped P-type amorphous silicon layer. .

Meanwhile, after the process of forming the heavily doped P-type first semiconductor layer 200b is completed, a predetermined amount of B ₂ H ₆ gas remains in the chamber. Therefore, from the second solar cell production after the first solar cell production, since the inside of the chamber is already formed in a P-type dopant atmosphere, SiH ₄ and H ₂ do not supply additional dopant gas, that is, B ₂ H ₆ gas into the chamber. gas only the supply and the first semiconductor layer (200a) of the lightly doped P-type may be formed, followed by SiH ₄ and H ₂ gas and with B ₂ H ₆ gas feed to the first of the highly doped P-type The semiconductor layer 200b is formed.

As described above, the low concentration doped P-type semiconductor layer 200a and the high concentration doped P-type semiconductor layer 200b may be formed by controlling only the supply amount of the reaction gas in one chamber. There is an advantage in that productivity is improved because no equipment or additional process is added.

Next, as shown in FIG. 13C, a first conductive layer 300 is formed on the first semiconductor layer 200, and the first electrode 400 is patterned on the first conductive layer 300. Form.

Next, as shown in FIG. 13D, the semiconductor wafer 100 on which the first electrode 400 is formed is vertically inverted, and then the second semiconductor layer 500a is lightly doped on the bottom surface of the inverted semiconductor wafer 100. The second semiconductor layer 500 is formed by forming a highly doped second semiconductor layer 500b on the lightly doped second semiconductor layer 500a. Each of the lightly doped second semiconductor layer 500a and the heavily doped second semiconductor layer 500b is formed not only on the lower surface of the semiconductor wafer 100 but also on the lower surface portion of the semiconductor wafer 100.

The lightly doped second semiconductor layer 500a and the heavily doped second semiconductor layer 500b are similar to the above-described lightly doped first semiconductor layer 200a and heavily doped first semiconductor layer 200b. It can be carried out by an extension process in the chamber of. That is, the low-doped N-type semiconductor layer 500a and the high-doped semiconductor layer may be controlled in a single PECVD chamber using a dopant gas of a Group 5 element such as phosphorus (P). The N-type second semiconductor layer 500b may be formed to extend, and detailed description thereof will be omitted.

Meanwhile, the process of any one of the lightly doped first semiconductor layer 200a and the lightly doped second semiconductor layer 500a may be omitted.

Next, as shown in FIG. 13E, a second conductive layer 600 is formed on the second semiconductor layer 500, and a second electrode 700 is formed on the second conductive layer 600.

Next, as can be seen in FIG. 13F, by removing each side edge portion 130 of the semiconductor wafer 100 along the separation groove line 110 by using the physical separation process illustrated in FIG. 10 or 11 described above. The upper and lower surfaces of the semiconductor wafer 100 are electrically separated. By the physical separation process, an inclined surface 106 that is a part of the separation groove line 110 is formed at the upper edge portion of each side of the semiconductor wafer 100. The first semiconductor layer 200 and the first conductive layer 300 are formed on the inclined surface 106.

Meanwhile, in the method of manufacturing the solar cell according to the fourth embodiment described above, the first conductive layer 300 and the second conductive layer 600 are both formed, but the present invention is not limited thereto. The first conductive layer 300 is not limited thereto. The formation process of each of the and second conductive layers 600 may be omitted.

14A to 14F are cross-sectional views schematically illustrating a method of manufacturing a solar cell according to a fifth embodiment of the present invention, which relates to the method of manufacturing the solar cell according to the fifth embodiment shown in FIG. will be. A detailed description of the same process as that described above will be omitted.

First, as shown in FIG. 14A, a semiconductor wafer 100 having a predetermined electrical polarity is prepared, and an upper separation groove line 110a is formed along an upper edge portion of the semiconductor wafer 100 using a separation groove line forming process. And a lower separation groove line 110b along the lower edge portion of the semiconductor wafer 100. Each of the upper and lower separation groove lines 110a and 110b is formed to have a predetermined depth from an upper surface and a lower surface of the semiconductor wafer 100 and may have a “V” shaped cross section. Each of the upper and lower separation groove lines 110a and 110b is formed to overlap each other, and is spaced apart from the side surface of the semiconductor substrate 100 by a distance L of 1 to 2 mm.

Next, as shown in FIG. 14B, the first semiconductor layer 200 is formed on the top surface of the semiconductor wafer 100 including the upper separation groove line 110a.

In the process of forming the first semiconductor layer 200, a P-type semiconductor layer, for example, a P-type amorphous silicon layer, is formed on the upper surface of the semiconductor wafer 100 by using a plasma enhanced chemical vapor deposition (PECVD) process. It can be done in a process. Accordingly, the first semiconductor layer 200 is formed not only on the top surface of the semiconductor wafer 100 and the inclined surface of the upper separation groove line 110a but also on the top surface portion of the semiconductor wafer 100 due to process characteristics.

Next, as shown in FIG. 14C, a first conductive layer 300 is formed on the first semiconductor layer 200, and the first electrode 400 is patterned on the first conductive layer 300. Form.

Next, as shown in FIG. 14D, after inverting the semiconductor wafer 100 on which the first electrode 400 is formed, the lower surface of the semiconductor wafer 100 inverted so that the lower separation groove line 110b faces upward. The second semiconductor layer 500 is formed thereon.

In the process of forming the second semiconductor layer 500, an N-type semiconductor layer, for example, an N-type amorphous silicon layer is formed on the bottom surface of the semiconductor wafer 100 by using a plasma enhanced chemical vapor deposition (PECVD) process. It can be done in a process. Accordingly, due to process characteristics, the second semiconductor layer 500 is formed not only on the inclined surface of the lower surface of the semiconductor wafer 100 and the lower separation groove line 110b but also on the lower surface portion of the semiconductor wafer 100.

Next, as shown in FIG. 14E, a second conductive layer 600 is formed on the second semiconductor layer 500, and a second electrode 700 is formed on the second conductive layer 600.

Next, as can be seen in FIG. 14F, each side edge portion of the semiconductor wafer 100 along the upper or lower separation groove lines 110a and 110b using the above-described physical separation process shown in FIG. 10 or 11. By removing the 130, the upper and lower surfaces of the semiconductor wafer 100 are electrically separated. By the physical separation process, an upper inclined surface 106 which is a part of the upper separation groove line 110a is formed in the upper corner portion of each side of the semiconductor wafer 100, and the first semiconductor layer is formed in the upper inclined surface 106. 200 and the first conductive layer 300 are formed. In addition, a lower inclined surface 108, which is a part of the lower separation groove line 110b, is formed at a lower edge portion of each side of the semiconductor wafer 100 by a physical separation process, and the second semiconductor is formed on the lower inclined surface 108. The layer 500 and the second conductive layer 600 are formed.

Meanwhile, in the method of manufacturing the solar cell according to the fifth embodiment described above, the first conductive layer 300 and the second conductive layer 600 are both formed, but the present invention is not limited thereto. The first conductive layer 300 is not limited thereto. The formation process of each of the and second conductive layers 600 may be omitted. In this case, the solar cell according to the manufacturing method of the solar cell according to the fifth embodiment has the same structure as the solar cell of the first embodiment shown in FIG.

On the other hand, the manufacturing method of the solar cell according to the fifth embodiment of the present invention, the semiconductor wafer 100 and the first semiconductor layer 200 in the same manner as the solar cell according to the third embodiment shown in FIG. In addition, the first intrinsic semiconductor layer 150 may be additionally formed between the two layers, and the second intrinsic semiconductor layer 450 may be additionally formed between the semiconductor wafer 100 and the second semiconductor layer 500.

On the other hand, the manufacturing method of the solar cell according to the fifth embodiment of the present invention, as in the solar cell according to the fourth embodiment shown in FIG. 6 described above, the first semiconductor layer 200 and the second semiconductor The structure of layer 500 can be changed. That is, the first semiconductor layer 200 is a lightly doped first semiconductor layer 200a formed on the upper surface of the semiconductor wafer 100 and a heavily doped first semiconductor layer 200a formed on the lightly doped first semiconductor layer 200a. It consists of 1 semiconductor layer 200b. In addition, the second semiconductor layer 500 is a lightly doped second semiconductor layer 500a formed on the bottom surface of the semiconductor wafer 100 and a heavily doped second semiconductor layer 500a. It may be made of two semiconductor layers (500b).

As described above, the solar cell manufacturing method according to the fifth embodiment of the present invention provides the above-described physical separation process by forming upper and lower separation groove lines 110a and 110b overlapping each other on the semiconductor wafer 100. It can be done easily.

15A to 15C are cross-sectional views schematically illustrating a method of manufacturing a solar cell according to a sixth embodiment of the present invention. A detailed description of the same process as that described above will be omitted.

First, as shown in FIG. 15A, a semiconductor wafer 100 having a predetermined electrical polarity is prepared, and an upper separation groove line 110a is formed along an upper edge portion of the semiconductor wafer 100 using a separation groove line forming process. And the lower separation groove line 110b are alternately formed along the lower edge of the semiconductor wafer 100. Each of the upper and lower separation groove lines 110a and 110b is formed to have a predetermined depth from an upper surface and a lower surface of the semiconductor wafer 100 and may have a “V” shaped cross section. Each of the upper and lower separation groove lines 110a and 110b is formed to be staggered at a predetermined distance without overlapping each other, and is spaced apart from the side surface of the semiconductor substrate 100 by a distance L of 1 to 2 mm.

Next, as shown in FIG. 14B, the first semiconductor layer 200 is formed on the top surface of the semiconductor wafer 100 including the upper separation groove line 110a.

In the process of forming the first semiconductor layer 200, a P-type semiconductor layer, for example, a P-type amorphous silicon layer, is formed on the upper surface of the semiconductor wafer 100 by using a plasma enhanced chemical vapor deposition (PECVD) process. It can be done in a process. Accordingly, the first semiconductor layer 200 is formed not only on the top surface of the semiconductor wafer 100 and the inclined surface of the upper separation groove line 110a but also on the top surface portion of the semiconductor wafer 100 due to process characteristics.

Subsequently, a first conductive layer 300 is formed on the first semiconductor layer 200, and a first electrode 400 is formed on the first conductive layer 300 in a pattern form.

Subsequently, the semiconductor wafer 100 on which the first electrode 400 is formed is inverted up and down, and then, on the lower surface of the semiconductor wafer 100 inverted so that the lower separation groove line 110b faces upward, a second semiconductor layer ( 500).

In the process of forming the second semiconductor layer 500, an N-type semiconductor layer, for example, an N-type amorphous silicon layer is formed on the bottom surface of the semiconductor wafer 100 by using a plasma enhanced chemical vapor deposition (PECVD) process. It can be done in a process. Accordingly, due to process characteristics, the second semiconductor layer 500 is formed not only on the inclined surface of the lower surface of the semiconductor wafer 100 and the lower separation groove line 110b but also on the lower surface portion of the semiconductor wafer 100.

Subsequently, a second conductive layer 600 is formed on the second semiconductor layer 500, and a second electrode 700 is formed on the second conductive layer 600.

Next, as shown in FIG. 14C, each side edge of the semiconductor wafer 100 along the upper or lower separation groove lines 110a and 110b using the physical separation process illustrated in FIG. 10 or 11 described above. The upper and lower surfaces of the semiconductor wafer 100 are electrically separated by removing the portion 130. By the physical separation process, an upper inclined surface 106 which is a part of the upper separation groove line 110a is formed in the upper corner portion of each side of the semiconductor wafer 100, and the first semiconductor layer is formed in the upper inclined surface 106. 200 and the first conductive layer 300 are formed. In addition, a lower inclined surface 108, which is a part of the lower separation groove line 110b, is formed at a lower edge portion of each side of the semiconductor wafer 100 by a physical separation process, and the second semiconductor is formed on the lower inclined surface 108. The layer 500 and the second conductive layer 600 are formed.

Meanwhile, in the method of manufacturing the solar cell according to the sixth embodiment described above, although the first conductive layer 300 and the second conductive layer 600 are both formed, the present invention is not limited thereto. The first conductive layer 300 is not limited thereto. The formation process of each of the and second conductive layers 600 may be omitted. In this case, the solar cell according to the manufacturing method of the solar cell according to the sixth embodiment has the same structure as the solar cell of the first embodiment shown in FIG.

On the other hand, the manufacturing method of the solar cell according to the sixth embodiment of the present invention, the semiconductor wafer 100 and the first semiconductor layer 200 in the same manner as the solar cell according to the third embodiment shown in FIG. In addition, the first intrinsic semiconductor layer 150 may be additionally formed between the two layers, and the second intrinsic semiconductor layer 450 may be additionally formed between the semiconductor wafer 100 and the second semiconductor layer 500.

On the other hand, the manufacturing method of the solar cell according to the sixth embodiment of the present invention, the first semiconductor layer 200 and the second semiconductor layer in the same manner as the solar cell according to the fourth embodiment shown in FIG. The structure of 500 may be changed. That is, the first semiconductor layer 200 is a lightly doped first semiconductor layer 200a formed on the upper surface of the semiconductor wafer 100 and a heavily doped first semiconductor layer 200a formed on the lightly doped first semiconductor layer 200a. It consists of 1 semiconductor layer 200b. In addition, the second semiconductor layer 500 is a lightly doped second semiconductor layer 500a formed on the bottom surface of the semiconductor wafer 100 and a heavily doped second semiconductor layer 500a. It may be made of two semiconductor layers (500b).

As described above, the solar cell manufacturing method according to the sixth exemplary embodiment of the present invention facilitates the above-described physical separation process by forming upper and lower separation groove lines 110a and 110b intersecting each other on the semiconductor wafer 100. It can be done.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100 semiconductor wafer 150 first intrinsic semiconductor layer
200: first semiconductor layer 200a: lightly doped first semiconductor layer
200b: highly doped first semiconductor layer 300: first conductive layer
400: first electrode 450: second intrinsic semiconductor layer
500: second semiconductor layer 500a: lightly doped second semiconductor layer
500b: heavily doped second semiconductor layer 600: second conductive layer
700: second electrode

Claims (19)

Semiconductor wafer:
A first semiconductor layer formed on an upper surface of the semiconductor wafer;
A first electrode formed on the first semiconductor layer;
A second semiconductor layer formed on the bottom surface of the semiconductor wafer; And
It is configured to include a second electrode formed on the second semiconductor layer,
And an isolation groove line in which the first semiconductor layer is formed on an upper surface of the semiconductor wafer. The method of claim 1,
A solar cell according to claim 1, wherein a separation groove line in which the second semiconductor layer is formed is formed on a lower side of the semiconductor wafer. 3. The method of claim 2,
A portion of the side surface of the semiconductor wafer is exposed to the outside to electrically separate the first and second semiconductor layer formed in the separation groove line. A semiconductor wafer having an upper inclined surface formed obliquely on an upper edge portion of each side:
A first semiconductor layer formed on the upper surface and the upper inclined surface of the semiconductor wafer;
A first electrode formed on the first semiconductor layer;
A second semiconductor layer formed on the bottom surface of the semiconductor wafer; And
And a second electrode formed on the second semiconductor layer. 5. The method of claim 4,
The semiconductor wafer further has a lower inclined surface formed inclined at the lower edge portion of each side,
The second semiconductor layer is formed on the lower surface and the lower inclined surface of the semiconductor wafer. 6. The method according to any one of claims 1 to 5,
Further comprising a first conductive layer formed on the upper surface of the first semiconductor layer and a second conductive layer formed on the lower surface of the second semiconductor layer,
The first electrode is formed on the upper surface of the first conductive layer,
The second electrode is a solar cell, characterized in that formed on the upper surface of the second conductive layer. 6. The method according to any one of claims 1 to 5,
An intrinsic semiconductor layer is further formed between at least one of the semiconductor wafer and the first semiconductor layer and between the semiconductor wafer and the second semiconductor layer. 6. The method according to any one of claims 1 to 5,
At least one semiconductor layer of the first semiconductor layer and the second semiconductor layer comprises a lightly doped semiconductor layer formed on the semiconductor wafer and a lightly doped semiconductor layer formed on the lightly doped semiconductor layer. Solar cells. Forming a separation groove line in an edge portion of the semiconductor wafer;
Forming a first semiconductor layer on an upper surface of the semiconductor wafer including the separation groove line, and forming a second semiconductor layer on the lower surface of the semiconductor wafer;
Forming a first electrode on the first semiconductor layer, and forming a second electrode on the second semiconductor layer; And
And separating the edge portion of the semiconductor wafer from the semiconductor wafer using the separation groove line. The method of claim 9,
And a depth of the separation groove line is 1/2 to 3/4 of the thickness of the semiconductor wafer. The method of claim 9,
The distance between the separation groove line and the side surface of the semiconductor wafer is 1 ~ 2mm manufacturing method of the solar cell. Forming an upper separation groove line in an upper edge portion of the semiconductor wafer and forming a lower separation groove line in a lower edge portion of the semiconductor wafer;
Forming a first semiconductor layer on an upper surface of the semiconductor wafer including the upper separation groove line, and forming a second semiconductor layer on a lower surface of the semiconductor wafer including the lower separation groove line;
Forming a first electrode on the first semiconductor layer, and forming a second electrode on the second semiconductor layer; And
And separating the edge portion of the semiconductor wafer from the semiconductor wafer by using the upper and lower separation groove lines. 13. The method of claim 12,
And the upper separation groove line and the lower separation groove line overlap each other or cross each other. The method of claim 13,
The upper separation groove line and the lower separation groove line is a solar cell manufacturing method, characterized in that spaced apart from the side of the semiconductor wafer by a distance of 1 ~ 2mm. 15. The method according to any one of claims 9 to 14,
The separation groove line is a solar cell manufacturing method, characterized in that formed by a laser to have a predetermined depth to have a "V" shaped cross section. 15. The method according to any one of claims 9 to 14,
The step of separating the edge portion of the semiconductor wafer is a solar cell manufacturing method, characterized in that for separating the edge portion from the semiconductor wafer by vacuum adsorption or pressure of the edge portion of the semiconductor wafer. 15. The method according to any one of claims 9 to 14,
Forming a first conductive layer on an upper surface of the first semiconductor layer; And
Further comprising forming a second conductive layer on a lower surface of the second semiconductor layer,
The first electrode is formed on the upper surface of the first conductive layer, the second electrode is a manufacturing method of a solar cell, characterized in that formed on the upper surface of the second conductive layer. 15. The method according to any one of claims 9 to 14,
And forming an intrinsic semiconductor layer between at least one of the semiconductor wafer and the first semiconductor layer and between the semiconductor wafer and the second semiconductor layer. 15. The method according to any one of claims 9 to 14,
The step of forming at least one semiconductor layer of the first semiconductor layer and the second semiconductor layer,
Forming a lightly doped semiconductor layer on the semiconductor wafer; And
Forming a highly doped semiconductor layer on the lightly doped semiconductor layer.

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