KR20130102212A - Method of manufacturing semiconductor device using the hardmask - Google Patents

Method of manufacturing semiconductor device using the hardmask Download PDF

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Publication number
KR20130102212A
KR20130102212A KR1020120023266A KR20120023266A KR20130102212A KR 20130102212 A KR20130102212 A KR 20130102212A KR 1020120023266 A KR1020120023266 A KR 1020120023266A KR 20120023266 A KR20120023266 A KR 20120023266A KR 20130102212 A KR20130102212 A KR 20130102212A
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KR
South Korea
Prior art keywords
hard mask
layer
etching
semiconductor device
forming
Prior art date
Application number
KR1020120023266A
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Korean (ko)
Inventor
김현영
이시영
송상엽
이완호
김주현
허원구
김기범
Original Assignee
삼성전자주식회사
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Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020120023266A priority Critical patent/KR20130102212A/en
Publication of KR20130102212A publication Critical patent/KR20130102212A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The present invention relates to a method for manufacturing a semiconductor device, comprising: forming an etched layer on a semiconductor substrate; Forming a hard mask layer formed of a transparent conductive oxide film on the etched layer; Forming a photoresist pattern on the hard mask layer; Patterning the hard mask layer using the photoresist pattern as an etch mask to form a hard mask; Etching the etched layer using the hard mask as an etch mask; And removing the hard mask by wet etching. .

Description

Method of manufacturing semiconductor device using hard mask {Method of manufacturing semiconductor device using the hardmask}

The present invention relates to a method for manufacturing a semiconductor device using a hard mask.

Due to the high integration of semiconductor devices, the line width of the pattern is narrowed, and therefore, the pattern of the photoresist film may be difficult due to the limitation of the resolution of the exposure equipment. Accordingly, a technique using a hard mask formed of a material having a high etching selectivity is being used. Here, the hard mask transfers the pattern of the photoresist to the substrate.

However, as the stacking structure of the semiconductor device is complicated, the thickness of the stacking structure increases, and thus, the deposition thickness of the hard mask is also increased. As a result, there is an additional need for a process for smoothly removing the thick hard mask in a subsequent process. In addition, there is a problem in that the alignment key opening process is additionally performed before the current etching process because the photo alignment key formed in the previous process is not seen due to the use of a thick hard mask.

Therefore, in the method of manufacturing a semiconductor device using such a hard mask, a separate process for removing the hard mask must be additionally performed, and an alignment key opening process must be additionally performed. .

Therefore, there is a need for a method of manufacturing a semiconductor device using a hard mask that is easy to form a fine pattern and can simplify the process.

A method of manufacturing a semiconductor device according to the present invention includes forming an etching target layer on a semiconductor substrate; Forming a hard mask layer formed of a transparent conductive oxide film on the etched layer; Forming a photoresist pattern on the hard mask layer; Patterning the hard mask layer using the photoresist pattern as an etch mask to form a hard mask; Etching the etched layer using the hard mask as an etch mask; And removing the hard mask by wet etching.

The transparent conductive oxide film may be indium tin oxide (ITO).

The forming of the hard mask layer may be performed using any one of evaporation, sputtering, and chemical vapor deposition (CVD).

The forming of the hard mask layer may be performed at a temperature of 500 ° C. or less.

In the forming of the hard mask layer, after forming a transparent conductive oxide film using any one of evaporation or sputtering at room temperature, annealing may be performed at a temperature of 500 ° C. or less.

Removing the hard mask by wet etching may be performed using an etchant including HCl or HNO 3 .

The etched layer may be any one selected from the group consisting of oxides, nitrides and oxynitrides.

The nitride may be a material including SiN.

The oxide may be a material including SiO 2 .

Patterning the hard mask layer made of ITO may include dry etching the ITO using the photoresist pattern as an etch mask.

The dry etching may be performed using a plasma containing Cl 2 or BCl 3 gas.

Etching the etched layer using the hard mask as an etch mask may perform dry etching on the etched layer.

Etching the etched layer formed of an oxide layer made of a material including SiO 2 may be performed by dry etching using a plasma containing CF 4 gas.

In the present invention, by using a transparent conductive oxide film having a high etching selectivity as a hard mask, it is easy to manufacture a semiconductor device having a fine pattern, and a separate alignment key opening process can be omitted, thereby simplifying the process.

1 is a process flowchart showing a method of manufacturing a semiconductor device using a transparent conductive oxide film as a hard mask according to an embodiment of the present invention.
2 to 7 are process diagrams illustrating a method of manufacturing the semiconductor device illustrated in FIG. 1.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of the elements in the drawings may be exaggerated for clarity of description, and the elements denoted by the same reference numerals in the drawings are the same elements.

1 is a flowchart illustrating a method of manufacturing a semiconductor device using a transparent conductive oxide film as a hard mask according to an embodiment of the present invention, and FIGS. 2 to 7 are flowcharts illustrating a method of manufacturing the semiconductor device shown in FIG. 1. .

In the method of manufacturing a semiconductor device using the hard mask according to the present invention, first, as shown in FIG. 2, the etching target layer 120 is formed on the substrate 100 (S110).

The substrate 100 according to the present embodiment may be a conventional semiconductor substrate such as silicon. In addition, although not shown on the substrate 100, it may be provided as an electronic device that performs a predetermined function, such a device may be implemented in a structure in which a plurality of semiconductor layers are stacked. For example, a semiconductor memory device such as a RAM or a photovoltaic device such as a semiconductor light emitting diode may be formed on the substrate 100.

The etched layer 120 may be any one of an oxide, nitride, and oxynitride on the substrate 100. For example, the oxide may be SiO 2 , and the nitride may be SiN x. The etched layer may be formed using a conventional deposition method or the like.

Next, as shown in FIG. 3, a hard mask layer 140 is formed on the etched layer 120 (S120).

The hard mask layer 140 may be made of a transparent conductive oxide, and in particular, the hard mask layer 140 may be indium tin oxide (ITO).

The hard mask layer 140 may be formed using evaporation, sputtering, chemical vapor deposition (CVD), or the like, which is used in a conventional semiconductor device film forming process.

Here, the hard mask layer 140 is preferably formed at a temperature of 500 ° C or less. However, the hard mask layer 140 may be formed by performing annealing at a temperature of 500 ° C. after forming a transparent conductive oxide film using a deposition method or a sputtering method at room temperature.

As described above, in forming the stacked structure of the semiconductor device, it is necessary to precisely align the stacked structure formed on the substrate and the hard mask to be formed by etching the hard mask layer. However, in the present invention, since the optically transparent transparent conductive oxide film is used as the hard mask layer, alignment of the hard mask and the underlying structure is easy. Therefore, it is not necessary to perform the alignment key open process for the subsequent process, thereby simplifying the process.

Next, as shown in FIG. 4, a photoresist layer is deposited on the hard mask layer 140 and then patterned to form a photoresist pattern 160 (S130).

The photoresist pattern 160 may be formed by coating a photoresist layer on the hard mask layer 140 and patterning the photoresist layer by exposure and development.

Next, as shown in FIG. 5, the hard mask layer 140 is etched using the photoresist pattern 160 as an etch mask to form a hard mask 141 (S140).

It is preferable to perform a dry etching process on the hard mask layer 140.

In particular, when the hard mask layer 140 is made of indium tin oxide (ITO), Cl 2 is added to the hard mask layer 140. Or BCl 3 It is preferable to perform a dry etching process using plasma containing such gases. Cl 2 Alternatively, the plasma including the gas of BCl 3 has a high etching selectivity compared to the etching layer 120 formed of any one material of an oxide, nitride, and oxynitride formed thereunder. Thus Cl 2 , or BCl 3 When the dry etching of the hard mask layer 140 made of ITO using a gas, such as gas, only the hard mask layer 140 made of ITO is etched and the etching layer 120 made of any one of oxides, nitrides, and oxynitrides disposed below. Is not etched.

Next, as shown in FIG. 6, the etching target layer 120 is etched using the hard mask 141 as an etching mask (S150).

The etching target layer 120 is preferably subjected to a dry etching process.

In particular, the plasma in which the etching layer 120 is included in the case containing SiO 2, the hard mask and CF 4 gas, considering the etching selectivity of the etching layer, etching selection ratio of high comprising the SiO 2 is made of a transparent conductive oxide film It is preferable to perform a dry etching process using.

Next, as shown in FIG. 7, the hard mask 141 is removed (S160).

In order to remove the hard mask 141, it is preferable to perform a wet etching process. As an etchant for the wet etching, a solution containing HCl and HNO 3 may be used. As such, when the hard mask is removed by the wet etching method, recesses that may occur in the stacked structure formed on the substrate are reduced as compared with the case where the hard mask is removed by dry etching. In addition, when the hard mask is removed by wet etching as in the present invention, the process may be simplified as compared to dry etching, which requires several steps to remove the hard mask.

In particular, the hard mask made of ITO is characterized in that the ITO film is easily removed when the wet mask is removed by wet etching using an etchant such as HCl or HNO 3 .

Therefore, no additional process other than wet etching is needed to remove the hard mask.

As such, when a hard mask made of a transparent conductive oxide is used when manufacturing a semiconductor device, since the hard mask is transparent, an additional process of opening an alignment key for alignment with an underlying layer is unnecessary, and the hard mask is wet. Since it is easily removed by etching, it is possible to simplify the process. In addition, since etching is performed using a hard mask made of a transparent conductive oxide having a high etching selectivity, it is easy to manufacture a semiconductor device having a fine pattern.

The method of manufacturing a semiconductor device using a hard mask made of a transparent conductive oxide according to the present invention may be used in a capacitor forming process of a DRAM, a channel hole forming process of a flash memory, and the like.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is defined by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims, As will be described below.

100: substrate 120: etching layer
121: pattern of the semiconductor device 140: hard mask layer
141: hard mask 160: photoresist pattern

Claims (13)

Forming an etched layer on the semiconductor substrate;
Forming a hard mask layer formed of a transparent conductive oxide film on the etched layer;
Forming a photoresist pattern on the hard mask layer;
Patterning the hard mask layer using the photoresist pattern as an etch mask to form a hard mask;
Etching the etched layer using the hard mask as an etch mask; And
Removing the hard mask by wet etching;
Wherein the semiconductor device is a semiconductor device.
The method of claim 1,
The transparent conductive oxide film is a method of manufacturing a semiconductor device, characterized in that ITO (Indium Tin Oxide).
The method of claim 1,
The forming of the hard mask layer may be performed using any one of evaporation, sputtering, and chemical vapor deposition (CVD).
The method of claim 3,
Forming the hard mask layer, the method of manufacturing a semiconductor device, characterized in that performed at a temperature of 500 ° C or less.
The method of claim 1,
The forming of the hard mask layer may include performing annealing at a temperature of 500 ° C. or less after forming a transparent conductive oxide film using any one of evaporation and sputtering at room temperature. The manufacturing method of the semiconductor element.
The method of claim 1,
Removing the hard mask by wet etching may be performed using an etchant including HCl or HNO 3 .
The method of claim 1,
The etching layer is a method of manufacturing a semiconductor device, characterized in that any one selected from the group consisting of oxides, nitrides and oxynitrides.
The method of claim 7, wherein
The nitride is a method of manufacturing a semiconductor device, characterized in that the material containing SiN.
The method of claim 7, wherein
The oxide is a method of manufacturing a semiconductor device, characterized in that the material containing SiO 2 .
The method of claim 2,
The patterning of the hard mask layer made of ITO may include dry etching the ITO using the photoresist pattern as an etch mask.
The method of claim 10,
The dry etching is Cl 2 Or using a plasma containing BCl 3 gas.
The method of claim 1,
The etching of the etching target layer using the hard mask as an etching mask may include performing dry etching on the etching target layer.
10. The method of claim 9,
And etching the etched layer formed of an oxide layer made of a material containing SiO 2 by dry etching using a plasma containing CF 4 gas.
KR1020120023266A 2012-03-07 2012-03-07 Method of manufacturing semiconductor device using the hardmask KR20130102212A (en)

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KR1020120023266A KR20130102212A (en) 2012-03-07 2012-03-07 Method of manufacturing semiconductor device using the hardmask

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KR20130102212A true KR20130102212A (en) 2013-09-17

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