KR20130097310A - Array substrate for flat panel display and method of fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate for a flat panel display and a method for fabricating the same are provided to prevent plasma damage to an organic gate insulating layer and an organic semiconductor layer by forming a plasma protection layer between the organic gate insulating layer and a gate electrode. CONSTITUTION: A first protection layer (122a) includes a gate contact hole and a drain contact hole. A gate line (123) is formed on the upper part of the first protection layer. The gate line is in contact with a gate electrode through the gate contact hole. A pixel electrode (131) is formed on the upper part of the first protection layer. The pixel electrode is connected to a drain electrode through the drain contact hole.

Description

Array substrate for flat panel display and manufacturing method thereof {Array substrate for flat panel display and method of fabricating the same}

The present invention relates to a flat panel display device, and more particularly, to an array substrate including a thin film transistor having an organic semiconductor layer using an organic semiconductor material.

In recent years, as the society enters a full-scale information age, a display field for processing and displaying a large amount of information has been rapidly developed, and various various flat panel display devices have been developed and are in the spotlight.

Specific examples of such flat panel display devices include a liquid crystal display device (LCD), a plasma display panel (PDP), a field emission display (FED) And electroluminescence display device (ELD). These flat panel display devices are excellent in performance of thinning, light weight, and low power consumption, and are rapidly replacing existing cathode ray tubes (CRTs).

On the other hand, such a flat panel display device uses a glass substrate to withstand the high heat generated during the manufacturing process, there is a limit in providing light weight thinning and flexibility.

Therefore, recently, flexible display devices, which are manufactured to maintain display performance even if they are bent like paper using flexible materials such as plastic substrates instead of glass substrates without conventional flexibility, are rapidly emerging as next-generation flat panel displays.

However, in the flexible display device using the plastic substrate, the maximum process temperature of the component forming process is limited to 200 ° C. or less due to manufacturing characteristics.

Recently, organic semiconductor thin film transistors that can be formed in a low temperature process below 180 ° C have been actively developed to be used as switching elements of flexible display devices.

Since the manufacturing of the thin film transistor by the low temperature process mainly uses the coating apparatus, the initial equipment investment cost is very low than the manufacturing using expensive vacuum deposition equipment, and as a result, the manufacturing cost can be reduced. .

On the other hand, the organic semiconductor material proceeds to a low temperature process of 200 ℃ or less has a characteristic that is very vulnerable to the etching solution for etching the developer or metal material of the photoresist mainly used for patterning.

That is, when forming an organic semiconductor layer having a predetermined pattern, the organic semiconductor material does not have photosensitive characteristics. Therefore, in order to pattern the organic semiconductor layer, exposure, development, and etching processes using photosensitive materials are generally performed. When the organic semiconductor material is exposed to the developer of the photoresist mainly used for the internal structure, the internal structure is damaged, thereby deteriorating the semiconductor characteristics and increasing the degradation rate.

Therefore, after the organic gate insulating film and the gate metal material are deposited on the organic semiconductor layer for patterning the organic semiconductor layer, the gate metal material is patterned as a mask. In the process of forming the gate metal material on the organic gate insulating film, In addition, plasma damage is directly applied to the organic gate insulating layer and the organic semiconductor layer.

Plasma damage inflicts damage to the organic gate insulating film and the organic semiconductor layer in the form of a charge of the plasma to form the gate metal material. Deterioration occurs.

The present invention is to solve the above problems, the first object is to provide an array substrate manufacturable in a low temperature process, through which the second object to reduce the manufacturing cost.

In addition, a third object of the semiconductor layer made of an organic semiconductor material to be more easily patterned without being exposed to a developer or an etching solution, and to prevent plasma damage to the organic gate insulating film and the organic semiconductor layer. The purpose.

In order to achieve the object as described above, the present invention comprises a data wiring formed in one direction on the boundary of the pixel region on the substrate in which the pixel region having a switching region is defined; Source and drain electrodes formed in the switching region on the substrate and spaced apart from each other; An organic semiconductor layer formed on one end of the source and drain electrodes facing each other and on an area separated from the source and drain electrodes; An organic gate insulating layer formed over the organic semiconductor layer; A plasma protection layer formed on the organic gate insulating layer; A gate electrode formed on the plasma protection layer; A first passivation layer formed over the gate electrode and including a gate contact hole exposing the gate electrode and a drain contact hole exposing the drain electrode; A gate wiring formed over the first passivation layer and in contact with the gate electrode through the gate contact hole and intersecting the data wiring and formed at a boundary of the pixel region; An array substrate for a flat panel display device is formed on the first passivation layer and includes a pixel electrode connected to the drain electrode through the drain contact hole.

In this case, the plasma protective layer is made of Y2O3, Al2O3, or made of a copolymer polymer material of fluorobenzene as a backbone, and the organic semiconductor layer, the organic gate insulating layer, the plasma protective layer, and a gate electrode Consists of the same shape and the same area.

And a drain contact pad on the first passivation layer, the drain contact pad contacting the drain electrode through the drain contact hole, and a drain contact pad contact hole exposing the drain contact pad on the first passivation layer. A second protective layer is formed, and the pixel electrode contacts the drain contact pad through the drain contact pad contact hole.

The gate wiring overlaps the pixel electrode to form a storage capacitor overlapping each other with the first protective layer interposed therebetween.

In addition, the present invention provides a method of manufacturing a semiconductor device comprising: forming data lines extending in one direction on a boundary of the pixel area on a substrate on which a pixel area having a switching area is defined, and simultaneously forming source and drain electrodes spaced apart from each other in the switching area; Sequentially forming an organic semiconductor layer, an organic gate insulating film, a plasma protective layer, and a gate electrode in the spaced area between the source and drain electrodes and the source and drain electrodes and having the same shape and area; Forming a first passivation layer including a gate contact hole and a drain contact hole exposing the gate electrode and the drain electrode over the gate electrode; Forming a gate wiring on the first passivation layer to contact the gate electrode through the gate contact hole and a pixel electrode connected to the drain electrode through the drain contact hole; It provides a manufacturing method.

In this case, the forming of the gate electrode, the plasma protection layer, the organic gate insulating film, and the organic semiconductor layer may include an organic semiconductor material layer, a gate insulating material layer, and an entire surface of the substrate including the source and drain electrodes; Continuously depositing a plasma protective material layer, a first metal layer; Forming a photoresist pattern on the first metal layer corresponding to the spaced area between the source and drain electrodes and the source and drain electrodes; Forming a gate electrode by wet etching the first metal layer exposed to the outside of the photoresist pattern; Removing the photoresist pattern; Dry etching the plasma protective layer, the organic gate insulating material layer, and the organic semiconductor material layer exposed by the gate electrode portion to form the plasma protective layer, the organic gate insulating film, and the organic semiconductor layer. And forming a drain contact pad in contact with the drain electrode through the drain contact hole on the first passivation layer.

Further, a second passivation layer further comprises a drain contact pad contact hole exposing the drain contact pad over the first passivation layer, wherein the pixel electrode is connected to the drain contact pad through the drain contact pad contact hole. Contact.

As described above, according to the present invention, since the semiconductor layer is made of an organic semiconductor material which does not deteriorate even when the semiconductor layer is manufactured in a low temperature process of 200 ° C. or lower, the initial equipment investment is eliminated by using expensive vacuum deposition equipment. The cost is very inexpensive.

In particular, by using the gate electrode as a blocking mask in the process of patterning the organic semiconductor layer, the organic semiconductor layer can be patterned more easily without being exposed to the developer or etching solution.

The plasma protective layer is formed between the organic gate insulating film and the gate electrode, thereby preventing the plasma damage from being applied to the organic gate insulating film and the organic semiconductor layer.

Through this, there is an effect that can prevent the crack of the gate electrode formed on the organic gate insulating film, there is an effect that can reduce the leakage current and improve the current flashing ratio.

1 is a plan view schematically showing one pixel area of an array substrate including a thin film transistor having an organic semiconductor layer according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. FIG.
3a to 3b are photographs taken through a scanning electron microscope (SEM) of the surface of the gate electrode with or without the plasma protective layer.
4A to 4B are graphs showing electrical characteristics of a thin film transistor with and without a plasma protective layer.
5A through 5J are cross-sectional views illustrating manufacturing steps of an array substrate including a thin film transistor having an organic semiconductor layer according to an embodiment of the present invention.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

1 is a plan view schematically illustrating one pixel area of an array substrate including a thin film transistor having an organic semiconductor layer according to an embodiment of the present invention.

As shown in the drawing, the array substrate 101 includes a plurality of gate wirings 121 and data wirings 110 defining the pixel region P by crossing the gate wirings 121 arranged in parallel with a predetermined interval. .

In this case, the thin film transistor Tr is formed in the switching region TrA near the intersection point of the gate wiring 121 and the data wiring 110 of each pixel region P, and the pixel electrode is substantially in the region where the image is realized. 131 is formed.

The thin film transistor Tr includes source and drain electrodes 115 and 117, a semiconductor layer 113, and a gate electrode 111, and the source electrode 115 is branched from the data line 110. The drain electrode 117 is spaced apart from the source electrode 115.

The gate electrode 111 includes the source and drain electrodes 115 and 117 and covers the spaced apart regions of the two electrodes, and the gate electrode 111 includes the thin film transistor Tr. It is connected to the gate wiring 121 through the gate contact hole 121 of the first protective layer 122a formed on the front surface of the substrate.

In addition, the semiconductor layer 113 is formed of an organic semiconductor material, and is disposed under the gate electrode 111, and an organic gate insulating layer 119 is positioned between the semiconductor layer 113 and the source and drain electrodes 115 and 117. do.

The drain electrode 117 is connected to the drain contact pad 125 through the drain contact hole 127 of the first passivation layer 122a and includes an array including a gate wiring 121 and a drain contact pad 125. A second passivation layer 122b is formed on the front surface of the substrate 101, and the pixel electrode 131 is connected to the drain contact pad 125 through the drain contact pad contact hole 129 of the second passivation layer 122b. Electrically connected.

In this case, the pixel electrode 131 is partially overlapped with a portion of the gate wiring 121, so that the overlapping pixel electrode 131 and the gate wiring 121 are respectively the first and second storage electrodes 123a, 131a, and FIG. 2), and the second protective layer 122b formed between the two electrodes serves as a dielectric to form the storage capacitor StgC.

Here, the array substrate 101 of the present invention is made of an organic semiconductor material that does not degrade the device performance even if the semiconductor layer 113 is manufactured in a low temperature process of 200 ℃ or less, thereby eliminating the need for expensive vacuum deposition equipment Therefore, the initial capital investment cost is very low.

In particular, in the array substrate 101 of the present invention, the semiconductor layer 113 made of an organic semiconductor material can be patterned more easily without being exposed to a developer or an etching solution, and the organic gate insulating film 119 and the organic semiconductor layer 113 can be patterned. Plasma damage can be prevented from being applied.

Since the characteristic configuration of the present invention can be better represented through a cross-sectional structure, it will be described in more detail with reference to the cross-sectional configuration of the array substrate according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along a cutting line II-II of FIG. 1, and FIGS. 3A to 3B are photographs taken through a scanning electron microscope (SEM) of the surface of a gate electrode with or without a plasma protective layer. to be.

4A to 4B are graphs showing the electrical characteristics of the thin film transistor with and without the plasma protective layer.

In this case, for convenience of description, a portion in which the thin film transistor Tr in each pixel region P is to be formed will be defined as a switching region TrA.

As illustrated, the array substrate 101 has data wirings (110 in FIG. 1) extending in the first direction, and the source is formed in the switching region TrA in a form branched from the data wirings (110 in FIG. 1). An electrode 115 and a drain electrode 117 spaced apart from each other are formed.

At this time, the source and drain electrodes 115 and 117 and the data wiring (110 in FIG. 1) are formed under the insulating layer, for example, silicon oxide (SiO 2) or silicon nitride (SiN x), on the entire surface of the substrate 101. May be further formed. This is to improve adhesion between the substrate 101, the metal source and drain electrodes 115 and 117, and the data wiring 110 (see FIG. 1).

Meanwhile, the source and drain electrodes 115 and 117 may be made of one selected from gold (Au), silver (Ag), aluminum (Al), and indium-tin oxide (ITO), where a relatively high work function value is obtained. Gold (Au) and indium-tin-oxide (ITO), which are conductive materials having a p-type organic semiconductor material, are used when the organic semiconductor layer 113 is composed, and silver and aluminum (Al) are mainly n-type. When the organic semiconductor layer 113 is formed of an organic semiconductor material of, the source and drain electrodes 115 and 117 are formed, respectively.

An organic semiconductor layer 113 made of an organic semiconductor material is formed in contact with one end of the source and drain electrodes 115 and 117 facing each other, and corresponding to the spaced apart regions of the two electrodes 115 and 117. .

Here, the organic semiconductor material may be pentacene, copper phthalocyanine, polythiophene, polyaniline, polyacetylene, polypyrrole, polyphenylene vinylene ) Or derivatives thereof, and any other known organic semiconductor material.

An organic gate insulating layer 119 having the same shape and the same area as that of the organic semiconductor layer 113 and completely overlapping the organic semiconductor layer 113 is formed. The organic gate insulating layer 119 is formed of an organic insulating material, for example, It may be made of a fluorine-based polymer material or a copolymerized polymer material using a fluorine-based monomer.

In addition, a plasma protection layer 200 having the same shape and the same area as that of the organic gate insulation layer 119 and completely overlapping the organic gate insulation layer 119 is formed. The gate electrode 111 having the same shape and the same area as the layer 200 is formed.

Here, the plasma protection layer 200 serves to protect the organic gate insulating layer 119 and the organic semiconductor layer 113 below the plasma protection layer in the process of forming the gate electrode 111.

That is, the gate electrode 111 is made of one of molybdenum (Mo), chromium (Cr), titanium (Ti), the gate electrode 111 is formed through sputtering, the gate electrode by sputtering As a method of forming the 111, a sputter target (not shown) for forming the gate electrode 111 on the substrate 101 on which the plasma protection layer 200 is formed in the reaction chamber (not shown) is spaced apart by a predetermined distance. After the injection, oxygen gas and argon gas are injected to form plasma excited ions of the sputter target.

In this case, when the plasma protection layer 200 is not present, plasma damage is caused to the organic gate insulating layer 119 and the organic semiconductor layer 113 due to the high temperature generated by the oxygen ions and the plasma generated in the process of forming the gate electrode 111. Will be added.

Accordingly, the organic gate insulating layer 119 and the organic semiconductor layer 113 have a problem in that the device characteristics are deteriorated. However, the present invention is directed to the organic gate insulating layer 119 and the organic semiconductor from plasma damage. By further forming the plasma protective layer 200 to protect the layer 113, it is possible to prevent the occurrence of the above problems.

In this case, the plasma protection layer 200 may be made of Y 2 O 3 and Al 2 O 3 having resistance to plasma, and may be made of a copolymerized polymer material having fluorobenzene as a backbone.

The first protective layer 122b is formed on the gate electrode 111 on the front surface of the array substrate 101 by using an organic insulating material, for example, photoacrylic or polyvinyl alcohol (PVA). In this case, the first passivation layer 122b includes a gate contact hole 121 exposing the gate electrode 111 in the switching region TrA, and a drain contact hole 127 exposing the drain electrode 117. It is provided.

In addition, any one of gold (Au), silver (Ag), copper (Cu), molybdenum (MoTi), aluminum (Al), aluminum neodymium (AlNd), and nickel (Ni) may be disposed on the first passivation layer 122b. The gate wiring 123 is formed to contact the gate electrode 111 through the gate contact hole 121 and intersect with the data wiring 110 (see FIG. 1) to define the pixel region P.

The drain contact pad 125 is formed at one side of the gate wiring 123 to contact the drain electrode 117 through the drain contact hole 127.

The second passivation layer 122b is formed on the gate wiring 123 and the drain contact pad 125 on the front surface of the array substrate 101 by using an organic insulating material, for example, photoacrylic or polyvinyl alcohol (PVA). have.

In this case, the second passivation layer 122b includes a drain contact pad contact hole 129 exposing the drain contact pad 125 in the switching region TrA, and a drain contact over the second passivation layer 122b. The thin film transistor Tr having the organic semiconductor layer 113 according to the present invention is formed by forming the pixel electrode 131 electrically connected to the drain electrode 117 of the thin film transistor Tr through the pad contact hole 129. The array substrate 101 is completed.

On the other hand, in each pixel area P, the second storage electrode having the pixel electrode 131 extending through the second protective layer 122b over the first storage electrode 123a formed of the gate wiring 123 ( 131a) is formed.

In this case, the first and second storage electrodes 123a and 131a overlapping each other with the second protective layer 122b interposed therebetween to form a storage capacitor StgC.

The present invention can be patterned more easily without using the gate electrode 111 as a blocking mask in the process of patterning the organic semiconductor layer 113, without being exposed to the developer or etching solution.

Further, by further forming the plasma protection layer 200 between the gate electrode 111 and the organic gate insulating film 119, it is possible to prevent plasma damage from being applied to the organic gate insulating film 119 and the organic semiconductor layer 113. have.

In addition, the plasma damage is prevented from being applied to the organic gate insulating film 119 and the organic semiconductor layer 113, thereby preventing cracking of the gate electrode 111 formed on the organic gate insulating film 119. can do.

That is, FIG. 3A is a photograph taken through a scanning electron microscope (SEM) of the surface of the gate electrode 111 formed directly on the organic gate insulating film 119, and the gate electrode on the organic gate insulating film 119. In the process of sputtering the 111, plasma damage is applied to the organic gate insulating layer 119, and cracks and the like are generated in the gate electrode 111 formed thereon.

On the contrary, in FIG. 3B, after the plasma protection layer 200 is formed on the organic gate insulating layer 119, the surface of the gate electrode 111 on the plasma protection layer 200 is scanned. Photographed through a scanning electron microscope (SEM), the organic gate insulating film 119 is not subjected to plasma damage by the plasma protection layer 200, the gate electrode by the plasma damage of the organic gate insulating film 119 It can be confirmed that the crack of 111 does not occur.

As described above, since plasma damage is not applied to the organic gate insulating layer 119 and the organic semiconductor layer 113, the leakage current of the thin film transistor Tr may be reduced.

That is, when plasma damage is applied to the organic semiconductor layer 113, a problem occurs that the off current, that is, the off current, also increases due to the deterioration of device characteristics of the organic semiconductor layer 113.

4A and 4B, FIG. 4A is a graph illustrating electrical characteristics of a thin film transistor including a general organic semiconductor layer in which a plasma protection layer is not formed, and FIG. 4B is in accordance with an embodiment of the present invention. A graph showing electrical characteristics of the thin film transistor Tr on which the plasma protection layer 200 is formed on the organic semiconductor layer 113.

4A and 4B, the maximum current value of the thin film transistor having no plasma protective layer formed thereon is ~ 1E-5, and the leakage current value is 1E-9 ~ 1E-10, and the thin film according to the embodiment of the present invention. The maximum current value of the transistor Tr is ˜1E-5 and the leakage current value is 1E-12.

That is, it can be seen that the current in the off state of the thin film transistor Tr in which the plasma protection layer 200 is formed is reduced compared to the thin film transistor in which the plasma protective layer 200 is not formed.

In this way, by reducing the leakage current, the current flicker ratio Ion / Ioff is improved.

In conclusion, it can be seen that the thin film transistor Tr of the present invention has excellent electrical characteristics in all aspects, such as current flashing ratio and leakage current, compared to the thin film transistor in which the plasma protection layer 200 is not formed.

Accordingly, the thin film transistor Tr of the present invention can be patterned more easily without the organic semiconductor layer 113 being exposed to a developer or an etching solution, and a plasma protective layer between the gate electrode 111 and the organic gate insulating film 119. By further forming the 200, plasma damage can be prevented from being applied to the organic gate insulating film 119 and the organic semiconductor layer 113.

Therefore, the plasma damage is prevented from being applied to the organic gate insulating film 119 and the organic semiconductor layer 113, thereby preventing the crack of the gate electrode 111 formed on the organic gate insulating film 119 from occurring. The leakage current reduction and current flashing ratio can be improved.

Hereinafter, the process of manufacturing the array substrate 101 of the present invention will be described in more detail.

5A through 5J are cross-sectional views illustrating manufacturing processes of an array substrate including a thin film transistor having an organic semiconductor layer according to an exemplary embodiment of the present invention, and a manufacturing step process for a portion cut along the cutting line II-II of FIG. 1. It is a cross section.

In this case, for convenience of description, an area in which the thin film transistor Tr is formed in the pixel area P is defined as a switching area TrA.

First, as shown in FIG. 5A, a low-resistance metal material, for example, gold (Au), silver (Ag), aluminum (Al), aluminum alloy (AlNd), copper (Cu), is disposed on the transparent insulating substrate 101. , By depositing one of the copper alloy to form a first metal layer (not shown).

Subsequently, application of a photoresist (not shown) on the first metal layer (not shown), exposure using a photo mask (not shown), development of the exposed photoresist (not shown), and etching of the first metal layer (not shown) And a mask process including a series of unit processes, such as strips of photoresist (not shown), to extend data in one direction (110 in FIG. 1) and data wiring (for each pixel region P). A source electrode 115 connected to 110 of FIG. 1 and a drain electrode 117 spaced apart from the source electrode 115 by a predetermined interval are formed.

Next, as shown in FIG. 5B, a liquid organic semiconductor material, for example, liquid pentacene or the like, is disposed above the source and drain electrodes 115 and 117 and the data wiring (110 in FIG. 1) spaced apart from each other. Polythiophene is coated on the entire surface using an inkjet device, a nozzle coating device, a bar coating device, a slit coating device, a spin coating device or a printing device. The material layer 113a is formed.

Subsequently, the above-described inkjet apparatus, nozzle coating apparatus, bar coating apparatus, and slit are successively coated with an organic insulating material, for example, a fluoropolymer or a fluorinated monomer, onto the organic semiconductor material layer 113a. The gate insulating material layer 119a having a flat surface is formed by coating the entire surface using a slit coating apparatus, a spin coating apparatus, or a printing apparatus.

Next, a plasma protection layer is deposited on the gate insulating material layer 119a by depositing a copolymer polymer material having a backbone of Y 2 O 3, Al 2 O 3, or fluorobenzene made of an organic insulating material. The material layer 200a is formed.

Next, the second metal layer 111a is formed by depositing one of a metal material, for example, molybdenum (Mo), chromium (Cr), and titanium (Ti), on the plasma protection material layer 200a.

In this case, in the process of depositing the second metal layer 111a, the plasma protection material layer 200a causes plasma damage to the gate insulating material layer 119a and the organic semiconductor material layer 113a by plasma generated by sputtering. It prevents you from losing.

Therefore, the problem of deterioration of device characteristics of the gate insulating material layer 119a and the organic semiconductor material layer 113a may be prevented from occurring, and cracking of the second metal layer 111a may be prevented from occurring.

In addition, the leakage current reduction and the current flashing ratio can be improved.

Next, as shown in FIG. 5C, a photoresist, for example, a photoresist made of general photoacrylic material or a photoresist made of PAC, is coated on the entire surface of the substrate 101 and exposed and developed on the second metal layer 111a. The photoresist pattern 180 is formed in the switching region TrA.

In this case, the photoresist pattern 180 may include the source and drain electrodes 115 and 117 spaced apart from each other among the switching regions TrA and the second metal layer 111a to correspond to the spaced regions between the two electrodes 115 and 117. To form up.

Next, as shown in FIG. 5D, the second metal layer (111a of FIG. 5C) exposed to the outside of the photoresist pattern 180 is removed by wet etching, thereby removing the gate electrode 111 over the plasma protection material layer 200a. ).

Thereafter, as shown in FIG. 5E, the photoresist pattern (180 of FIG. 5D) remaining on the gate electrode 111 is removed by going through the strip.

Next, as shown in FIG. 5F, dry etching is performed using the gate electrode 111 as a blocking mask, thereby exposing the plasma protective material layer (200a of FIG. 5D) and the gate below the gate electrode 111. By simultaneously removing the insulating material layer (119a of FIG. 5D) and the organic semiconductor material layer (113a of FIG. 5D), an island-shaped plasma having the same shape and area as the gate electrode 111 and completely overlapping the switching region TrA is completely formed. The protective layer 200 is formed, and at the same time, the organic gate insulating layer 119 and the organic semiconductor layer 113 having the same size and pattern shape are formed under the plasma protective layer 200.

In this case, the source and drain electrodes 115 and 117, the organic semiconductor layer 113, the organic gate insulating layer 119, and the gate electrode 111 formed in the switching region TrA form a thin film transistor Tr.

Next, as shown in FIG. 5G, the gate contact hole 121 and the drain exposing the gate electrode 111 are exposed by applying an organic insulating material or depositing and patterning an inorganic insulating material on the gate electrode 111. A first passivation layer 122a having a drain contact hole 127 exposing the electrode 117 is formed.

Next, as shown in FIG. 5H, a low-resistance metal material, for example, gold (Au) or silver (Ag), is disposed on the first protective layer 122a having the gate contact hole 121 and the drain contact hole 127. By depositing copper (Cu), molybdenum (MoTi), aluminum (Al), aluminum neodymium (AlNd), and nickel (Ni) to form a third metal layer (not shown) and patterning it by performing a mask process. The gate wiring 123 is formed to contact the gate electrode 111 through the contact hole 121 and intersect with the data wiring 110 (see FIG. 1) to define the pixel region P.

A drain contact pad 125 is formed to contact the drain electrode 117 through the drain contact hole 127.

Next, as illustrated in FIG. 5I, the drain contact pad 125 may be exposed by coating an organic insulating material on the gate wiring 123 and the drain contact pad 125 or by depositing and patterning an inorganic insulating material. A second protective layer 122b having a drain contact pad contact hole 129 is formed.

Next, as illustrated in FIG. 5J, a transparent conductive material, for example, a metal material ITO or IZO is deposited on the entire surface of the second protective layer 122b having the drain contact pad contact hole 129. Not shown).

Thereafter, the transparent conductive material layer (not shown) is patterned by a mask process to form the pixel electrode 131 in contact with the drain contact pad 125 through the drain contact pad contact hole 129 for each pixel region P. FIG. As a result, the array substrate 101 including the thin film transistor Tr having the organic semiconductor layer 113 is completed.

In this case, the pixel electrode 131 is formed so that a part of the end thereof overlaps with a part of the gate wiring 121, so that the overlapping pixel electrode 131 and the gate wiring 121 are respectively the first and second storage electrodes 123a and 131a. The second protective layer 122b formed between the two electrodes serves as a dielectric to form the storage capacitor StgC.

As described above, the array substrate 101 of the present invention is made of an organic semiconductor material that does not degrade the device performance even if the semiconductor layer 113 is manufactured in a low temperature process of 200 ℃ or less, using expensive vacuum deposition equipment By not doing so, the initial capital investment cost is very low.

In particular, by using the gate electrode 111 as a blocking mask in the process of patterning the organic semiconductor layer 113, the organic semiconductor layer 113 can be patterned more easily without being exposed to the developer or etching solution.

Further, by further forming the plasma protection layer 200 between the organic gate insulating film 119 and the gate electrode 111, it is possible to prevent plasma damage from being applied to the organic gate insulating film 119 and the organic semiconductor layer 113. have.

As a result, cracking of the gate electrode 111 formed on the organic gate insulating layer 119 may be prevented, and leakage current reduction and current flashing ratio may be improved.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

101: array substrate, 111: gate electrode, 113: organic semiconductor layer
115, 117: source and drain electrodes, 119: organic gate insulating film
121: drain contact hole, 122a, 122b: first and second protective layers
123: gate wiring (123a: first storage electrode), 125: drain contact pad
127: drain contact hole, 129: drain contact pad contact hole
131: pixel electrode (131a: second storage electrode)
200: plasma protective layer
Tr: thin film transistor, P: pixel area, StgC: storage capacitor

Claims (10)

Data wiring formed in one direction on a boundary of the pixel area on a substrate on which a pixel area having a switching area is defined;
Source and drain electrodes formed in the switching region on the substrate and spaced apart from each other;
An organic semiconductor layer formed on one end of the source and drain electrodes facing each other and on an area separated from the source and drain electrodes;
An organic gate insulating layer formed over the organic semiconductor layer;
A plasma protection layer formed on the organic gate insulating layer;
A gate electrode formed on the plasma protection layer;
A first passivation layer formed over the gate electrode and including a gate contact hole exposing the gate electrode and a drain contact hole exposing the drain electrode;
A gate wiring formed over the first passivation layer and in contact with the gate electrode through the gate contact hole and intersecting the data wiring and formed at a boundary of the pixel region;
A pixel electrode formed on the first passivation layer and connected to the drain electrode through the drain contact hole;
Array substrate for a flat panel display device comprising a.
The method of claim 1,
The plasma protective layer is made of Y 2 O 3, Al 2 O 3, or an array substrate for a flat panel display device made of a copolymerized polymer material having fluorobenzene as a backbone.
The method of claim 1,
And the organic semiconductor layer, the organic gate insulating film, the plasma protective layer, and the gate electrode have the same shape and the same area.
The method of claim 1,
And a drain contact pad in contact with the drain electrode through the drain contact hole on the first passivation layer.
5. The method of claim 4,
A second passivation layer including a drain contact pad contact hole exposing the drain contact pad is formed on the first passivation layer, and the pixel electrode contacts the drain contact pad through the drain contact pad contact hole. Array board for display device.
The method of claim 1,
And the gate wiring overlapping the pixel electrode to form a storage capacitor overlapping each other with the first protective layer interposed therebetween.
Forming data wirings extending in one direction on a boundary of the pixel region on a substrate on which a pixel region having a switching region is defined, and simultaneously forming source and drain electrodes spaced apart from each other in the switching region;
Sequentially forming an organic semiconductor layer, an organic gate insulating film, a plasma protective layer, and a gate electrode in the spaced area between the source and drain electrodes and the source and drain electrodes and having the same shape and area;
Forming a first passivation layer including a gate contact hole and a drain contact hole exposing the gate electrode and the drain electrode over the gate electrode;
Forming a gate wiring contacting the gate electrode through the gate contact hole on the first passivation layer and a pixel electrode connected to the drain electrode through the drain contact hole
Array substrate manufacturing method for a flat panel display device comprising a.
The method of claim 7, wherein
The forming of the gate electrode, the plasma protective layer, the organic gate insulating film, and the organic semiconductor layer may include:
Continuously depositing an organic semiconductor material layer, a gate insulating material layer, a plasma protective material layer, and a first metal layer on an entire surface of the substrate including the source and drain electrodes;
Forming a photoresist pattern on the first metal layer corresponding to the spaced area between the source and drain electrodes and the source and drain electrodes;
Forming a gate electrode by wet etching the first metal layer exposed to the outside of the photoresist pattern;
Removing the photoresist pattern;
Dry etching the plasma protective layer, the organic gate insulating material layer, and the organic semiconductor material layer exposed by the gate electrode portion to form the plasma protective layer, the organic gate insulating film, and the organic semiconductor layer. Array substrate manufacturing method for a flat panel display device comprising a.
The method of claim 7, wherein
And forming a drain contact pad in contact with the drain electrode through the drain contact hole on the first passivation layer.
The method of claim 9,
A second protective layer further includes a drain contact pad contact hole exposing the drain contact pad over the first passivation layer, wherein the pixel electrode contacts the drain contact pad through the drain contact pad contact hole. Method of manufacturing array substrate for flat panel display.

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