KR20130091418A - Multiplexer for high communication - Google Patents

Abstract

PURPOSE: A multiplexer for high speed communication is provided to improve eye opening by converting an inputted data signal into a real data signal and a dummy data signal which have different potential difference and then performing subtraction. CONSTITUTION: A multiplexer for high speed communication includes conversion units (110,120,130) and an output unit (Dout). The conversion unit converts a data signal inputted in parallel using a clock signal or a clock inverse signal into a real data signal and a dummy data signal which have different voltage level respectively. The output unit outputs potential difference between the real data signal and the dummy data signal. The conversion unit includes a clock control switching unit (110) and a data control switching unit (120). The clock control switching unit operates by being controlled by the clock signal or the clock inverse signal. The data control switching unit is controlled by a first or a second data signal and is outputted from the clock control switching unit.

Description

Multiplexer for High Speed Communications {MULTIPLEXER FOR HIGH COMMUNICATION}

The present invention relates to a multiplexer for high speed communication, and more particularly to a multiplexer for high speed communication using a dummy data signal.

The multiplexer is a device that sequentially converts data signals input in parallel into serial data signals and outputs the serial data signals.

However, as the communication speed is gradually increased, the multiplexer also has an issue of whether or not the eye opening of the output data signal is excellent. That is, when the processing speed of the multiplexer reaches several to several tens of Gbps, the eye opening of the output data signal is significantly worsened, so that it is difficult to obtain a normal data signal due to an error of the data signal.

Therefore, in recent years, circuit designers of high-speed communication systems are actively researching a technique capable of transmitting a data signal within a range in which eye opening is not damaged.

According to the present invention, a multiplexer for high speed communication having excellent eye opening can be provided by converting an input data signal into a real data signal and a dummy data signal having different potential differences.

The multiplexer for high-speed communication according to the first aspect of the present invention converts at least two or more data signals inputted in parallel by using a clock signal or a clock inversion signal into real data signals and dummy data signals having different voltage levels, respectively. ; And output means for outputting a potential difference between the real data signal and the dummy data signal.

Preferably, the phase of the real data signal is different from the phase of the dummy data signal, and the dummy is converted from the second data signal of the at least two data signals and the real data signal is converted from the first data signal of the at least two or more data signals. The data signal is converted simultaneously and synchronously.

Preferably, the output means outputs a potential difference between the real data signal corresponding to the first data signal of the at least two data signals and the dummy data signal corresponding to the second data signal of the at least two data signals.

The multiplexer for high-speed communication according to the second invention of the present application outputs the first and second real data signals and the first and second dummy data signals by delaying the first and second data signals having different phases by 90 degrees, respectively. Delay unit; A clock control switching unit controlled by a clock signal or a clock inversion signal and operating in different operating regions; A data control switching device configured to output a pair of data signals having different voltage levels, respectively, controlled by a pair of the first real data signal or the second dummy data signal, or controlled by a pair of the second real data signal or the first dummy data signal; part; And output means for outputting a potential difference of a pair of data signals having different voltage levels.

Preferably, the first real data signal and the second dummy data signal are converted simultaneously and synchronously.

Preferably, the clock control switching unit includes a plurality of switching elements controlled by the clock signal and connected in parallel to turn on in different operating regions.

Preferably, the data control switching unit includes a plurality of switching element groups independently connected to each other between the plurality of switching elements and the ground in the clock control switching unit to individually control the output of the plurality of switching elements.

Preferably, the output means outputs a potential difference between the first real data signal and the second dummy data signal.

Preferably, the swing width of the first real data signal is about 2 to 5 times larger than the swing width of the second dummy data signal.

According to the present invention, high-speed operation can be avoided by generating dummy signals having different phases and voltage levels inside the multiplexer, and a multiplexer having excellent eye opening can be implemented.

1A is a detailed circuit diagram of a multiplexer according to an embodiment of the present invention;
1B is a data signal generation circuit diagram according to an embodiment of the present invention;
2 is a data timing diagram of a multiplexer according to an embodiment of the present invention;
3A is a current path in a sensing period of a latch circuit according to an embodiment of the present invention;
3B illustrates a current path in a holding period of a latch circuit according to an embodiment of the present invention, and
4 is an ideal timing waveform diagram of a latch circuit according to an embodiment of the present invention.

Hereinafter, exemplary embodiment (s) of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the elements of each drawing, it should be noted that the same elements are denoted by the same reference numerals as much as possible even if they are displayed on different drawings. In addition, many specific details are shown in the following description, which is provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. Will be self-evident.

1A is a detailed circuit diagram of a multiplexer according to an embodiment of the present invention.

The multiplexer for high-speed communication of the present invention includes converting means (110, 120) for converting at least two or more data signals inputted in parallel using a clock signal or a clock inversion signal into real data signals and dummy data signals having different voltage levels, respectively. , 130); And output means Dout for outputting a potential difference between the real data signal and the dummy data signal. Here, reference numeral 130 denotes a subtraction part including a reactor and a resistor.

The multiplexer for high-speed communication of the present invention is a dummy data converted from a real data signal D11 converted from the first data signal D1 and two data signals D2 among at least two or more data signals. Signal D22 is converted simultaneously and synchronously.

The converting means in the multiplexer for high-speed communication of the present invention includes a clock control switching unit 110 controlled to operate by a clock signal CLK or a clock inversion signal CLKB; And a data control switching unit 120 controlled by the first or second data signal to control a plurality of outputs output from the clock control switching unit 110.

In addition, the clock control switching unit 110 in the converting means is controlled by the clock signal CLK and controlled by the plurality of switching elements 111 and 112 and the clock inversion signal CLKB connected in parallel to turn on in different operation regions. And a plurality of switching elements 113 and 114 connected in parallel to turn on in different operating regions.

In detail, the first switching element 111 is controlled by the clock signal CLK to operate in the saturation region, and the second switching element 112 is controlled by the clock signal CLK to operate in the active region. The third switching element 113 is controlled by the clock inversion signal CLKB to operate in the active region, and the fourth switching element 114 is controlled by the clock inversion signal CLKB to operate in the saturation region.

In addition, the data control switching unit 120 may include a first real data signal D11 corresponding to the first data signal D1 and a first dummy data signal D12 or a second data signal D2 corresponding to the first data signal D1. The second real data signal D21 and the second dummy data signal D22 are controlled between the plurality of switching elements 111, 112, 113, and 114 in the clock control switching unit 110 and the ground GND. A plurality of switching element groups 121, 122, 123, 124, 125, 126, 127, and 128 that are independently connected to each other to control the output of the plurality of switching elements 111, 112, 113, and 114 individually Include.

Specifically, the plurality of switching device groups include first to fourth switching device groups 121 and 122 (123 and 124) (125 and 126) and (127 and 128). The first switching device groups 121 and 122 are controlled by the first real data signal D11, the second switching device groups 123 and 124 are controlled by the second dummy data signal D22, and the third switching device. The groups 125 and 126 are controlled by the first dummy data signal D12, and the fourth switching device groups 127 and 128 are controlled by the second real data signal D21.

The plurality of switching elements 121 and 122 in the first switching element group are alternately turned on in accordance with a logic level of an applied data signal. The same applies to the second to fourth switching device groups.

FIG. 1B is a circuit diagram of a real and dummy data signal generation circuit according to an embodiment of the present invention, in which first real and dummy data signals D11 and D12 are generated from a first data signal D1, and a second data signal D2 is generated. It can be seen that the second real and dummy data signals D21 and 22 are generated.

The first real data signal D11 is a signal delayed by 90 degrees from the input first data signal D1, and the first dummy data signal D12 is a signal that uses the first data signal D1 as it is. The phase of the data signal D11 is 90 degrees behind the phase of the first dummy data signal D12. The second real data signal D21 is a signal delayed by 180 degrees from the input second data signal D2, and the second dummy data signal D22 is a signal delayed by 90 degrees from the second data signal D2. The phase of the second real data signal D21 is 90 degrees behind the phase of the second dummy data signal D22.

According to another embodiment of the present invention, the phases of the real data signal and the dummy data signal may be reversed and used. That is, it is apparent to those skilled in the art that the phase of the real data signal is designed to be ahead of the phase of the dummy data signal.

The output means Dout outputs a potential difference between the first real data signal D11 and the second dummy data signal D22 or between the second real data signal D21 and the first dummy data signal D12. Output the potential difference.

2 is a data timing diagram of a multiplexer according to an embodiment of the present invention.

During the P1 section, the value output from the output means Dout is as follows.

Dout = first real data signal D11 to second dummy data signal D22

During the P2 section, the value output from the output means Dout is as follows.

Dout = second real data signal D21-first dummy data signal D12

At this time, in order to increase the swing width of the data signal, Dout = D11n-D22p may be output or Dout = D11p-D22n during the P1 period. Similarly, during the P2 period, a value of Dout = D21n-D12p can be output or a value of Dout = D21p-D12n can be output.

Here, the swing width of the real data signal is approximately 0.4V (+ 0.2V to -0.2V), and the swing width of the dummy data signal is approximately 0.2V (+ 0.1V to -0.1V). Therefore, since the swing width of the data signal output from the output means Dout is approximately 0.3V (= 0.2V-(-0.1V)), excellent eye opening conditions can be provided.

In addition, according to one embodiment of the present invention, the following latch circuit can be used to reduce the power consumption by reducing the size of the switching elements.

Figure 3a is a current path in the sensing period of the latch circuit according to an embodiment of the present invention, Figure 3b is a current path in the holding period of the latch circuit according to an embodiment of the present invention, Figure 4 is An ideal timing waveform diagram of a latch circuit according to one embodiment.

The latch circuit 300 according to an embodiment of the present invention includes a sensing unit 310 for sensing a data signal (Dinp, Dinn) input in synchronization with a first edge of a clock signal Clk applied from the outside, and a clock. And a holding unit 320 for changing the voltage level of the data signal output in synchronization with the second edge of the signal Clk.

In addition, the sensing unit 310 of the latch circuit according to the embodiment of the present invention may form a path driven by the sum of the currents from the plurality of current sources in synchronization with the first edge of the clock signal CLK ( P1, in synchronization with the second edge of the clock signal CLK, a path driven by a current from a single current source can be formed (P2).

Here, the first edge is a falling edge and the second edge is a rising edge.

Further, during the first logic level of the clock signal CLK, any one of the plurality of switching elements facing in the sensing unit 310 is controlled by the clock signal CLK to operate in the active region to form a first current path. In addition, any one of a plurality of opposing switching elements in the holding unit 320 may be controlled by a reference voltage signal to operate in an active region to form the second current path.

For example, the switching elements of the latch circuit according to an embodiment of the present invention may operate as shown in Table 1.

Sensing Unit P1 P2 Holding unit P1 P2 M0 ON (sat.) ON (sat.) M11 ON (sat.) ON (sat.) M1 ON (act.) OFF M13 ON (act.) OFF M12 OFF ON (act.) M4 OFF ON (act.) M2 ON (sat.) OFF M5 OFF ON (sat.) M3 OFF OFF M6 OFF OFF

1) P1 section

During the first logic level of the clock signal CLK, while any one of the plurality of switching elements facing in the sensing unit 310 is controlled by the clock signal CLK to operate in the active region, the other is connected to the reference voltage signal. It can be controlled to operate in the cutoff area.

In detail, during the P1 period, the sensing unit 310 may include a plurality of current paths as follows.

Power supply voltage (Vdd)-> Switching element (M0)-> Switching element (M1)-> Switching element (M2 or M3)-> Ground (GND)

Power supply voltage (Vdd)-> Switching element (M11)-> Switching element (M13)-> Switching element (M2 or M3)-> Ground (GND)

That is, since the sensing unit 310 receives current from the plurality of current sources during the P1 period, the sensing unit 310 may be designed to reduce the size of the switching elements in the sensing unit 310.

The sensing unit 310 includes switching elements M0, M1, M2, M3, and M12.

The switching device M0 and the switching device M11 that receive the bias voltage Vbiasp as the control signal of the gate terminal are always turned on in the saturation region.

The switching element M1 connected between the drain terminal of the switching element M0 and the switching elements M2 and M3 for receiving the data signal and receiving the activated clock signal Clk as a control signal of the gate terminal is located in the active region. It works. The switching device M12, which is connected between the drain terminal of the switching device M0 and the ground and receives the reference voltage Vref as a control signal of the gate terminal, is turned off.

Any one of the switching elements M2 and M3 for data signal reception, which is connected between the drain terminal of the switching element M1 and the ground and uses the input complementary data signals Dinn and Dinp as a control signal of the gate terminal, If it is turned on in the saturation region, the other one is turned off.

The holding unit 320 includes switching elements M11, M13, M4, M5, and M6.

The switching element M13 connected between the drain terminal of the switching element M11 and the sensing unit 310 and receiving the reference voltage Vref as a control signal of the gate terminal operates in an active region. The switching element M4 connected between the drain terminal of the switching element M11 and the data signal holding switching elements M5 and M6 and receiving the inverted clock inversion signal CLKB as the control signal of the gate terminal is turned off. Is in a state.

The switching elements M5 and M6 connected in parallel between the drain terminal of the switching element M4 and the ground and using the other terminal's drain terminal voltage as the control signal of the gate terminal have the switching element M4 turned off. The switching elements M5 and M6 are both turned off during the placed P1 period.

Here, the level of the reference voltage signal is lower than the level of the bias voltage signal, and controlled by the clock inverted clock inverted signal to operate in the cutoff region.

For example, the level of the bias voltage Vbiasp may be 0.53 volts, the level of the reference voltage Vref may be 0.45 volts, the first level of the clock signal clk may be 0.25 volts, and the second level may be 0.65 volts.

2) P2 section

During the second logic level of the clock signal CLK, while any one of the plurality of switching elements facing in the sensing unit 310 is controlled by the reference voltage signal to operate in the active region, the other is connected to the clock signal CLK. It can be controlled to operate in the cutoff area.

Specifically, when the switching device M1 using the deactivated clock signal as the control signal of the gate terminal is in the turn-off state, the switching devices M2 and M3 connected in parallel between the drain terminal of the switching device M1 and ground. Is turned off.

Since the switching element M1 is turned off, the switching element M12 using the reference voltage Vref as the control voltage of the gate terminal is turned on in the active region. Accordingly, the sensing unit 3110 may form a single path of 'power supply voltage Vdd-> switching device M0-> switching device M12-> ground GND'.

On the other hand, since the switching device M4 using the activated clock inversion signal Clkb as the control signal of the gate terminal is turned on in the active region, the switching device M5 connected in parallel between the drain terminal of the switching device M4 and ground. , M6) are alternately turned on. Accordingly, the holding unit 120 may form a single path of 'power supply voltage Vdd-> switching element M11-> switching element M4-> switching element M5 or M6-> ground GND'. Can be.

As a result, the voltage level of the output signals Do_p and Do_n is high due to the plurality of current sources in the P1 section, while the voltage level of the output signal is low due to the single current source in the P2 section.

As described above, although the specific embodiment (s) have been described in the detailed description of the present invention, various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiment (s), but should be defined by the appended claims and equivalents thereof.

110: clock control switching unit
120: data control switching unit
130: subtraction part
310: sensing unit
320: holding unit

Claims (16)

Conversion means for converting at least two or more data signals inputted in parallel by using a clock signal or a clock inversion signal into real data signals and dummy data signals each having a different voltage level; And
Output means for outputting a potential difference between the real data signal and the dummy data signal
Multiplexer for high speed communication comprising a. The method of claim 1,
And a phase of the real data signal and a phase of the dummy data signal are different. The method of claim 2,
High speed, characterized in that the real data signal converted from the first data signal of the at least two or more data signals and the dummy data signal converted from the second data signal of the at least two or more data signals are converted simultaneously and synchronously Communication multiplexer. The method of claim 1, wherein the conversion means,
A clock control switching unit which is operated by being controlled by the clock signal or the clock inversion signal; And
A data control switching unit controlling the first or second data signal to control a plurality of outputs output from the clock control switching unit;
High speed communication multiplexer comprising a. The method of claim 4, wherein the clock control switching unit,
And a plurality of switching elements controlled in said clock signal and connected in parallel to turn on in different operating regions. The method of claim 4, wherein the data control switching unit,
A plurality of switching element groups controlled by the first or second data signal and independently connected to each other between the plurality of switching elements in the clock control switching unit and the ground to individually control the output of the plurality of switching elements; Multiplexer for high speed communications, including. 2. The apparatus according to claim 1,
And outputting a potential difference between a real data signal corresponding to a first data signal of the at least two data signals and a dummy data signal corresponding to a second data signal of the at least two or more data signals. The method according to claim 6,
A first switching device group of the plurality of switching device groups is controlled to the first data signal, and a second switching device group of the sixth plurality of switching device groups is a second data advance ahead of the second data signal. And a phase of the first data signal and a phase of the second data enhancement signal are controlled by a signal. The method of claim 1,
The swing width of the real data signal is 2 to 5 times larger than the swing width of the dummy data signal multiplexer for communication. The method of claim 8, wherein the second data delay signal delayed by a predetermined time from the second data advance signal is generated by a latch,
The latch
A sensing unit configured to sense the second data signal;
A holding unit for changing the voltage level of the second data signal,
And the sensing unit forms a path driven by the sum of the currents of the sensing unit and the current source of the holding unit in synchronization with the first edge of the clock signal. A delay unit configured to delay the first and second data signals having different phases by 90 degrees and output the first and second real data signals and the first and second dummy data signals, respectively;
A clock control switching unit controlled by a clock signal or a clock inversion signal and operating in different operating regions;
Data that is a pair of the first real data signal or the second dummy data signal, respectively, or is controlled by a pair of the second real data signal or the first dummy data signal, and outputs a pair of data signals having different voltage levels. Control switching unit; And
Output means for outputting a potential difference of a pair of data signals having different voltage levels
Multiplexer for high speed communication comprising a. 12. The method of claim 11,
And the first real data signal and the second dummy data signal are converted simultaneously and synchronously. The method of claim 11, wherein the clock control switching unit,
And a plurality of switching elements controlled in said clock signal and connected in parallel to turn on in different operating regions. The method of claim 11, wherein the data control switching unit,
And a plurality of switching element groups independently connected between a plurality of switching elements in the clock control switching unit and a ground to individually control the outputs of the plurality of switching elements. The method of claim 11, wherein the output means,
And outputting a potential difference between the first real data signal and the second dummy data signal. 12. The method of claim 11,
The swing width of the first real data signal is 2 to 5 times larger than the swing width of the second dummy data signal, multiplexer for high speed communication.

Images