JP2012231394A - Phase interpolation circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the linearity of phase interpolation.SOLUTION: A phase interpolation circuit includes: a first drive circuit adjusted in driving force by a first control signal to generate a first current corresponding to the driving force set by the first control signal in accordance with a first clock; a second drive circuit adjusted in driving force by a second control signal to generate a second current corresponding to the driving force set by the second control signal in accordance with a second clock delayed in phase from the first clock; and an adjustment section for generating a third current for canceling the second current when the levels of the first clock and the second clock are different from each other. The driving force of the first drive circuit and the driving force of the second drive circuit are set such that the sum of the first current and the second current is constant.

Description

  The present invention relates to a phase interpolation circuit and a semiconductor device.

  Various methods for adjusting the phase and frequency of a clock have been proposed for a clock synchronous semiconductor integrated circuit (for example, Patent Document 1, Patent Document 2, and Patent Document 3). For example, a phase interpolation circuit that adjusts the phase of a clock receives two clocks having different phases and outputs a clock obtained by interpolating the phases of the two clocks. The phase interpolation circuit includes, for example, an inverter (hereinafter also referred to as an early inverter) that receives a relatively advanced phase clock (hereinafter also referred to as an early clock) and a relatively delayed phase clock (hereinafter referred to as a slow clock). An inverter (hereinafter also referred to as a slow-side inverter).

  The output of the early side inverter and the output of the late side inverter are connected to a common node. As a result, a clock obtained by interpolating the phases of the two clocks is output to the common node. In this type of phase interpolation circuit, a through current flows when the levels of the two clocks are different.

  In recent years, a phase interpolation circuit that prevents a through current has been proposed (for example, Patent Document 4). In the phase interpolation circuit that prevents the through current, for example, each inverter of the early side inverter and the late side inverter has two pMOS transistors and two nMOS transistors connected in series between the power source and the ground line. Note that the slow inverter receives, for example, both a fast clock and a slow clock.

  For example, the slow-side inverter receives one of two clocks at the gates of a pMOS transistor and an nMOS transistor whose drains are connected to each other, and receives the other clock at the gates of the remaining pMOS transistor and nMOS transistor. As a result, when the levels of the two clocks are different, one of the two pMOS transistors and one of the two nMOS transistors are turned off in the slow-side inverter.

JP 2001-273048 A JP 2002-215262 A JP 2003-124787 A JP 2004-129110 A

  When performing fine phase adjustment with variable weighting of the driving force of the fast side inverter and the slow side inverter, in a general phase interpolation circuit, linearity of phase interpolation with respect to weighting deteriorates due to through current. For example, when the early clock changes from a high level to a low level, the pMOS transistor of the early inverter is turned on. At this time, since the nMOS transistor of the slow inverter is turned on, a through current flows from the pMOS transistor of the fast inverter to the nMOS transistor of the slow inverter. The drive current (current for driving the load) of the faster inverter is reduced by the through current. For this reason, in the period when the through current flows, the early inverter drives the load with a driving force smaller than the set driving force. For this reason, the linearity of the phase interpolation with respect to the weighting of the driving force deteriorates.

  Note that the phase interpolation circuit that prevents the through current does not perform fine phase adjustment with variable weighting of the driving force of the two inverters. For example, in a phase interpolation circuit that prevents a through current, a clock having a phase (for example, an intermediate phase between two clocks) based on a preset fixed weight is generated.

  An object of the present invention is to improve the linearity of phase interpolation.

  In one aspect of the present invention, the phase interpolation circuit adjusts the driving force by the first control signal, and generates a first current corresponding to the driving force set by the first control signal according to the first clock. The driving force is adjusted by one driving circuit and the second control signal, and the second current corresponding to the driving force set by the second control signal is set according to the second clock whose phase is delayed compared to the first clock. A second driving circuit to be generated; and an adjustment unit that generates a third current for canceling the second current when the levels of the first clock and the second clock are different from each other. The driving force of the second driving circuit is set so that the sum of the first current and the second current is constant.

  The linearity of phase interpolation can be improved.

2 illustrates an example of a phase interpolation circuit in an embodiment. 2 illustrates an example of a drive circuit and an offset circuit illustrated in FIG. An example of the inverter shown in FIG. 2 is shown. An example of the operation of the phase interpolation circuit shown in FIG. 1 is shown. 3 shows an example of the relationship between the number of ONs of the inverter shown in FIG. 2 and the delay time. An example of the phase interpolation circuit in another embodiment is shown. 7 shows an example of a drive circuit and an offset circuit shown in FIG. An example of the phase interpolation circuit in another embodiment is shown. 2 shows an example of a semiconductor device on which the phase interpolation circuit of the above-described embodiment is mounted.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an example of a phase interpolation circuit PI in one embodiment. For example, the phase interpolation circuit PI adjusts the phase of a clock of a data transmission / reception circuit that performs data transmission / reception between modules in an LSI chip and data transmission / reception between LSIs. For example, the phase interpolation circuit PI adjusts the phase of the clock of the memory interface circuit in the server or personal computer.

  Phase interpolation circuit PI has a drive circuit 10 that receives clock CLK10 and control signal CNTA, a drive circuit 20 that receives clock CLK20 and control signal CNTB, and an offset circuit 30 that receives clock CLK10. The clock CLK20 is a clock with a phase lag compared to the clock CLK10.

  The outputs of the drive circuits 10 and 20 and the offset circuit 30 are connected to a common output terminal PIOUT, for example. Hereinafter, the voltage of the output terminal PIOUT is also referred to as an output voltage PIOUT. For example, as shown in FIG. 9, an output buffer such as an inverter is connected to the output terminal PIOUT.

  The driving force of the driving circuit 10 is variably set by the control signal CNTA, for example. Then, the drive circuit 10 generates a current corresponding to the set driving force according to the clock CLK10. Thereby, for example, the drive circuit 10 charges and discharges the load capacitance of the output terminal PIOUT according to the clock CLK10.

  For example, the driving force of the driving circuit 20 is variably set by the control signal CNTB. Then, the drive circuit 20 generates a current corresponding to the set driving force in accordance with the clock CLK20. Thereby, for example, the drive circuit 20 charges and discharges the load capacitance of the output terminal PIOUT according to the clock CLK20.

  For example, the driving force of the driving circuit 20 is set to the driving circuit 10 so that the sum of the driving force set to the driving circuit 10 and the driving force set to the driving circuit 20 is constant. Is set according to That is, the driving power of the driving circuit 10 and the driving power of the driving circuit 20 are set so that, for example, the sum of the current of the driving circuit 10 and the current of the driving circuit 20 is constant.

  The offset circuit 30 generates a current for canceling the current of the drive circuit 20 when the levels of the clocks CLK10 and CLK20 are different from each other. That is, the offset circuit 30 functions as an adjustment unit that generates a current for canceling the current of the drive circuit 20 when the levels of the clocks CLK10 and CLK20 are different from each other. For example, the offset circuit 30 supplies a current corresponding to the through current to the drive circuit 20.

  Thereby, in this embodiment, for example, it is possible to prevent the current for charging / discharging the load capacity of the output terminal PIOUT from becoming smaller than the current corresponding to the driving force set by the control signal CNTA. That is, in this embodiment, it is possible to prevent the driving force of the driving circuit 10 from becoming smaller than the driving force set by the control signal CNTA.

  FIG. 2 shows an example of the drive circuits 10 and 20 and the offset circuit 30 shown in FIG. The drive circuit 10 has n inverters INVE (INVE1, INVE2,..., INVEn) that receive the clock CLK10 in common (n is an integer of 2 or more).

  The output of each inverter INVE is connected to the output terminal PIOUT. Each inverter INVE is controlled to be turned on / off according to control signals EN and ENX received at control terminals GN and GP, respectively. The numbers at the end and “n” of the control signals EN and ENX correspond to the numbers at the end of the inverter INVE and “n”, respectively. The control signal ENX is, for example, an inverted signal of the control signal EN. Note that the control signals EN and ENX received by the inverter INVE correspond to the control signal CNTA shown in FIG.

  For example, the driving force of the driving circuit 10 is variably set by adjusting the number of inverters INVE to be turned on with the control signals EN and ENX. That is, the weighting of the driving force of the driving circuit 10 is set by setting the number of inverters INVE to be turned on by the control signals EN and ENX.

  The drive circuit 20 has n inverters INVL (INVL1, INVL2,..., INVLn) that receive the clock CLK20 in common. The output of each inverter INVL is connected to the output terminal PIOUT. Note that the number and “n” at the end of the inverter INVL correspond to the number and “n” at the end of the control signals EN and ENX, respectively. The configuration and driving force of each inverter INVL are the same as, for example, each inverter INVE.

  For example, each inverter INVL is controlled to be turned on / off according to control signals ENX and EN received at the control terminals GN and GP, respectively. The control terminal GN of the inverter INVL is connected to the control terminal GP of the inverter INVE, and the control terminal GP of the inverter INVL is connected to the control terminal GN of the inverter INVE. Therefore, the number of inverters INVL set to ON among n inverters INVL is the same as the number of inverters INVE set to OFF among n inverters INVE. For example, when m inverters INVE (m is an integer from 0 to n) are turned on, (nm) inverters INVL are turned on.

  Thus, the weight of the driving force of the driving circuit 20 is set according to the weight of the driving force of the driving circuit 10. For example, the driving force of the driving circuit 20 is variably set by adjusting the number of inverters INVL to be turned on with the control signals EN and ENX. Therefore, control signals EN and ENX received by inverter INVL correspond to control signal CNTB shown in FIG.

  The offset circuit 30 has an inverter INVC that receives the clock CLK10. The driving power of the inverter INVC is equal to or greater than the total driving power of the n inverters INVL (driving power of the driving circuit 20). For example, the configuration of the inverter INVC is the same as that of the inverter INVE except for the size of the transistor. The control terminal GN of the inverter INVC is connected to the power supply VDD, and the control terminal GP of the inverter INVC is grounded. As a result, the inverter INVC is maintained in the on state.

  Note that the configuration of the inverter INVC may be different from that of the inverter INVE. The offset circuit 30 may include n or more inverters having the same size as the inverter INVE, and may include n inverters having the same size as the inverter INVE.

  FIG. 3 shows an example of the inverters INVE, INVL, INVC shown in FIG. The dashed arrows in FIG. 3 show an example of current that flows when the clocks CLK10 and CLK20 are at a low level and a high level, respectively.

  Each inverter INVE includes pMOS transistors MP10 and MP20 and nMOS transistors MN20 and MN10 connected in series between a power supply VDD and a ground line (a power supply line to which a ground voltage is supplied). For example, the pMOS transistor MP10 has a source connected to the power supply VDD, a drain connected to the source of the pMOS transistor MP20, and a gate connected to the gate of the nMOS transistor MN10. The pMOS transistor MP10 receives the clock CLK10 at the gate.

  In the pMOS transistor MP20, the drain is connected to the output terminal PIOUT and the drain of the nMOS transistor MN20, and the gate is connected to the control terminal GP. The nMOS transistor MN20 has a source connected to the drain of the nMOS transistor MN10 and a gate connected to the control terminal GN. That is, the nMOS transistor MN20 and the pMOS transistor MP20 function as a switch for turning on / off the inverter INVE according to the control signals EN and ENX.

  The source of the nMOS transistor MN10 is grounded. The nMOS transistor MN10 receives the clock CLK10 at the gate. That is, the nMOS transistor MN10 and the pMOS transistor MP10 receive a common clock CLK10 at their gates. For example, the nMOS transistor MN10 and the pMOS transistor MP10 function as an inverter that receives the clock CLK10.

  The configuration of the inverter INVL is the same as that of the inverter INVE. For example, the nMOS transistor MN10 and the pMOS transistor MP10 function as an inverter that receives the clock CLK20. For example, the nMOS transistor MN20 and the pMOS transistor MP20 function as switches that turn on / off the inverter INVE in accordance with the control signals ENX, EN.

  Note that the gate of the nMOS transistor MN20 of the inverter INVL is connected to the gate of the pMOS transistor MP20 of the inverter INVE. The gate of the pMOS transistor MP20 of the inverter INVL is connected to the gate of the nMOS transistor MN20 of the inverter INVE. Therefore, in the combination of inverters INVE and INVL having the same number at the end of the code, when one is on, the other is off. For example, when m inverters INVE are on, (n−m) inverters INVL are on.

  The inverter INVC includes pMOS transistors MP12 and MP22 and nMOS transistors MN22 and MN12 connected in series between the power supply VDD and the ground line. The configuration of the inverter INVC is the same as that of the inverter INVE except for the sizes (gate width / gate length) of the transistors MN12, MN22, MP12, and MP22. For example, the size of each transistor MN12, MN22, MP12, MP22 is n times or more the size of each transistor MN10, MN20, MP10, MP20.

  As a result, the inverter INVC has a driving force that is equal to or greater than the sum of the driving forces of the n inverters INVE (the driving force of the driving circuit 10 and the driving circuit 20). The nMOS transistor MN12 may be formed by n or more nMOS transistors MN10, and the nMOS transistor MN22 may be formed by n or more nMOS transistors MN20. The pMOS transistor MP12 may be formed of n or more pMOS transistors MP10, and the pMOS transistor MP22 may be formed of n or more pMOS transistors MP20.

For example, when the size of the transistors MN12, MN22, MP12, and MP22 of the inverter INVC is n times that of the transistors MN10, MN20, MP10, and MP20 of the inverter INVE, the current ICD generated by the offset circuit 30 is expressed by Expression (1). Is done. Note that Id in Expression (1) is a current generated by one inverter INVE.
ICD = n · Id (1)
Further, when m inverters INVE (m is an integer of 0 or more and n or less) are turned on, the currents IED and ILD generated by the drive circuits 10 and 20 are expressed by equations (2) and (3), respectively. expressed.
IED = m · Id (2)
ILD = (nm) · Id (3)
For example, when the clocks CLK10 and CLK20 are at a low level and a high level, respectively, the pMOS transistor MP12 of the inverter INVC, the pMOS transistor MP10 of the inverter INVE, and the nMOS transistor MN10 of the inverter INVL are turned on. Therefore, of the currents ICD and IED, the current ILD corresponding to the through current is supplied to the drive circuit 20, and the remaining current is supplied to the output terminal PIOUT.

Therefore, when the clocks CLK10 and CLK20 are at a low level and a high level, respectively, the current IDR supplied to the output terminal PIOUT is expressed by Expression (4). When the clocks CLK10 and CLK20 are at a low level and a high level, respectively, the current IDR in Expression (4) is drawn from the output terminal PIOUT.
IDR = ICD + IED−ILD = 2 · m · Id (4)
Further, when the clocks CLK10 and CLK20 are both at a low level, the current IDR2 supplied to the output terminal PIOUT is expressed by Expression (5). When both the clocks CLK10 and CLK20 are at a high level, the current IDR2 of Expression (5) is drawn from the output terminal PIOUT.
IDR2 = ICD + IED + ILD = 2 · n · Id (5)
Thus, for example, in a period in which the levels of the clocks CLK10 and CLK20 are different from each other, the current IDR for charging and discharging the load capacitance of the output terminal PIOUT increases in proportion to the number “m” of inverters INVE to be turned on. Further, during the period in which the levels of the clocks CLK10 and CLK20 are the same, the current IDR2 that charges and discharges the load capacitance of the output terminal PIOUT is kept constant regardless of the number “m” of the inverters INVE to be turned on. Therefore, in this embodiment, the current for charging / discharging the load capacitance of the output terminal PIOUT can be accurately controlled by variably setting the number “m” of the inverters INVE to be turned on. Thereby, in this embodiment, it can prevent that the linearity of phase interpolation deteriorates by the influence of a through current.

  Note that the configuration of the phase interpolation circuit PI is not limited to this example. For example, in the inverters INVE and INVL, the signals received at the gates may be reversed by the pMOS transistors MP10 and MP20, and the signals received at the gates may be reversed by the nMOS transistors MN10 and MN20. In the inverter INVC, the signal received at the gate may be reversed by the pMOS transistors MP12 and MP22, and the signal received at the gate may be reversed by the nMOS transistors MN12 and MN22.

  Further, the phase interpolation circuit PI may include, for example, a dummy nMOS transistor and a pMOS transistor that receive the clock CLK20 at the gate. For example, a dummy nMOS transistor has its source and drain grounded. For example, the dummy pMOS transistor has a source and a drain connected to the power supply VDD.

  The sizes of the dummy nMOS transistor and the pMOS transistor are the same as, for example, the nMOS transistor MN12 and the pMOS transistor MP12. In this case, since the input loads of the clocks CLK10 and CLK20 are the same, for example, it is possible to prevent a difference in the slew rates of the drive circuits 10 and 20.

  FIG. 4 shows an example of the operation of the phase interpolation circuit PI shown in FIG. FIG. 4 shows an example of the operation of the phase interpolation circuit PI when the number of inverters INVE is eight (n = 8). The solid line of the output voltage PIOUT in the figure indicates the output voltage PIOUT when all the inverters INVE are set to ON (m = n = 8), and the broken line of the output voltage PIOUT indicates that all the inverters INVE are set to OFF. The output voltage PIOUT is shown (m = 0). In addition, waveforms (voltages OUT10,..., OUT18) in parentheses in the figure indicate the output of an inverter (for example, the output buffer OBUF shown in FIG. 9) connected to the output terminal PIOUT, for example. Hereinafter, the inverter connected to the output terminal PIOUT is also referred to as an output buffer.

  For example, the voltage OUT10 indicates the output of the output buffer when all the inverters INVE are set to ON (m = n). For example, the voltage OUT18 indicates the output of the output buffer when all the inverters INVE are set to OFF (m = 0). In the example of FIG. 4, the threshold voltage of the inverter connected to the output terminal PIOUT is half of the power supply VDD.

  First, at time T10, the clock CLK10 changes from a high level to a low level, and the clock CLK20 is maintained at a high level. For this reason, the nMOS transistor MN12 of the inverter INVC and the nMOS transistor MN10 of the inverter INVE are turned off. Then, the pMOS transistor MP12 of the inverter INVC and the pMOS transistor MP10 of the inverter INVE are turned on. Further, the nMOS transistor MN10 of the inverter INVL is maintained in the on state, and the pMOS transistor MP10 of the inverter INVL is maintained in the off state. Therefore, the current IDR shown in the equation (4) is supplied to the output terminal PIOUT.

  For example, when all inverters INVE are set to ON (m = n), the output voltage PIOUT has a slope based on the current IDR (IDR = 2 · n · Id) and the load capacity of the output terminal PIOUT, It rises with progress. In a period in which the output voltage PIOUT is lower than the threshold voltage (VDD / 2) of the output buffer (period before time T12), the voltage OUT10 is maintained at a high level.

  Note that the output voltage PIOUT when all the inverters INVE are set to OFF (m = 0) is maintained at the ground voltage GND because the current IDR is not supplied to the output terminal PIOUT. Therefore, at time T10, the voltage OUT18 is maintained at a high level.

  At time T12, the clock CLK10 is maintained at a low level, and the clock CLK20 changes from a high level to a low level. For this reason, the nMOS transistor MN12 of the inverter INVC and the nMOS transistor MN10 of the inverter INVE are maintained in the off state. Further, the pMOS transistor MP12 of the inverter INVC and the pMOS transistor MP10 of the inverter INVE are maintained in the on state. Then, the nMOS transistor MN10 of the inverter INVL is turned off, and the pMOS transistor MP10 of the inverter INVL is turned on. Therefore, the current IDR2 shown in the equation (5) is supplied to the output terminal PIOUT.

  For example, when all the inverters INVE are set to ON, the current IDR2 is the same as the current IDR. For this reason, the output voltage PIOUT increases with the passage of time with the same slope as before time T12 after time T12. For example, during the period from time T10 to time T12, the output voltage PIOUT rises from the ground voltage GND to half of the power supply VDD. After time T12, the output voltage PIOUT rises from a half of the power supply VDD to the power supply VDD.

  Therefore, at time T12, the output voltage PIOUT rises to the threshold voltage (VDD / 2) of the output buffer. As a result, the voltage OUT10 changes from a high level to a low level. That is, the voltage OUT10 changes to the low level after the time TD10 has elapsed from the time T10 when the clock CLK10 changes from the high level to the low level.

  Note that the output voltage PIOUT when all the inverters INVE are set to OFF is a slope based on the current IDR2 (IDR2 = 2 · n · Id) and the load capacity of the output terminal PIOUT, and the power supply VDD increases with time. To rise. In a period in which the output voltage PIOUT is lower than the threshold voltage (VDD / 2) of the output buffer, the voltage OUT18 is maintained at a high level. When the output voltage PIOUT rises to the threshold voltage (VDD / 2) of the output buffer, the voltage OUT18 changes from a high level to a low level. For example, the voltage OUT18 changes to the low level after the time TD18 has elapsed from the time T10 when the clock CLK10 changes from the high level to the low level.

  At time T20, the clock CLK10 changes from the low level to the high level, and the clock CLK20 is maintained at the low level. For this reason, the nMOS transistor MN12 of the inverter INVC and the nMOS transistor MN10 of the inverter INVE are turned on. Then, the pMOS transistor MP12 of the inverter INVC and the pMOS transistor MP10 of the inverter INVE are turned off. Further, the nMOS transistor MN10 of the inverter INVL is maintained in the off state, and the pMOS transistor MP10 of the inverter INVL is maintained in the on state. Therefore, the current IDR shown in the equation (4) is drawn from the output terminal PIOUT.

  For example, the output voltage PIOUT when all the inverters INVE are set to ON has a slope based on the current IDR (IDR = 2 · n · Id) and the load capacity of the output terminal PIOUT, and decreases with time. . In a period in which the output voltage PIOUT is higher than the threshold voltage (VDD / 2) of the output buffer (period before time T22), the voltage OUT10 is maintained at a low level.

  Note that the output voltage PIOUT when all the inverters INVE are set to OFF is maintained at the power supply VDD because the current IDR is not extracted from the output terminal PIOUT. Therefore, at time T20, the voltage OUT18 is maintained at a low level.

  At time T22, the clock CLK10 is maintained at a high level, and the clock CLK20 changes from a low level to a high level. For this reason, the nMOS transistor MN12 of the inverter INVC and the nMOS transistor MN10 of the inverter INVE are maintained in the on state. Further, the pMOS transistor MP12 of the inverter INVC and the pMOS transistor MP10 of the inverter INVE are maintained in the off state. Then, the nMOS transistor MN10 of the inverter INVL is turned on, and the pMOS transistor MP10 of the inverter INVL is turned off. Therefore, the current IDR2 shown in the equation (5) is drawn from the output terminal PIOUT.

  For example, when all the inverters INVE are set to ON, the current IDR2 is the same as the current IDR. For this reason, the output voltage PIOUT decreases with the passage of time with the same slope as before time T22 after time T22. For example, in the period from time T20 to time T22, the output voltage PIOUT drops from the power supply VDD to half of the power supply VDD. Then, after time T22, the output voltage PIOUT drops from a half of the power supply VDD to the ground voltage GND.

  Therefore, at time T22, the output voltage PIOUT drops to the threshold voltage (VDD / 2) of the output buffer. As a result, the voltage OUT10 changes from a low level to a high level. That is, voltage OUT10 changes to high level after time TD10 has elapsed from time T20 when clock CLK10 changed from low level to high level.

  The output voltage PIOUT when all the inverters INVE are set to OFF is a slope based on the current IDR2 (IDR2 = 2 · n · Id) and the load capacity of the output terminal PIOUT, and the ground voltage with time. Descent to GND. In a period in which the output voltage PIOUT is higher than the threshold voltage (VDD / 2) of the output buffer, the voltage OUT18 is maintained at a low level. When the output voltage PIOUT drops to the threshold voltage (VDD / 2) of the output buffer, the voltage OUT18 changes from the low level to the high level. For example, voltage OUT18 changes to high level after time TD18 has elapsed from time T20 when clock CLK10 changes from low level to high level.

  As described above, the delay time TD (TD10, TD18) of the voltage OUT with respect to the clock CLK10 changes according to the number “m” of the inverters INVE to be turned on. For example, the delay time TD10 when all the inverters INVE are set to ON is the minimum delay time with respect to the clock CLK10. The delay time TD18 when all the inverters INVE are set to OFF is the maximum delay time with respect to the clock CLK10. In this embodiment, as shown in FIG. 5, the delay time between the delay time TD10 and the delay time TD18 can be set by adjusting the number “m” of the inverters INVE to be turned on.

  FIG. 5 shows an example of the relationship between the number of ONs of the inverter INVE shown in FIG. 2 and the delay time. FIG. 5 shows an example of the relationship between the number “m” of ONs of the inverter INVE and the delay time TD when the number of inverters INVE is eight (n = 8). In the example of FIG. 5, the size of the transistors MN12, MN22, MP12, and MP22 of the inverter INVC is eight times (n times) that of the transistors MN10, MN20, MP10, and MP20 of the inverter INVE.

  The delay time TD (TD10-TD18) of the output voltage PIOUT until it reaches one-half of the power supply voltage VDD increases with a decrease in the number “m” of ON of the inverter INVE. Here, for example, “m = 8” in the figure indicates the output voltage PIOUT when all (eight) inverters INVE are set to ON and all (eight) inverters INVL are set to OFF. ing. For example, “m = 7” indicates the output voltage PIOUT when seven inverters INVE are set to ON and one inverter INVL is set to ON.

In the period from the time T10 to the time T12, the current of the drive circuit 20 is canceled out, so that the current IDR (IDR = 2 · m · Id) expressed by the equation (4) is supplied to the output terminal PIOUT. Therefore, the current IDR supplied to the output terminal PIOUT increases in proportion to the number “m” of ON of the inverter INVE. Therefore, the output voltage PIOUT at time T12 increases in proportion to the number “m” of ON of the inverter INVE, as shown in the equation (6). Here, Vt12 in Expression (6) represents the output voltage PIOUT at time T12. Further, “C” in Expression (6) is the load capacitance of the output terminal PIOUT, and TD10 is the time from time T10 to time T12.
Vt12 = IDR · TD10 / C = 2 · m · Id · TD10 / C (6)
After time T12, the current IDR2 (IDR = 2 · n · Id) shown in the equation (5) is supplied to the output terminal PIOUT. Therefore, when the number “n” of the inverters INVE and INVL of the drive circuits 10 and 20 is constant, the current IDR supplied to the output terminal PIOUT is constant regardless of the number “m” of ON of the inverter INVE. For this reason, after time T12, the output voltage PIOUT rises to the power supply VDD with a constant slope regardless of the number “m” of ON of the inverter INVE.

Therefore, the relationship between “m” and the delay time TD of the output voltage PIOUT reaching one half of the power supply voltage VDD is expressed by Expression (7).
IDR2 · (TD−TD10) = C · (VDD / 2−Vt12) (7)
In the example of FIG. 5, when all the inverters INVE are set to ON (m = n), the output voltage PIOUT reaches half of the power supply voltage VDD at time TD10. Therefore, by substituting VDD / 2 and “n” into Vt12 and “m” in equation (6), equation (8) is given. The delay time TD is given by equation (9) based on equations (6), (7), and (8).
VDD / 2 = 2 · n · Id · TD10 / C (8)
TD = TD10 (1+ (nm) / n) (9)
“N−m” in Expression (9) corresponds to the number of inverters INVE turned off. That is, the delay time TD increases with an increase in the number of inverters INVE turned off. The delay time TD10 corresponds to the delay time of the clock CLK20 with respect to the clock CLK10. Therefore, in this embodiment, the delay time TD can be accurately adjusted in steps of 1 / n of the delay time TD10. In other words, in this embodiment, the clock phase can be accurately adjusted in a step of 1 / n of the phase difference between the clocks CLK10 and CLK20.

  Note that the inverters INVE, INVL, and INVC are designed so that the output voltage PIOUT does not exceed a threshold voltage (for example, VDD / 2) before the CLK20 changes after the clock CLK10 changes. For example, the inverters INVE, INVL, and INVC are designed so that the output voltage PIOUT at time T12 does not exceed the threshold voltage (VDD / 2) even when all the inverters INVE are set to ON. If this condition is satisfied, the phase of the clock is changed even when the size of the transistors MN12, MN22, MP12, and MP22 of the inverter INVC is eight times (n times) that of the transistors MN10, MN20, MP10, and MP20 of the inverter INVE. It can be adjusted accurately.

  As described above, in this embodiment, the phase interpolation circuit PI includes the offset circuit 30 that generates a current for canceling the current of the drive circuit 20. For example, the offset circuit 30 generates a current for canceling the current of the drive circuit 20 when the levels of the clocks CLK10 and CLK20 are different from each other. Thus, in this embodiment, when the levels of the clocks CLK10 and CLK20 are different from each other, the load capacitance of the output terminal PIOUT can be charged / discharged with a current proportional to the number “m” of ONs of the inverter INVE of the drive circuit 10. That is, in this embodiment, the clock phase can be accurately adjusted by adjusting the number “m” of ONs of the inverter INVE of the drive circuit 10. As a result, in this embodiment, the linearity of phase interpolation can be improved.

  FIG. 6 shows an example of the phase interpolation circuit PI in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The phase interpolation circuit PI of this embodiment has a drive circuit 22 and an offset circuit 32 instead of the drive circuit 20 and the offset circuit 30 shown in FIG. Other configurations are the same as those of the above-described embodiment. For example, the phase interpolation circuit PI adjusts the phase of the clock of the memory interface circuit in the server or personal computer.

  The phase interpolation circuit PI includes drive circuits 10 and 22 and an offset circuit 32. For example, the outputs of the drive circuits 10 and 22 and the offset circuit 32 are connected to a common output terminal PIOUT. For example, the drive circuit 10 generates a current corresponding to the driving force set by the control signal CNTA according to the clock CLK10. Thereby, for example, the drive circuit 10 charges and discharges the load capacitance of the output terminal PIOUT according to the clock CLK10.

  Drive circuit 22 receives clock CLK20 and control signal CNTB. For example, the driving force of the driving circuit 22 is variably set by the control signal CNTB. Then, the drive circuit 22 generates a current corresponding to the set driving force in accordance with the clock CLK20. Thereby, for example, the drive circuit 22 charges and discharges the load capacity of the output terminal PIOUT according to the clock CLK20. The clock CLK20 is a clock with a phase lag compared to the clock CLK10.

  Offset circuit 32 receives clock CLK10 and control signal CNTB. For example, the driving force of the offset circuit 32 is variably set by the control signal CNTB. The offset circuit 32 generates a current for canceling the current of the drive circuit 22 when the levels of the clocks CLK10 and CLK20 are different from each other. For example, the offset circuit 32 supplies a current corresponding to the through current to the drive circuit 22. Thereby, in this embodiment, for example, it is possible to prevent the current for charging / discharging the load capacity of the output terminal PIOUT from becoming smaller than the current corresponding to the driving force set by the control signal CNTA. That is, in this embodiment, it is possible to prevent the driving force of the driving circuit 10 from becoming smaller than the driving force set by the control signal CNTA.

  FIG. 7 shows an example of the drive circuits 10 and 22 and the offset circuit 32 shown in FIG. The dashed arrows in FIG. 7 show an example of currents that flow when the clocks CLK10 and CLK20 are at a low level and a high level, respectively. The numbers at the end of the inverter INVE, the drive units NDRV and PDRV, the control signals EN and ENX, and the meaning of “n” are the same as those in FIG. The drive circuit 10 is the same as the drive circuit 10 shown in FIG. Therefore, the control signals EN and ENX received by the inverter INVE correspond to the control signal CNTA shown in FIG.

  The drive circuit 22 includes n drive units NDRV (NDRV1, NDRV2,..., NDRVn) that receive the clock CLK20 in common. The drive unit NDRV corresponds to, for example, a circuit on the ground line side of the inverter INVL illustrated in FIG. For example, each drive unit NDRV includes nMOS transistors MN20 and MN10 connected in series between the output terminal PIOUT and the ground line.

  The nMOS transistor MN10 receives the clock CLK20 at the gate. The gate of the nMOS transistor MN20 is connected to the control terminal GN. That is, the nMOS transistor MN20 functions as a switch for turning on / off the drive unit NDRV in accordance with the control signal ENX. The control signal ENX received by the drive unit NDRV is included in the control signal CNTB shown in FIG.

  For example, when the driving unit NDRV is set to ON by the control signal ENX, the driving unit NDRV draws current from the output terminal PIOUT in accordance with the clock CLK20. That is, the drive unit NDRV functions as a current generation unit that draws current from the output terminal PIOUT in accordance with the clock CLK20.

  The offset circuit 32 has n drive units PDRV (PDRV1, PDRV2,..., PDRVn) that receive the clock CLK10 in common. The drive unit PDRV corresponds to, for example, a circuit on the power supply VDD side of the inverter INVL illustrated in FIG. For example, each drive unit PDRV includes pMOS transistors MP10 and MP20 connected in series between the power supply VDD and the output terminal PIOUT.

  The pMOS transistor MP10 receives the clock CLK10 at the gate. The gate of the pMOS transistor MP20 is connected to the control terminal GP. That is, the pMOS transistor MP20 functions as a switch for turning on / off the drive unit PDRV in accordance with the control signal EN. For example, the control signal EN received by the drive unit PDRV is included in the control signal CNTB shown in FIG. Since the control signal ENX is an inverted signal of the control signal EN, the number of ON of the drive unit PDRV is the same as the number of ON of the drive unit NDRV.

  For example, when the driving unit PDRV is turned on by the control signal EN, the driving unit PDRV supplies a current to the output terminal PIOUT according to the clock CLK10. That is, the drive unit PDRV functions as a current generation unit that supplies current to the output terminal PIOUT according to the clock CLK10.

  The control terminal GN of the drive unit NDRV is connected to the control terminal GP of the inverter INVE, and the control terminal GP of the drive unit PDRV is connected to the control terminal GN of the inverter INVE. Therefore, the number of drive units NDRV set to ON and the number of drive units PDRV set to ON are the same as the number of inverters INVE set to OFF among n inverters INVE. For example, when m (m is an integer of 0 to n) inverters INVE are turned on, (nm) drive units NDRV and (n−m) drive units PDRV are turned on.

  Thus, the weighting of the driving force of the driving circuit 22 and the offset circuit 32 is set according to the weighting of the driving force of the driving circuit 10. For example, the drive power of the drive circuit 22 and the offset circuit 32 is variably set by adjusting the number of drive units NDRV and PDRV to be turned on with the control signals ENX and EN. Therefore, control signal ENX received by drive unit NDRV and control signal EN received by drive unit PDRV correspond to control signal CNTB shown in FIG.

  Here, for example, the driving force of each driving unit NDRV and each driving unit PDRV is the same as that of each inverter INVE. Thus, for example, the offset circuit 32 (more specifically, the drive unit PDRV set to ON) is generated by the current ILD generated by the drive circuit 22 (more specifically, the drive unit NDRV set to ON). A current ICD corresponding to is generated.

  For example, the pMOS transistor MP10 of the drive unit PDRV and the nMOS transistor MN10 of the drive unit NDRV are turned on while the clocks CLK10 and CLK20 are at a low level and a high level, respectively. As a result, a current ICD that flows from the power supply VDD to the output terminal PIOUT is generated by the offset circuit 32, and a current ILD that flows from the output terminal PIOUT to the ground line is generated by the drive circuit 22. Thus, the current ILD generated by the drive circuit 22 is canceled by the current ICD generated by the offset circuit 32, for example.

  That is, the offset circuit 32 generates a current ICD for canceling the current ILD of the drive circuit 22 when the clocks CLK10 and CLK20 are at a low level and a high level, respectively. That is, the offset circuit 32 functions as an adjustment unit that generates a current ICD for canceling out the current ILD of the drive circuit 22 when the levels of the clocks CLK10 and CLK20 are different from each other. For example, during periods when the clocks CLK10 and CLK20 are at a low level and a high level, a current IDR corresponding to the current IED generated by the drive circuit 10 is supplied to the output terminal PIOUT.

  Note that the pMOS transistor MP10 of the drive unit PDRV and the nMOS transistor MN10 of the drive unit NDRV are turned off while the clocks CLK10 and CLK20 are at a high level and a low level, respectively. For this reason, the through current does not flow through the drive unit NDRV. Therefore, during periods when the clocks CLK10 and CLK20 are at a high level and a low level, a current IDR corresponding to the current IED generated by the drive circuit 10 is drawn from the output terminal PIOUT.

  That is, during a period in which the levels of the clocks CLK10 and CLK20 are different from each other, the load capacitance of the output terminal PIOUT is charged / discharged by the current IDR corresponding to the current IED generated by the drive circuit 10. The current IED is given by, for example, the equation (2) described with reference to FIG. 3 (IED = m · Id). Therefore, the current IDR increases in proportion to the number “m” of ON of the inverter INVE.

  Further, in a period in which both of the clocks CLK10 and CLK20 are at a low level, the pMOS transistor MP10 of the drive unit PDRV is turned on, and the nMOS transistor MN10 of the drive unit NDRV is turned off. Therefore, a current IDR corresponding to the sum of the current IED generated by the drive circuit 10 and the current ICD generated by the offset circuit 32 is supplied to the output terminal PIOUT.

  In this embodiment, since the current ICD is equal to the current ILD, the current ICD is given by, for example, the equation (3) described with reference to FIG. 3 (ICD = ILD = (nm) · Id). Accordingly, when both the clocks CLK10 and CLK20 are at a low level, when the number “n” of inverters INVE of the drive circuit 10 is constant, the current IDR supplied to the output terminal PIOUT is the number “m” of ON of the inverter INVE. Regardless of, it is constant.

  In a period in which both of the clocks CLK10 and CLK20 are at a high level, the pMOS transistor MP10 of the drive unit PDRV is turned off and the nMOS transistor MN10 of the drive unit NDRV is turned on. Therefore, a current IDR corresponding to the sum of the current IED generated by the drive circuit 10 and the current ILD generated by the drive circuit 22 is drawn from the output terminal PIOUT. The current ILD is given by, for example, the equation (3) described with reference to FIG.

  Therefore, in a period in which both of the clocks CLK10 and CLK20 are low, when the number “n” of inverters INVE of the drive circuit 10 is constant, the current IDR drawn from the output terminal PIOUT is equal to the number “m” of ON of the inverter INVE. Regardless, it is constant. That is, during a period in which the levels of the clocks CLK10 and CLK20 are the same, the load capacitance of the output terminal PIOUT is charged and discharged by a constant current (n · Id).

  Thus, in this embodiment, the current for charging / discharging the load capacitance of the output terminal PIOUT can be accurately controlled by variably setting the number “m” of the inverters INVE to be turned on. Thereby, in this embodiment, it can prevent that the linearity of phase interpolation deteriorates by the influence of a through current. That is, in this embodiment, the clock phase can be accurately controlled by variably setting the number “m” of inverters INVE to be turned on.

  Note that the configuration of the phase interpolation circuit PI is not limited to this example. For example, the signal received at the gate of the pMOS transistor MP10 and the signal received at the gate of the pMOS transistor MP20 may be reversed. Further, the signal received at the gate of the nMOS transistor MN10 and the signal received at the gate of the nMOS transistor MN20 may be reversed.

  Further, for example, the phase interpolation circuit PI may include two dummy pMOS transistors that receive the clock CLK20 at the gate for one nMOS transistor MN10. For example, the dummy pMOS transistor has a source and a drain connected to the power supply VDD. The sizes of the two dummy pMOS transistors are the same as, for example, the pMOS transistor MP10. In this case, since the input loads of the clocks CLK10 and CLK20 are the same, for example, it is possible to prevent a difference between the slew rates of the drive circuits 10 and 22.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, in this embodiment, the offset circuit 32 does not generate a current during a period in which the clock CLK10 is at a high level. For this reason, in this embodiment, the power consumption of the phase interpolation circuit PI can be suppressed.

  FIG. 8 shows an example of the phase interpolation circuit PI in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The dashed arrows in FIG. 8 show an example of currents that flow when the clocks CLK10 and CLK20 are at a high level and a low level, respectively. The numbers at the end of the inverter INVE, the drive units NDRV and PDRV, the control signals EN and ENX, and the meaning of “n” are the same as those in FIG.

  The phase interpolation circuit PI of this embodiment has a drive circuit 24 and an offset circuit 34 instead of the drive circuit 22 and the offset circuit 32 shown in FIG. Other configurations are the same as those of the embodiment described with reference to FIGS. For example, the phase interpolation circuit PI adjusts the phase of the clock of the memory interface circuit in the server or personal computer.

  The phase interpolation circuit PI includes drive circuits 10 and 24 and an offset circuit 34. For example, the outputs of the drive circuits 10 and 24 and the offset circuit 34 are connected to a common output terminal PIOUT. The drive circuit 24 is the same as the offset circuit 32 shown in FIG. 7 except that it receives the clock CLK20 instead of the clock CLK10. The offset circuit 34 is the same as the drive circuit 22 shown in FIG. 7 except that it receives the clock CLK10 instead of the clock CLK20.

  Therefore, for example, the pMOS transistor MP10 of the drive unit PDRV and the nMOS transistor MN10 of the drive unit NDRV are turned on while the clocks CLK10 and CLK20 are at a high level and a low level, respectively. During this period, the current ICD corresponding to the current ILD generated by the drive circuit 24 (more specifically, the drive unit PDRV set to ON) is set to the offset circuit 34 (more specifically, ON). Therefore, the current ILD of the drive circuit 24 is canceled out. That is, the offset circuit 34 functions as an adjustment unit that generates a current ICD for canceling the current ILD of the drive circuit 24 when the levels of the clocks CLK10 and CLK20 are different from each other.

  Note that the configuration of the phase interpolation circuit PI is not limited to this example. For example, the signal received at the gate of the pMOS transistor MP10 and the signal received at the gate of the pMOS transistor MP20 may be reversed. Further, the signal received at the gate of the nMOS transistor MN10 and the signal received at the gate of the nMOS transistor MN20 may be reversed.

  Further, for example, the phase interpolation circuit PI may include two dummy nMOS transistors that receive the clock CLK20 at the gate with respect to one pMOS transistor MP10. For example, a dummy nMOS transistor has its source and drain grounded. The sizes of the two dummy nMOS transistors are the same as, for example, the nMOS transistor MN10. In this case, since the input loads of the clocks CLK10 and CLK20 are the same, for example, it is possible to prevent a difference between the slew rates of the drive circuits 10 and 24.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 9 shows an example of a semiconductor device SYS on which the phase interpolation circuit PI of the above-described embodiment is mounted. The semiconductor device SYS includes, for example, a module 100 that includes transmission units 130 and 132 that transmit data, and a module 200 that includes reception units 210 and 212 that receive data. The module 100 includes, for example, phase interpolation units 110 and 112, a delay circuit 120, and transmission units 130 and 132. For example, the transmission units 130 and 132 form part of the memory interface circuit.

  Each of the phase interpolation units 110 and 112 includes a phase interpolation circuit PI, a control unit PCTL, and an output buffer OBUF. For example, the control unit PCTL controls the phase interpolation circuit PI using the control signals EN and ENX. For example, the control unit PCTL sets the control signals EN and ENX so that the phase of data received by the receiving unit 210 of the module 200 and the phase of data received by the receiving unit 212 are aligned. The output buffer OBUF is, for example, an inverter. The output buffer OBUF receives the output voltage PIOUT of the phase interpolation circuit PI and generates an output voltage OUT (hereinafter also referred to as clock OUT). For example, the output buffer OBUF of the phase interpolation unit 110 outputs the clock OUT to the transmission unit 130. Further, for example, the output buffer OBUF of the phase interpolation unit 112 outputs the clock OUT to the transmission unit 132.

  The delay circuit 120 receives the clock CLK10 and generates a clock CLK20 obtained by delaying the clock CLK10. Then, the delay circuit 120 outputs the clock CLK20 to the phase interpolation circuits PI of the phase interpolation units 110 and 112, respectively. The transmission unit 130 operates in synchronization with the clock OUT supplied from the phase interpolation unit 110 and transmits data to the reception unit 210 of the module 200. The transmission unit 132 operates in synchronization with the clock OUT supplied from the phase interpolation unit 112 and transmits data to the reception unit 212 of the module 200.

  The clock OUT output from the output buffer OBUF of each of the phase interpolation units 110 and 112 is a clock whose phase is adjusted by the phase interpolation circuit PI. Therefore, in the semiconductor device SYS, for example, even when the wiring length between the transmission unit 130 and the reception unit 210 is different from the wiring length between the transmission unit 132 and the reception unit 212, the data received by the reception unit 210 and the reception unit 212 are The phase shift from the received data can be reduced.

  The phase interpolation units 110 and 112 may be provided on the data receiving side (for example, the module 200). Modules 100 and 200 may be formed on different LSI chips or may be formed on the same LSI chip.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A first driving circuit that adjusts a driving force by a first control signal and generates a first current corresponding to the driving force set by the first control signal according to a first clock;
A driving force is adjusted by the second control signal, and a second current corresponding to the driving force set by the second control signal is generated according to a second clock that is delayed in phase from the first clock. Two drive circuits;
An adjustment unit that generates a third current for canceling out the second current when the levels of the first clock and the second clock are different from each other;
The phase interpolation circuit, wherein the driving force of the first driving circuit and the driving force of the second driving circuit are set such that a sum of the first current and the second current is constant.
(Appendix 2)
The first drive circuit includes:
N inverters (n is an integer greater than or equal to 2) that receive the first clock in common, have outputs connected to a common output node, and are individually controlled to be turned on / off by the first control signal;
The second driving circuit includes:
N inverters commonly receiving the second clock, having an output connected to the output node and individually controlled on / off by the second control signal;
The adjustment unit is
Receiving the first clock, having an output connected to the output node, and having a driving power equal to or greater than a total driving power of n inverters of the second driving circuit;
Of the n inverters of the second drive circuit, the number of inverters set to ON is the same as the number of inverters set to OFF of the n inverters of the first drive circuit. A characteristic phase interpolation circuit.
(Appendix 3)
The phase interpolation circuit according to claim 2, wherein the driving force of the adjusting unit is the same as the total driving force of n inverters of the second driving circuit.
(Appendix 4)
The first drive circuit includes:
N inverters (n is an integer greater than or equal to 2) that receive the first clock in common, have outputs connected to a common output node, and are individually controlled to be turned on / off by the first control signal;
One of the second drive circuit and the adjustment unit is
The power supply line is connected in parallel between the output node, current is supplied to the output node according to one of the first clock and the second clock, and ON / OFF is individually controlled by the second control signal. N first current generators to be
The other of the second drive circuit and the adjustment unit is
Connected in parallel between the output node and the ground line, draws current from the output node according to the other of the first clock and the second clock, and is individually controlled to be turned on / off by the second control signal N second current generators to be
The number of the first current generation units set to ON and the number of the second current generation units set to ON are the number of inverters set to OFF among n inverters of the first drive circuit. The phase interpolation circuit according to appendix 1, wherein the phase interpolation circuit is the same as
(Appendix 5)
The n first current generation units flow current into the output node according to the first clock,
The n second current generators are set to ON as many as the number of the first current generators set to ON, and draw current from the output node according to the second clock. The phase interpolation circuit according to appendix 4.
(Appendix 6)
The n first current generation units flow current into the output node according to the second clock,
The n second current generation units are set to ON by the same number as the number of the first current generation units set to ON, and draw current from the output node according to the first clock. The phase interpolation circuit according to appendix 4.
(Appendix 7)
A semiconductor device including a module including a phase interpolation circuit,
The phase interpolation circuit includes:
A first driving circuit that adjusts a driving force by a first control signal and generates a first current corresponding to the driving force set by the first control signal according to a first clock;
A driving force is adjusted by the second control signal, and a second current corresponding to the driving force set by the second control signal is generated according to a second clock that is delayed in phase from the first clock. Two drive circuits;
An adjustment unit that generates a third current for canceling out the second current when the levels of the first clock and the second clock are different from each other;
The driving force of the first driving circuit and the driving force of the second driving circuit are set so that the sum of the first current and the second current is constant.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  10, 20, 22, 24 ... drive circuit; 30, 32, 34 ... offset circuit; INVC, INVE, INVL ... inverter; MN10, MN12, MN20, MN22 ... nMOS transistor; MP10, MP12, MP20, MP22 ... pMOS transistor; NDRV, PDRV ... Driver

Claims (5)

A first driving circuit that adjusts a driving force by a first control signal and generates a first current corresponding to the driving force set by the first control signal according to a first clock;
A driving force is adjusted by the second control signal, and a second current corresponding to the driving force set by the second control signal is generated according to a second clock that is delayed in phase from the first clock. Two drive circuits;
An adjustment unit that generates a third current for canceling out the second current when the levels of the first clock and the second clock are different from each other;
The phase interpolation circuit, wherein the driving force of the first driving circuit and the driving force of the second driving circuit are set such that a sum of the first current and the second current is constant. The first drive circuit includes:
N inverters (n is an integer greater than or equal to 2) that receive the first clock in common, have outputs connected to a common output node, and are individually controlled to be turned on / off by the first control signal;
The second driving circuit includes:
N inverters commonly receiving the second clock, having an output connected to the output node and individually controlled on / off by the second control signal;
The adjustment unit is
Receiving the first clock, having an output connected to the output node, and having a driving power equal to or greater than a total driving power of n inverters of the second driving circuit;
Of the n inverters of the second drive circuit, the number of inverters set to ON is the same as the number of inverters set to OFF of the n inverters of the first drive circuit. A characteristic phase interpolation circuit. 3. The phase interpolation circuit according to claim 2, wherein a driving force of the adjustment unit is the same as a total driving force of n inverters of the second drive circuit. The first drive circuit includes:
N inverters (n is an integer greater than or equal to 2) that receive the first clock in common, have outputs connected to a common output node, and are individually controlled to be turned on / off by the first control signal;
One of the second drive circuit and the adjustment unit is
The power supply line is connected in parallel between the output node, current is supplied to the output node according to one of the first clock and the second clock, and ON / OFF is individually controlled by the second control signal. N first current generators to be
The other of the second drive circuit and the adjustment unit is
Connected in parallel between the output node and the ground line, draws current from the output node according to the other of the first clock and the second clock, and is individually controlled to be turned on / off by the second control signal N second current generators to be
The number of the first current generation units set to ON and the number of the second current generation units set to ON are the number of inverters set to OFF among n inverters of the first drive circuit. The phase interpolation circuit according to claim 1, wherein: A semiconductor device including a module including a phase interpolation circuit,
The phase interpolation circuit includes:
A first driving circuit that adjusts a driving force by a first control signal and generates a first current corresponding to the driving force set by the first control signal according to a first clock;
A driving force is adjusted by the second control signal, and a second current corresponding to the driving force set by the second control signal is generated according to a second clock that is delayed in phase from the first clock. Two drive circuits;
An adjustment unit that generates a third current for canceling out the second current when the levels of the first clock and the second clock are different from each other;
The driving force of the first driving circuit and the driving force of the second driving circuit are set so that the sum of the first current and the second current is constant.

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