KR20130087915A - Thin film transistor and the manufacturing method thereof - Google Patents

Abstract

PURPOSE: A thin film transistor and a manufacturing method thereof are provided to improve the reverse bias property of the thin film transistor by laminating a gate insulating layer of magnesium oxide on the upper part of a silicon oxide layer. CONSTITUTION: A gate (120) is formed on a substrate (110). A first gate insulating layer (130) is formed on the gate and the substrate in order to cover the gate. A second gate insulating layer (140) of magnesium oxide is formed on the first gate insulating layer. A semiconductor layer (150) is formed on the second gate insulating layer in order to correspond to the gate. A source and a drain electrode (160) are formed on the second gate insulating layer.

Description

Thin film transistor and its manufacturing method

The present invention relates to a thin film transistor and a method of manufacturing the same.

Thin film transistors are used in displays and various applications. In such a thin film transistor, an active layer including a source, a drain, and a channel region is formed of a semiconductor. The thin film transistor may be formed of an amorphous silicon thin film transistor, a polycrystalline silicon thin film transistor, an oxide semiconductor thin film transistor, or the like according to the semiconductor of the channel layer.

Recently, in order to increase the size of the display, it is required to develop a transistor having stable operation and durability by securing the constant current characteristics of the driving thin film transistor.

Amorphous silicon thin film transistors can be fabricated in low temperature processes but have very low mobility and do not meet the constant current test conditions. On the other hand, the polycrystalline silicon thin film transistor has a high mobility and a satisfactory constant current test condition, but it is difficult to obtain a uniform characteristic, so it is difficult to make a large area and a high temperature process is required.

Accordingly, development of oxide semiconductor thin film transistors in which an active layer is formed of an oxide semiconductor has been actively performed. The oxide semiconductor thin film transistor suppresses carrier concentration by applying hafnium (Hf), zirconium (Zr), gallium (Ga), etc. to the semiconductor layer in order to increase the band gap, but by applying Hf, Zr, Ga, etc. The composition of the semiconductor layer is changed to reduce the electrical characteristics of the thin film transistor.

SUMMARY OF THE INVENTION The present invention is to overcome the above-mentioned problems, and an object of the present invention is to improve the reverse bias characteristics of a thin film transistor by a gate insulating layer made of magnesium oxide, thereby improving reliability and at the same time improving electrical characteristics. The present invention provides a thin film transistor and a method of manufacturing the same.

In order to achieve the above object, a thin film transistor and a method of manufacturing the same according to the present invention include a gate formed on a substrate, a first gate insulating layer formed on the gate and the substrate to cover the gate, and the first gate insulation. A second gate insulating layer formed on the layer and made of magnesium oxide, a semiconductor layer formed on the second gate insulating layer so as to correspond to the gate, and a portion of the semiconductor layer electrically connected to the second gate insulating layer, It may include a source and a drain electrode formed in.

The second gate insulating layer may be formed to cover all of the top surface of the first gate insulating layer.

The second gate insulating layer may be formed to have a predetermined thickness to cover the top surface of the first gate insulating layer.

The second gate insulating layer may be formed to a thickness of 0.1nm to 2nm.

The second gate insulating layer may be interposed between the first gate insulating layer and the semiconductor layer, between the first gate insulating layer and the source electrode, and between the first gate insulating layer and the drain electrode. .

The first gate insulating layer may be formed of a silicon oxide film.

The first gate insulating layer may be formed to a thickness of 250 nm to 350 nm on the substrate and the top surface of the gate.

The second gate insulating layer may be formed in a thin film form or an array of quantum dots compared to the thickness of the first gate insulating layer.

The semiconductor layer may be made of IGZO, which is an oxide semiconductor.

The semiconductor device may further include a passivation layer formed to cover the source electrode, the drain electrode, and the semiconductor layer, and a contact electrically connected to the source and the drain electrode through the passivation layer in a downward direction from an upper surface of the passivation layer.

A gate forming step of forming a gate on a substrate, a first gate insulating layer forming step of forming a first gate insulating layer on the gate and the substrate to cover the gate, and oxidizing on the first gate insulating layer A second gate insulating layer forming step of forming a second gate insulating layer made of magnesium, a semiconductor layer forming step of forming a semiconductor layer on the second gate insulating layer so as to correspond to the gate, and a part of which is electrically And forming a source electrode and a drain electrode so as to form a source electrode and a drain electrode so as to be connected to each other.

In the forming of the second gate insulating layer, a second gate insulating layer may be formed on the top surface of the first gate insulating layer with a thickness of 0.1 nm to 2 nm.

Forming a passivation layer to cover the source and drain electrodes and the semiconductor layer; and forming a contact hole so that the source and drain electrodes are exposed upward through the passivation layer from an upper surface of the passivation layer to a lower direction; The method may further include forming a contact by filling a conductive material in the contact hole.

In the thin film transistor and the manufacturing method thereof according to the present invention, the reverse bias characteristic of the thin film transistor is improved by the gate insulating layer made of magnesium oxide, thereby improving reliability and at the same time improving electrical characteristics.

1 is a cross-sectional view illustrating a thin film transistor according to an exemplary embodiment of the present invention.
2A and 2B are band gap energy graphs showing carrier movement characteristics depending on whether a second gate insulating layer is formed in a thin film transistor.
3 is a current voltage waveform showing electrical characteristics depending on whether a second gate insulating layer is formed in a thin film transistor.
4A and 4B are waveforms illustrating voltage-current characteristics according to wavelengths and temperatures depending on whether a second gate insulating layer is formed in a thin film transistor.
5 is a flowchart illustrating a method of manufacturing the thin film transistor of FIG. 1.
6A to 6G are cross-sectional views illustrating a method of manufacturing the thin film transistor of FIG. 5.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention. Here, parts having similar configurations and operations throughout the specification are denoted by the same reference numerals.

1, a cross-sectional view illustrating a thin film transistor according to the present invention is shown.

As shown in FIG. 1, the thin film transistor 100 includes a substrate 110, a gate 120, a first gate insulating layer 130, a second gate insulating layer 140, a semiconductor layer 150, a source and a drain. The electrode 160, the passivation layer 170, and the contact 180 are included.

The substrate 110 has a flat upper surface 111 and a flat lower surface 112 opposite to the upper surface 111. The gate 120 is formed on the substrate 110 to partially cover the upper surface 111 of the substrate 110. The substrate 110 may be made of glass, plastic, sapphire, quartz, quartz, flexible polymer, acrylic, or equivalent components thereof, but is not limited thereto.

The gate 120 is formed in a predetermined pattern to cover a portion of the upper surface 111 of the substrate 110. The gate 120 is interposed between the substrate 110 and the first gate insulating layer 130. The gate 120 may be made of any one of aluminum, copper, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium, and alloys thereof.

The first gate insulating layer 130 is formed on the top surface 111 of the substrate 110 and the gate 120 to cover the gate 120. The first gate insulating layer 130 electrically protects the gate 120. The first gate insulating layer 130 may be made of silicon dioxide (SiO ₂ ) having insulating properties. The first gate insulating layer 130 may be formed to cover all the upper portions of the substrate 110 on which the gate 120 is formed. The first gate insulating layer 130 may be formed to a thickness of 250nm to 350nm. The first gate insulating layer 130 formed of the silicon oxide layer has a bandgap characteristic of 9 eV.

The second gate insulating layer 140 is formed on the first gate insulating layer 130 to cover the first gate insulating layer 130. The second gate insulating layer 140 may be formed on the upper surface of the first gate insulating layer 130 to have a predetermined thickness. In addition, the second gate insulating layer 140 is interposed between the semiconductor layer 150 and the first gate insulating layer 130. In addition, the second gate insulating layer 140 is interposed between the first gate insulating layer 130 and the source and drain electrodes 160. The second gate insulating layer 140 may be made of magnesium oxide (MgO), which is a metal oxide.

The second gate insulating layer 140 may be formed in a thin film form compared to the thickness of the first gate insulating layer 130. In addition, the second gate insulating layer 140 may have a form in which the second gate insulating layer 140 is arranged with quantum dots.

The second gate insulating layer 140 may be formed to a thickness of 0.1nm to 2nm. When the thickness of the second gate insulating layer 140 is less than 0.1 nm, adsorption of electrons, which is a characteristic of magnesium oxide, may be reduced. In addition, when the thickness of the second gate insulating layer 140 exceeds 2 nm, the mobility characteristics of electrons required to drive the transistor may be reduced.

The second gate insulating layer 140 made of magnesium oxide has an excellent insulating property and has a high bandgap characteristic of 7.6 eV, which is suitable for maintaining a low carrier concentration.

The magnesium (Mg) element has a high electron bonding ability with an electron (O) element having a negative electron conductivity of 1.3 and a negative charge of 3.44. Oxygen (O) has higher negative conductivity than indium (In, 1.78), gallium (Ga, 1.81), and zinc (Zn, 1.65) of the semiconductor layer 150 when the semiconductor layer 150 is made of IGZO. Since the ionic bond strength with magnesium may be stronger. This means that adding or removing oxygen to the second gate insulating layer 140 made of magnesium oxide may have a greater influence on the carrier concentration in the semiconductor layer 150 than the indium gallium and zinc. do. The electrical characteristics and the carrier movement characteristics of the thin film transistor by the second gate insulating layer 140 made of magnesium oxide will be described after the description of each configuration of the thin film transistor 100.

The semiconductor layer 150 is formed to correspond to the gate 120 on the second gate insulating layer 140. That is, the semiconductor layer 150 is formed on the top surface of the second gate insulating layer 140 so as to overlap the gate 120. The semiconductor layer 150 is made of IGZO, an oxide semiconductor in which indium (In), gallium (Ga), zinc (Zn), and oxygen (O) are mixed. The semiconductor layer 150 may be formed to a thickness of 40 to 50nm.

The source and drain electrodes 160 are formed on the second gate insulating layer 140 so that a portion thereof is electrically connected to the semiconductor layer 150. That is, the source and drain electrodes 160 are formed on the semiconductor layer 150 and on the second gate insulating layer 140. The source and drain electrodes 160 may be formed by patterning a metal layer to cover both the semiconductor layer 150 and the second gate insulating layer 140. By the patterning, the source electrode 161 is spaced apart from the drain electrode 162 around the semiconductor layer 150 and electrically separated from each other. The source and drain electrodes 160 may be made of any one of metals such as copper, titanium, molybdenum, chromium, tantalum, tungsten, aluminum, and alloys thereof, but are not limited thereto.

The passivation layer 170 is formed to cover both the source and drain electrodes 160 and the semiconductor layer 150. The passivation layer 170 includes a semiconductor layer 150 and an insulating layer for protecting the source and drain electrodes 160. The protective film 170 may be formed of a silicon oxide film or a silicon nitride film, but is not limited thereto.

The passivation layer 170 includes a contact hole 171 formed to expose a portion of the source and drain electrodes 160 to an upper portion thereof.

The contact 180 is formed to fill the contact hole 171 of the passivation layer 170. The contact 180 is electrically connected to the source and drain electrodes 160, respectively. The contact 180 may be formed by depositing and planarizing a metallic material on the passivation layer 170, but is not limited thereto.

2A and 2B, a band of the thin film transistor X of the control group without the second gate insulating layer 140 interposed therebetween and the thin film transistor 100 of the present application with the second gate insulating layer 140 interposed therebetween. Gap and carrier movement characteristics are shown. In this case, the first gate insulating layer 130 has a thickness of 300 nm, the second gate insulating layer 140 has a thickness of 1 nm, and the semiconductor layer 150 has a thickness of 45 nm. When the first gate insulating layer 130, which is silicon dioxide, and the semiconductor layer 150, which is IGZO, are stacked, the band alignment state VBO (Valence Band Offset) is 2.0 eV. When the first gate insulating layer 130 of silicon dioxide, the second gate insulating layer 140 of magnesium oxide, and the semiconductor layer 150 of IGZO are sequentially stacked, a high band gap of magnesium oxide (7.6eV) is obtained. VBO (Valence Band Offset) has a value larger than 2.0 eV.

As shown in FIGS. 2A and 2B, the light having a wavelength (550 nm) having a higher energy (2.25 eV) than the control thin film transistor (X) and the VBO of the thin film transistor 100 of the present application is thin film transistors (X, 100). When incident on, the movement of the resulting hole carrier is shown. At this time, the wavelength of the incident light may use light of a wavelength lower than 550nm.

In the control thin film transistor X, when light with a wavelength of 550 nm or higher than VBO is incident, the generated hole carriers are moved to the first gate insulating layer 130. In this case, a barrier layer is formed on the first gate insulating layer 130 by a hole carrier.

In the thin film transistor 100 of the present application, when light having a wavelength of 550 nm or lower than VBO is incident, the generated hole carriers are moved to the second gate insulating layer 140 made of magnesium oxide. At this time, since the VBO of the thin film transistor 100 of the present application is higher than the control thin film transistor X, the concentration of the carrier is lower. In addition, the thin film transistor 100 of the present application is difficult to move to the first gate insulating layer 130 through which the hole carrier must go through two steps. That is, the hole carriers may be prevented from moving to the first gate insulating layer 130 by the second gate insulating layer 140. As described above, in the thin film transistor 100 of the present application, since the hole carrier moves to the second gate insulating layer 140, the second gate insulating layer 140, which is a thin film of 1 nm, becomes a tunnel barrier layer.

Since the barrier layer is formed in the second gate insulating layer 140 which is a thin film by the hole carrier, the thin film transistor 100 of the present application is not significantly affected by the wavelength and temperature of the incident light, thereby improving timely characteristics. do. Such electrical characteristics will be described with reference to the current voltage waveforms shown in FIGS. 3, 4A, and 4B.

3 illustrates an electrical characteristic of a waveform of a drain current according to a gate voltage of a thin film transistor according to whether the second gate insulating layer 140 is applied. That is, FIG. 3 illustrates the thin film transistor 100 and the second gate insulating layer 140 of the present application, when the second gate insulating layer 140 is interposed between the first gate insulating layer 130 and the semiconductor layer 150. The drain current waveform according to the gate voltage of the control thin film transistor X, which is the case where only the first gate insulating layer 130 and the semiconductor layer 150 are provided, is illustrated. In this case, the thin film transistors 100 and X have a voltage VDS between the drain electrode and the source electrode of 10V, and the width W and the length L of the semiconductor layer 150 are 100 μm and 20 μm, respectively. .

As shown in FIG. 3, it can be seen that the thin film transistor 100 of the present application reaches a threshold voltage for entering a saturation region at a smaller gate voltage than the control thin film transistor X. As a result of the measurement, it can be seen that the threshold voltage of the thin film transistor X of the control unit is -1.135V, and the threshold voltage of the thin film transistor 100 of the present application is reduced to -1.336V.

In addition, it can be seen from FIG. 4 that the thin film transistor 100 of the present application has a large current change by a small voltage change, compared to the thin film transistor X of the control group. As a result, S-Slope (Subthreshold slope), which is the slope before the threshold voltage, can be seen that the thin film transistor 100 of the present application is 0.362V, which is further reduced compared to 0.390V of the thin film transistor X of the control group. And as a result of the mobility calculation, it can be seen that the thin film transistor (X) of the control is increased to 10.556 of the thin film transistor 100 of the present application compared to 7.556.

As such, the thin film transistor 100 to which the second gate insulating layer 140 made of magnesium oxide is applied may improve reverse bias characteristics to improve reliability and at the same time improve electrical characteristics.

4A and 4B, the time of the thin film transistor X of the control without the second gate insulating layer 140 and the thin film transistor 100 of the present application with the second gate insulating layer 140 interposed therebetween. The voltage and current waveforms for each of the characteristics of NBTS (Negative Bias Temperature Stress) and NBTS (Negative Bias Illumination Temperature Stress) are shown. In this case, the first insulating layer 130 has a thickness of 300 nm, the second gate insulating layer 140 has a thickness of 1 nm, and the semiconductor layer 150 has a W / L of 100 μm / 20 μm.

As shown in FIG. 4A, the NBTS characteristic NBTSx of the control thin film transistor X shows that the threshold voltage is shifted by -3.13V as the gate voltage VGS is 5000 seconds after the initial voltage i. Able to know. At this time, the temperature was maintained at 30 ° C. In addition, the NBITS characteristic (NBITSx) of the control thin film transistor (X) is compared to the initial voltage (i_D) where the gate voltage (VGS) has no light. It can be seen that the threshold voltage is shifted by -4.09V. At this time, in the measurement of the gate voltage VGS, the voltage between the drain and the source is 10V and the temperature is maintained at 30 ° C.

As shown in FIG. 4B, it can be seen that the NBTS characteristic NBTS100 of the thin film transistor 100 of the present application is -2.07V shifted as the gate voltage VGS is 5000 seconds after the initial time i. have. At this time, the temperature was maintained at 30 ° C. In addition, the NBITS characteristic (NBITS100) of the thin film transistor 100 of the present application is 5000 seconds after the light having the intensity of 0.1mW / cm2 is incident on the wavelength of 550nm compared to the initial (i_D) where the gate voltage (VGS) has no light. As the 5000s_P), the threshold voltage is shifted by -3.03V. Here, an initial (i_P) current-voltage waveform is also shown in which light having an intensity of 0.1 mW / cm 2 is incident at a wavelength of 550 nm. In the measurement of the gate voltage VGS, the voltage between the drain and the source is 10V and the temperature is maintained at 30 ° C.

As shown in FIGS. 4A and 4B, the thin film transistor 100 of the present application has a smaller change in current transfer characteristic due to a change in wavelength and temperature of light than a control thin film transistor (X). That is, the thin film transistor 100 of the present application has a lower change characteristic than the initial state of the control thin film transistor X, and thus can be stably operated, thereby improving reliability of the device.

5 is a flowchart illustrating a method of manufacturing the thin film transistor of FIG. 1, and FIGS. 6A to 6G are cross-sectional views illustrating a method of manufacturing the thin film transistor of FIG. 5.

First, as shown in FIG. 5, the thin film transistor includes a gate forming step S1, a first gate insulating layer forming S2, a second gate insulating layer forming step S3, a semiconductor layer forming step S4, a source and a drain. An electrode forming step S5, a protective film forming step S6, and a contact forming step S7 are included. Such a method of manufacturing the thin film transistor of FIG. 5 will be described in detail with reference to FIGS. 6A to 6H.

As shown in FIG. 6A, in the gate forming step S1, a gate 120 having a predetermined pattern is formed on a substrate 110 of a substantially flat plate. Prior to forming the gate 120, a buffer layer made of silicon oxide (SiOx) or silicon nitride (SiNx) may be further formed on the substrate 110, but is not limited thereto. The gate 120 may be formed by stacking a single layer made of any one of conductive materials or different conductive materials, and then patterning the gate 120, but is not limited thereto.

As shown in FIG. 6B, in the first gate insulating layer formation S2, the first gate insulating layer 130 is formed to cover both the gate 120 formed on the substrate 110 and the top surface of the substrate 110. do. The first gate insulating layer 130 may be formed by applying an insulating layer to a predetermined thickness so as to cover both the upper surface of the gate 120 and the substrate 110. The first gate insulating layer 130 may be formed to cover all the upper portions of the substrate 110 on which the gate 120 is formed by sputtering or plasma CVD.

As shown in FIG. 6C, in the forming of the second gate insulating layer S3, the second gate insulating layer 140 is formed on the first gate insulating layer 130 to cover the first gate insulating layer 130. do. The second gate insulating layer 140 is made of magnesium oxide. The second gate insulating layer 140 made of magnesium oxide may be deposited on the upper surface of the first gate insulating layer 130 by using an RF magnetron sputter. The second gate insulating layer 140 may be deposited to a thickness of 0.1 nm to 2 nm. The second gate insulating layer 140 may be formed in the form of a thin film or a quantum dot formed to a predetermined thickness.

As shown in FIG. 6D, in the semiconductor layer forming step S4, a semiconductor layer 140 having a predetermined thickness is formed on the second gate insulating layer 140. The semiconductor layer 150 is formed on the second gate insulating layer 140 to overlap the gate 120. The semiconductor layer 150 may be made of IGZO, which is an oxide semiconductor.

As shown in FIG. 6E, in the source and drain electrode forming step S5, a metal layer having a predetermined thickness is formed on the second gate insulating layer 140 and the semiconductor layer 150, and the semiconductor layer 150 is formed. The metal layer is patterned to be exposed to form a source electrode 161 and a drain electrode 162. In this case, the source and drain electrodes 160 are electrically separated by patterning.

As shown in FIG. 6F, in the protective film forming step S6, the protective film 170 is formed on the entire upper surface of the substrate 110 on which the source and drain electrodes 160 are formed. The passivation layer 170 may be formed in a single layer or a multilayer structure including any one of silicon oxide (SiOx), silicon nitride (SiNx), and an organic material, but is not limited thereto.

As shown in FIG. 6G, in the contact forming step S7, the passivation layer 170 is patterned to form contact holes 171 exposing the source and drain electrodes 160, respectively. In addition, a contact layer is formed on the passivation layer 170 to fill the contact hole 171, and then patterned to form the contact 180. Here, after the contact forming step S7, an electrode layer (not shown) electrically connected to the contact 180 and an interlayer insulating film (not shown) for electrically separating the electrode layer for connection of each electrode of the thin film transistor 100. Etc. can be further formed in a single layer or multiple layers.

What has been described above is just one embodiment for carrying out the thin film transistor and the manufacturing method thereof according to the present invention, the present invention is not limited to the above-described embodiment, as claimed in the following claims Without departing from the gist of the present invention, those skilled in the art to which the present invention pertains to the technical spirit of the present invention to the extent that various modifications can be made.

100; Thin film transistor
110; Substrate 120; gate
130; A first gate insulating layer 140; Second gate insulating layer
150; Semiconductor layer 160; Source and Drain Electrodes
170; Passivation 180; Contact

Claims (13)

A gate formed on the substrate;
A first gate insulating layer formed on the gate and the substrate to cover the gate;
A second gate insulating layer formed on the first gate insulating layer and made of magnesium oxide;
A semiconductor layer formed on the second gate insulating layer to correspond to the gate; And
And a portion of the semiconductor layer electrically connected to the semiconductor layer, the source and drain electrodes formed on the second gate insulating layer. The method according to claim 1,
The second gate insulating layer is formed to cover all of the upper surface of the first gate insulating layer. The method according to claim 1,
The second gate insulating layer may be formed to have a predetermined thickness to cover the top surface of the first gate insulating layer. The method according to claim 3,
The second gate insulating layer is thin film transistor, characterized in that formed in a thickness of 0.1nm to 2nm. The method according to claim 1,
The second gate insulating layer,
Between the first gate insulating layer and the semiconductor layer,
Between the first gate insulating layer and the source electrode,
And a thin film transistor interposed between the first gate insulating layer and the drain electrode. The method according to claim 1,
And the first gate insulating layer is formed of a silicon oxide film. The method of claim 6,
The first gate insulating layer is formed on the substrate and the upper surface of the thin film transistor, characterized in that formed in a thickness of 250nm to 350nm. The method according to claim 1,
The second gate insulating layer is a thin film transistor, characterized in that the thin film form or quantum dot array form compared to the thickness of the first gate insulating layer. The method according to claim 1,
The semiconductor layer is a thin film transistor, characterized in that the oxide semiconductor consisting of IGZO. The method according to claim 1,
A passivation layer formed to cover the source electrode, the drain electrode, and the semiconductor layer;
And a contact electrically connected to the source and the drain electrodes through the passivation layer in a downward direction from an upper surface of the passivation layer. A gate forming step of forming a gate on the substrate;
Forming a first gate insulating layer on the gate and the substrate to cover the gate;
A second gate insulating layer forming step of forming a second gate insulating layer made of magnesium oxide on the first gate insulating layer;
A semiconductor layer forming step of forming a semiconductor layer on the second gate insulating layer to correspond to the gate; And
And source and drain electrodes forming a source electrode and a drain electrode so that a portion of the semiconductor layer is electrically connected to the semiconductor layer. 12. The method of claim 11,
In the second gate insulating layer forming step
And forming a second gate insulating layer on the top surface of the first gate insulating layer with a thickness of 0.1 nm to 2 nm. 12. The method of claim 11,
Forming a passivation layer covering the source and drain electrodes and the semiconductor layer; And
And forming a contact hole to penetrate the passivation layer from the upper surface of the passivation layer so that the source and drain electrodes are exposed upward, and to form a contact by filling a conductive material in the contact hole. A manufacturing method of a thin film transistor.

Images