KR20130087766A - Light emitting diode and method of manufacturing the diode - Google Patents

Abstract

PURPOSE: A light emitting diode and a manufacturing method thereof are provided to improve the inner quantum efficiency of the light emitting diode by removing a defect part on which a threading dislocation is concentrated in a vertically grown semiconductor laminated structure. CONSTITUTION: A semiconductor laminated structure (110) includes an n-type compound semiconductor layer (111), an active layer (113), and a p-type compound semiconductor layer (115). An insulation pattern (120) is formed on the semiconductor laminated structure. A first transparent electrode (130) is formed on the semiconductor laminated structure. A P-type electrode (140) is electrically connected to the first transparent electrode. A second transparent electrode (150) is formed on the lower side of the semiconductor laminated structure.

Description

Light emitting diode and method of manufacturing the same

The present invention relates to a light emitting diode and a method of manufacturing the same, and more particularly, to a light emitting diode and a method of manufacturing the light emitting efficiency can be improved.

Light emitting diodes (LEDs) are a type of semiconductor light emitting devices that are manufactured by growing a P-N diode on a substrate. For example, the light emitting diode sequentially grows an n-type semiconductor layer, a light generation region, and a p-type semiconductor layer on a substrate, and then the transparent electrode and the p-type on the upper surface of the p-type semiconductor layer. After forming the electrode, and removing the substrate, it is manufactured by forming an n-type electrode under the n-type semiconductor layer. Light may be extracted through the transparent electrode on the p-type or n-type semiconductor layer.

Epitaxial Lateral Overgrowth (ELOG) is used as a method of growing the P-N diode. Specifically, first, a mask layer having a periodic pattern form is formed on the substrate or the buffer layer, and then the semiconductor layer is grown above the mask thickness on the substrate in the absence of the mask layer (window region). The semiconductor layer is grown horizontally on the mask. The semiconductor layer formed by the horizontal growth can greatly reduce the density of threading dislocations, thereby improving the performance of the light emitting diodes. However, even when the semiconductor layer is horizontally grown, defects including the threading potential exist in a portion where the semiconductor layer is in direct contact with the substrate, and the defects exist in all of the semiconductor layers including the light emitting region. This lowers the internal quantum efficiency, which indicates the efficiency with which the power applied to the electrode is converted to light.

The present invention provides a light emitting diode capable of improving the internal quantum efficiency.

The present invention provides a light emitting diode manufacturing method capable of improving the internal quantum efficiency.

The light emitting diode according to the present invention comprises a semiconductor laminate including an n-type compound semiconductor layer, an active layer and a p-type compound semiconductor layer, an insulation pattern provided inside the semiconductor laminate, and a semiconductor laminate structure provided with the insulation pattern. And a p-type electrode provided on the first transparent electrode and the first transparent electrode in contact with the p-type compound semiconductor layer and electrically connected to the first transparent electrode.

According to one embodiment of the invention, the light emitting diode is provided on the lower portion of the semiconductor laminated structure provided with the insulating pattern, the second transparent electrode and the contact with the n-type compound semiconductor layer divided by the insulating pattern and the The electronic device may further include an n-type electrode provided below the first transparent electrode and electrically connected to the second transparent electrode.

In example embodiments, the semiconductor stacked structure may be formed through horizontal growth, and the insulating pattern may be located at a defect site where threading dislocations are concentrated in the semiconductor stacked structure.

In example embodiments, the insulating pattern may penetrate the top and bottom of the semiconductor laminate.

According to one embodiment of the present invention, the insulating pattern may be arranged in the form of a plurality of lines parallel to each other.

According to one embodiment of the invention, the insulating pattern may be arranged in the form of a plurality of dots spaced apart from each other.

The method of manufacturing a light emitting diode according to the present invention includes forming a mask pattern on a substrate, and horizontally growing a semiconductor laminate including an n-type compound semiconductor layer, an active layer, and a p-type compound semiconductor layer on the substrate on which the mask pattern is formed. Forming the first transparent electrode and the p-type electrode sequentially on the stack structure, removing the substrate and the mask pattern, and threading dislocations in the semiconductor stack structure. The method may include removing a concentrated defect site and filling the region from which the defect site is removed with an insulating material to form an insulation pattern.

According to one embodiment of the present invention, the method of manufacturing a light emitting diode may further include sequentially forming a second transparent electrode and an n-type electrode under the stack structure.

According to one embodiment of the present invention, the substrate may be any one of a sapphire substrate, a substrate including silicon and a silicon compound, and a substrate including a compound consisting of metal and nitrogen.

According to one embodiment of the present invention, the forming of the mask pattern may be performed by selectively etching the mask layer after forming the mask layer on the substrate.

In example embodiments, the forming of the mask pattern may be performed by forming an ion implantation region on an upper surface of the substrate.

According to one embodiment of the present invention, the step of removing a defect site where the threading dislocations are concentrated in the semiconductor stack structure may be performed by removing a vertical upper portion of a region in contact with the substrate in the semiconductor stack structure.

The light emitting diode and the method of manufacturing the same according to the present invention can improve the internal quantum efficiency of the light emitting diode because the defect region where the threading dislocation is concentrated in the horizontally grown semiconductor laminate structure is removed.

1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.
2 is a flowchart illustrating a light emitting diode manufacturing method according to an embodiment of the present invention.
3 to 12 are cross-sectional views for describing a method of manufacturing the light emitting diode shown in FIG. 2.

Hereinafter, a light emitting diode according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 1, the light emitting diode 100 includes a semiconductor stack 110, an insulating pattern 120, a first transparent electrode 130, a p-type electrode 140, a second transparent electrode 150, and an n-type. Electrode 160.

The semiconductor stacked structure 110 includes an n-type compound semiconductor 111, an active layer 113, and a p-type compound semiconductor 115. The semiconductor laminate structure 110 may be formed of a III-V or II-VI compound semiconductor.

The n-type compound semiconductor layer 111 or the p-type compound semiconductor layer 115 may include a contact layer and a cladding layer, or may include a superlattice layer.

The active layer 113 may include a plurality of layers including a light generation layer in which holes recombine with electrons to generate light, and a cladding layer disposed above and below the light emitting layer. The active layer 113 may have a single quantum well structure or a multiple quantum well structure.

The non-doped semiconductor layer may be included in the n-type compound semiconductor layer 111 as a buffer layer. At the bottom of the n-type compound semiconductor layer 111, a polycrystalline growth layer may be present instead of a single crystal, and the polycrystalline growth layer may be included in the n-type compound semiconductor layer 111.

The semiconductor laminate structure 110 may have holes from the n-type compound semiconductor layer 111 and the p-type compound semiconductor layer 115 when a voltage is applied between the n-type compound semiconductor layer 111 and the p-type compound semiconductor layer 115. And electrons are injected into the light emitting layer, and light is generated by recombination of holes and electrons in the light emitting layer. Light generated in the emission layer is emitted to the outside through the p-type compound semiconductor layer 115 or the n-type compound semiconductor layer 111.

Although the semiconductor stacked structure 110 is illustrated as being stacked in the order of the n-type compound semiconductor 111, the active layer 113, and the p-type compound semiconductor 115, the p-type compound semiconductor 115, the active layer 113, and n The compound semiconductors 111 may be stacked in this order.

The semiconductor stacked structure 110 may be formed by an epitaxy process on a substrate on which a mask pattern is formed. Examples of the epitaxy process include Liquid Phase Epitaxy (LPE), Vapor Phase Epitaxy (VPE), Moleculer Beam Epitaxy (MBE), Chemical Vapor Deposition (CVD), Metalorganic Chemical Vapor Deposition (CVD), and Hydride Vapor Phase Epitaxy (HVPE). , ALD (atomic layer deposition), and the like.

The lower surface of the semiconductor laminate structure 110 preferably has a flat structure, but may have the same uneven structure as that of the mask pattern.

The insulating pattern 120 is provided inside the semiconductor stacked structure 110. For example, the insulating pattern 120 may penetrate the top and bottom of the semiconductor laminate structure 110. As another example, depending on the shape of the defect site described later, it may extend only to a predetermined height from the lower surface of the semiconductor laminate structure 110. The insulating pattern 120 may include an insulating material, and the insulating material may be a material including at least one of C, Si, Ti, and Al.

The insulating pattern 120 has a lattice constant mismatch between the substrate and the semiconductor stack 110 in the semiconductor stack 110 formed by horizontal growth, and has a threading potential along the vertical direction of the semiconductor stack 110. Replace the defective site where it is concentrated. Since the defect site is different depending on the shape of the mask pattern on the substrate, the shape of the insulating pattern 120 also depends on the shape of the mask pattern. That is, the insulating pattern 120 may have various shapes. For example, the insulation patterns 120 may have a line shape parallel to each other. As another example, the insulating pattern 120 may be in the form of a plurality of dots spaced apart from each other. As another example, the insulating pattern 120 may be in the form of a lattice.

Since the insulating pattern 120 replaces a defective portion of the semiconductor stack 110, the threading dislocations in the semiconductor stack 110 may be greatly reduced. Therefore, the internal quantum efficiency degradation due to the threading dislocations can be prevented.

The first transparent electrode 130 is disposed on the p-type compound semiconductor layer 115 of the semiconductor stacked structure 110 and is electrically connected to the p-type compound semiconductor layer 115. The first transparent electrode 130 may be formed of a transparent conductive oxide, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or fluorescent doped tin oxide (FTO). In addition, the first transparent electrode 130 may have a concave-convex structure on its surface. The uneven structure helps to extract light generated inside the semiconductor laminate structure 110.

The p-type electrode 140 is positioned on the first transparent electrode 130. The p-type electrode 140 is electrically connected to the first transparent electrode 130. The p-type electrode 140 may be used as a pad for bonding the wire. .

The second transparent electrode 150 is disposed under the n-type compound semiconductor layer 111 of the semiconductor stacked structure 110 and is electrically connected to the n-type compound semiconductor layer 111. The second transparent electrode 150 may be formed of a transparent conductive oxide. Examples of the transparent conductive oxide include ITO, IZO, ZnO, FTO, and the like. In addition, the second transparent electrode 150 may have a concave-convex structure on a surface thereof, and the concave-convex structure may be formed by anisotropic etching.

The n-type electrode 160 is disposed below the second transparent electrode 150. The n-type electrode 160 is electrically connected to the second transparent electrode 150. The n-type electrode 160 may be used as a pad for bonding the wire. .

Although not shown, the n-type electrode / reflective structure may be provided without the second transparent electrode 150 and the n-type electrode 160 under the semiconductor stacked structure 110. The n-type electrode / reflective structure makes ohmic contact with the n-type compound semiconductor layer 111. The n-type electrode / reflective structure may include a reflective layer, and the reflective layer may directly contact the n-type compound semiconductor layer 111. For example, the reflective layer may be formed of a reflective metal such as Ag or Al, and the metals may be well ohmic contacted to the n-type compound semiconductor layer 111. The n-type electrode / reflective structure may further include a protective metal layer protecting the reflective layer. Ni may be mentioned as an example of the said protective metal layer.

The light emitting diode 100 replaces a defect portion in which the threading dislocations are concentrated in the semiconductor laminate structure 110 with the insulating pattern 120, thereby reducing defects in the semiconductor laminate structure 110. Since the power provided to the light emitting diodes 100 may be improved in the internal quantum efficiency converted into light, the performance of the light emitting diodes 100 may be improved.

2 is a flowchart illustrating a light emitting diode manufacturing method according to an exemplary embodiment of the present invention, and FIGS. 3 to 12 are cross-sectional views illustrating the light emitting diode manufacturing method illustrated in FIG. 2.

2 and 3, the mask pattern 103 is formed on the substrate 101 (S110).

Examples of the substrate 101 may include a sapphire substrate, a substrate including silicon and a silicon compound, and a substrate including a compound consisting of metal and nitrogen. The substrate 101 may be a single crystal substrate.

The mask pattern 103 may be formed by forming a mask layer (not shown) on the substrate 101 and then selectively etching the mask layer. Thus, the mask pattern 103 masks to selectively expose the substrate 101. The mask pattern 103 may include silicon, a photoresist, or the like, but is not limited thereto.

The mask pattern 103 may have various shapes. For example, the mask pattern 103 may have a line shape parallel to each other as shown in FIG. As another example, as shown in FIG. 4, the mask pattern 103 may have a form of exposing the substrate 101 in the form of a plurality of dots spaced apart from each other. As another example, although not shown, the mask pattern 103 may be in the form of a plurality of dots spaced apart from each other.

Meanwhile, the mask pattern 103 may include a protrusion (not shown) on an upper surface, and the protrusion may have a shape of a hemisphere, a polygonal pillar, a cylinder, and a stripe. The protrusion may be formed by a lithography process or a heat treatment process.

As shown in FIG. 6, the mask pattern 103 may be formed by ion implantation into an upper surface of the substrate 101. The ion used for the ion implantation is preferably any one selected from N, C, B, Be, Li, Mg, O, F, S, P, As, Sr, Te, and compounds thereof. Specifically, the amount of ion implantation dose is adjusted to more than 1E17 ions / cm 2 5E18 ions / cm 2 or less, the implantation energy is preferably adjusted to 30 ~ 50keV. In this case, the mask pattern 103 may be formed to a depth of 50 to 1 μm from the surface of the substrate 101, and more preferably, to a depth of 50 to 200 nm.

The mask pattern 103 formed by ion implantation also has a form of a line parallel to each other, a form of exposing the substrate 101 in the form of a plurality of dots spaced apart from each other, a mask pattern 103 is a plurality of dots form a spaced apart from each other, etc. Can have

2 and 7, a semiconductor stacked structure including an n-type compound semiconductor layer 111, an active layer 113, and a p-type compound semiconductor layer 115 on a substrate 101 on which a mask pattern 103 is formed. Form 110 (S120).

The semiconductor stacked structure 110 may be formed by an epitaxy process on the substrate 101. Examples of the epitaxy process include Liquid Phase Epitaxy (LPE), Vapor Phase Epitaxy (VPE), Moleculer Beam Epitaxy (MBE), Chemical Vapor Deposition (CVD), Metalorganic Chemical Vapor Deposition (CVD), and Hydride Vapor Phase Epitaxy (HVPE). , ALD (atomic layer deposition), and the like.

Specifically, after the first semiconductor layer is formed on the substrate 101 on which the mask pattern 103 is formed, the n-type compound semiconductor layer 111 is formed by doping the first semiconductor layer to n-type. The active layer 113 is formed on the n-type compound semiconductor layer 111. After forming the second semiconductor layer on the active layer 113, the second semiconductor layer is doped with a p-type to form a p-type compound semiconductor layer 115.

As another example, the n-type compound semiconductor layer 111 is grown on the substrate 101 on which the mask pattern 103 is formed, the active layer 113 is grown on the n-type compound semiconductor layer 111, and the active layer 113 is formed. The p-type compound semiconductor layer 115 may be grown on it.

The semiconductor laminate structure 110 grows vertically at the portion in contact with the substrate 101 and horizontal growth (ELOG) on the mask pattern 103 not in contact with the substrate 101. The region in which the horizontal growth occurs in the semiconductor stack 110 is greatly reduced in density of threading dislocations, thereby improving internal quantum efficiency. However, in the region where the vertical growth occurs in the semiconductor laminate structure 110, the threading potential is concentrated due to the lattice constant mismatch between the substrate 101 and the semiconductor laminate structure 110, thereby deteriorating internal quantum efficiency. . Thus, the semiconductor laminate structure 110 has a defect portion 117 in which the threading dislocations are concentrated vertically above the region in contact with the substrate 101.

The n-type compound semiconductor layer 111 or the p-type compound semiconductor layer 115 may include a contact layer and a cladding layer, or may include a superlattice layer.

The active layer 113 may include a plurality of layers including a light generation layer in which holes recombine with electrons to generate light, and a cladding layer disposed above and below the light emitting layer. The active layer 113 may have a single quantum well structure or a multiple quantum well structure. When voltage is applied between the n-type compound semiconductor layer 111 and the p-type compound semiconductor layer 115, holes and electrons are injected into the light emitting layer from the n-type compound semiconductor layer 111 and the p-type compound semiconductor layer 115 ( and light is generated by recombination of holes and electrons in the light emitting layer. Light generated in the emission layer is emitted to the outside through the p-type compound semiconductor layer 115 or the n-type compound semiconductor layer 111.

The semiconductor layer of the semiconductor stacked structure 110 may be a III-V or II-VI compound semiconductor layer. In particular, the group III nitride compound semiconductors are widely used as materials capable of obtaining stable operation at high temperatures and obtaining high-output blue light and white light. However, group III nitride compound semiconductors are difficult to commercialize homogeneous nitride based substrates, so that sapphire (Al 2 O 3) can generally be formed on the substrate.

The non-doped semiconductor layer may be included in the n-type compound semiconductor layer 111 as a buffer layer. At the bottom of the n-type compound semiconductor layer 111, a polycrystalline growth layer may be present instead of a single crystal, and the polycrystalline growth layer may be included in the n-type compound semiconductor layer 111.

Although the semiconductor laminate structure 110 has been described as being formed in the order of the n-type compound semiconductor layer 111, the active layer 113, and the p-type compound semiconductor layer 115, the p-type compound semiconductor layer 115 and the active layer are described above. (113) and the n-type compound semiconductor layer 111 may be stacked in this order.

2 and 8, the first transparent electrode 130 and the p-type electrode 140 are sequentially formed on the semiconductor stack structure 110 (S130).

The first transparent electrode 130 is formed on the p-type compound semiconductor layer 115 of the semiconductor stacked structure 110. The first transparent electrode 130 may be formed of a transparent conductive oxide, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or fluorescent doped tin oxide (FTO). In addition, an uneven structure may be formed on the surface by anisotropically etching the first transparent electrode 130.

The p-type electrode 140 is formed on the first transparent electrode 130. The p-type electrode 140 may be formed by a general physical and chemical vapor deposition method.

2 and 9, the substrate 101 and the mask pattern 103 are removed (S140).

The substrate 101 and the mask pattern 103 may be removed by a lithography process, a polishing process, a laser lift off (LLO) process, or the like. After the substrate 101 and the mask pattern 103 are removed, the lower surface of the semiconductor laminate structure 110 preferably has a flat structure, but may have the same uneven structure as that of the mask pattern 103.

2 and 10, the defective portion 117 where the threading dislocations are concentrated in the semiconductor stack 110 is removed (S150).

Removal of the defect site 117 includes a lithography process, an etching process using a reactive ion beam, and a polishing process. For example, after forming a mask pattern (not shown) exposing the defect portion 117 on the lower surface of the semiconductor laminate 110, the first transparent electrode through the lithography process and the etching process using a reactive ion beam The semiconductor stacked structure 110 is etched until the 130 is exposed to remove the defect portion 117, and then the mask pattern is removed. Once the defect site 117 is removed, the semiconductor stack structure 110 has a plurality of openings 119. For example, the openings 119 may penetrate the top and bottom of the semiconductor stack 110, or may extend only up to a predetermined height from the bottom surface of the semiconductor stack 110.

Since the defect region 117, that is, the region where the threading dislocations are concentrated, is eliminated, it is possible to greatly reduce the threading dislocations in the semiconductor stack structure 110. Therefore, the internal quantum efficiency degradation due to the threading dislocations can be prevented.

2 and 11, the insulating pattern 120 is formed by filling a region in which the defect portion 117 is removed with an insulating material (S160).

The insulating pattern 120 may be formed by filling the region in which the defect portion 117 is removed and the openings 119 with an insulating material by a general physical and chemical vapor deposition method. The insulating material may be a material including at least one of C, Si, Ti, and Al. For example, the insulating pattern 120 may penetrate the top and bottom of the semiconductor laminate structure 110. As another example, the insulating pattern 120 may extend only to a predetermined height from the lower surface of the semiconductor laminate structure 110.

2 and 12, the second transparent electrode 150 and the n-type electrode 160 are sequentially formed under the semiconductor stack 110 (S170).

The second transparent electrode 150 is formed under the n-type compound semiconductor layer 111 of the semiconductor stacked structure 110. The second transparent electrode 150 may be formed of a transparent conductive oxide. Examples of the transparent conductive oxide include ITO, IZO, ZnO, FTO, and the like. In addition, the second transparent electrode 150 may be anisotropically etched to form an uneven structure on the surface.

The n-type electrode 160 is formed below the second transparent electrode 150. The n-type electrode 160 may be formed by a general physical and chemical vapor deposition method.

The light emitting diode 100 is completed by forming the second transparent electrode 150 and the n-type electrode 160.

Although not shown, the n-type electrode / reflective structure may be formed without forming the second transparent electrode 150 and the n-type electrode 160 under the semiconductor stacked structure 110. The n-type electrode / reflective structure is in electrical contact with the n-type compound semiconductor layer 111. The n-type electrode / reflective structure may include a reflective layer, and the reflective layer may directly contact the n-type compound semiconductor layer 111. For example, the reflective layer may be formed of a reflective metal such as Ag or Al. In addition, a protective metal layer may be further formed below the reflective layer to protect the reflective layer. The protective metal layer may be formed using Ni.

According to the light emitting diode manufacturing method, defects existing in the semiconductor stack structure 110 may be reduced by removing a defect site in which the threading dislocations are concentrated in the semiconductor stack structure 110. Therefore, the internal quantum efficiency of converting the power provided to the light emitting diode 100 into light can be improved.

As described above, according to the light emitting diode according to the present invention and a method of manufacturing the same, since the defect site in which the threading dislocations are concentrated in the semiconductor laminate structure is removed, the internal quantum efficiency decrease due to the threading dislocations can be reduced. Thus, a light emitting diode having relatively improved internal quantum efficiency can be manufactured.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims. It can be understood that it is possible.

100: light emitting diode 101: substrate
103 mask pattern 110 semiconductor laminated structure
111: n-type compound semiconductor layer 113: active layer
115: p-type compound semiconductor layer 117: defect site
119: opening 120: insulation pattern
130: first transparent electrode 140: p-type electrode
150: second transparent electrode 160: n-type electrode

Claims (12)

a semiconductor laminate including an n-type compound semiconductor layer, an active layer, and a p-type compound semiconductor layer;
An insulation pattern provided in the semiconductor laminate structure;
A first transparent electrode provided on the semiconductor laminate structure having the insulating pattern and in contact with the p-type compound semiconductor layer; And
And a p-type electrode provided on the first transparent electrode and electrically connected to the first transparent electrode. The semiconductor device of claim 1, further comprising: a second transparent electrode disposed under the semiconductor laminate structure having the insulating pattern and in contact with the n-type compound semiconductor layer divided by the insulating pattern; And
And a n-type electrode provided under the first transparent electrode and electrically connected to the second transparent electrode. The light emitting diode of claim 1, wherein the semiconductor stack structure is formed through horizontal growth, and the insulating pattern is positioned at a defect site where threading dislocations are concentrated in the semiconductor stack structure. The light emitting diode of claim 1, wherein the insulating pattern penetrates the top and bottom of the semiconductor laminate. The light emitting diode of claim 4, wherein the insulating patterns are arranged in a plurality of lines parallel to each other. The light emitting diode of claim 4, wherein the insulating patterns are arranged in a plurality of dot spaced apart from each other. Forming a mask pattern on the substrate;
Forming a semiconductor laminate structure including an n-type compound semiconductor layer, an active layer, and a p-type compound semiconductor layer through horizontal growth on the substrate on which the mask pattern is formed;
Sequentially forming a first transparent electrode and a p-type electrode on the stack structure;
Removing the substrate and the mask pattern;
Removing a defect site in which threading dislocations are concentrated in the semiconductor laminate structure; and
And forming an insulating pattern by filling the region from which the defective portion is removed with an insulating material. The method of claim 7, further comprising sequentially forming a second transparent electrode and an n-type electrode under the stack structure. The method of claim 7, wherein the substrate is any one of a sapphire substrate, a substrate including silicon and a silicon compound, and a substrate including a compound consisting of metal and nitrogen. The method of claim 7, wherein the forming of the mask pattern comprises forming a mask layer on the substrate and then selectively etching the mask layer. The method of claim 7, wherein the forming of the mask pattern comprises forming an ion implantation region on an upper surface of the substrate. The method of claim 7, wherein the removing of the defective portion in which the threading dislocations are concentrated in the semiconductor laminate structure is performed by removing a vertical upper portion of the region in contact with the substrate in the semiconductor laminate structure.

Images