KR20130082374A - Methods of fabricating semiconductor devices - Google Patents

Methods of fabricating semiconductor devices Download PDF

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Publication number
KR20130082374A
KR20130082374A KR1020120003561A KR20120003561A KR20130082374A KR 20130082374 A KR20130082374 A KR 20130082374A KR 1020120003561 A KR1020120003561 A KR 1020120003561A KR 20120003561 A KR20120003561 A KR 20120003561A KR 20130082374 A KR20130082374 A KR 20130082374A
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KR
South Korea
Prior art keywords
hard mask
gate electrode
film
pattern
forming
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KR1020120003561A
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Korean (ko)
Inventor
김범수
정영재
정승필
신경섭
이영철
임일호
김현성
Original Assignee
삼성전자주식회사
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Priority to KR1020120003561A priority Critical patent/KR20130082374A/en
Publication of KR20130082374A publication Critical patent/KR20130082374A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate

Abstract

A first insulating film, a first conductive film, a dielectric film, a second conductive film, a metal film, and a hard mask film are sequentially formed on the substrate, the hard mask film is patterned to form a hard mask pattern, and the hard mask pattern is patterned. The metal layer is patterned using a mask to form a metal gate electrode having exposed sides, a first passivation layer is formed on the exposed side of the metal gate electrode, and the second mask is formed using the hard mask pattern as a patterning mask. The conductive layer is patterned to form a second gate electrode having exposed sides, a second passivation layer is formed on the exposed side of the second gate electrode, and the dielectric layer and the substrate are formed using the hard mask pattern as a patterning mask. Patterning the first conductive film to form the dielectric pattern and the first gate electrode to form the gate structures. This method is described in the semiconductor device.

Description

Method of fabricating semiconductor devices

The technical field of the present invention relates to a semiconductor device and a method of manufacturing the same.

Patterns of semiconductor devices are gradually becoming finer, and thus the uniformity of fine patterns is becoming more stringent.

The problem to be solved by the present invention is to provide a semiconductor device.

Another object of the present invention is to provide a semiconductor device having excellent uniformity of patterns.

Another object of the present invention is to provide a semiconductor device having a protective film on the side of the metal gate electrode.

Another object of the present invention is to provide a semiconductor device having an air gap.

Another object of the present invention is to provide a method for manufacturing a semiconductor device.

Another object of the present invention is to provide a method of forming a pattern of a semiconductor device having excellent uniformity.

Another object of the present invention is to provide a method of manufacturing a semiconductor device including patterns having a double protective film.

Another object of the present invention is to provide a method for preventing a conductive pattern of a semiconductor device from being damaged in an etching process.

Another object of the present invention is to provide a method for preventing by-products of a conductive pattern of a semiconductor device from being generated in an etching process.

The various problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned herein will be fully understood by those skilled in the art from the following description.

The semiconductor device manufacturing method according to the technical idea of the present invention for solving the above problems, sequentially forming a first insulating film, a first conductive film, a dielectric film, a second conductive film, a metal film and a hard mask film on a substrate Patterning the hard mask layer to form a hard mask pattern, and patterning the metal layer using the hard mask pattern as a patterning mask to form a metal gate electrode having exposed sides, and on the exposed side of the metal gate electrode A first passivation layer is formed, and the second conductive layer is patterned using the hard mask pattern as a patterning mask to form a second gate electrode having exposed side surfaces, and a second passivation layer on the exposed side surface of the second gate electrode. And the dielectric film and the first conductive film are patterned using the hard mask pattern as a patterning mask. And forming a dielectric pattern and a first gate electrode to form gate structures.

The forming of the hard mask layer may include forming a first hard mask layer on the metal layer, and forming a second hard mask layer on the first hard mask layer.

The first passivation layer is vertically aligned with an upper surface and a side surface of the second hard mask pattern, a side surface of the first hard mask pattern, a side surface of the metal gate electrode, a surface of the second conductive layer, and side surfaces of the metal gate electrode. Vertical surfaces can be conformally covered.

The second passivation layer conforms to a top surface and a side surface of the second hard mask pattern, a side surface of the first hard mask pattern, a side surface of the first passivation layer pattern, a side surface of the second gate electrode, and an exposed top surface of the dielectric layer. Can be covered.

Forming the metal gate electrode may include removing a portion of the surface of the second conductive layer to recess it.

Forming the metal gate electrode may include partially removing side surfaces of the metal film.

Forming the first passivation layer removes portions formed on the top and side surfaces of the second hard mask pattern, the side surfaces of the first hard mask pattern, the side surfaces of the metal gate electrode, and the surface of the second conductive layer. And remaining portions formed on the sides of the metal gate electrodes.

Forming the first gate electrode may include removing all of the second passivation layer.

The method of manufacturing a semiconductor device according to the inventive concept may further include forming a second insulating layer pattern covering the gate structures, wherein the second insulating layer pattern may include side surfaces of the gate structures and an upper surface of the exposed substrate. And second insulating layer patterns formed on side surfaces and upper surfaces of the hard mask patterns of the adjacent gate structures may be physically connected to each other.

An air gap may be defined between the gate structures by the second insulating layer pattern.

The semiconductor device according to the inventive concept may provide a semiconductor device having uniform characteristics by forming patterns having excellent uniformity.

The semiconductor device according to the inventive concept may prevent the deterioration of characteristics of semiconductor devices by forming double protective layer patterns to prevent generation of by-products during etching of the conductive layers.

According to an aspect of the inventive concept, a semiconductor device may have a protective layer pattern formed thereon to prevent electrical deterioration of a device due to an electrical short or a coupling effect through electrical separation between fine gate electrodes of several tens of nm or less, and thus, the product to which the device is applied. Can improve the performance.

According to the semiconductor device of the inventive concept, by forming double protective layer patterns, the reliability of the device may be improved to increase the production yield of the product to which the device is applied.

Method of manufacturing a semiconductor device according to the technical idea of the present invention provides methods that can improve the productivity without burdening the existing process technology.

In addition, various effects of the technical features of the present invention will be added to the detailed description.

1 is a conceptual longitudinal cross-sectional view of a semiconductor device according to the inventive concept.
2 to 15 are conceptual longitudinal cross-sectional views illustrating a method of manufacturing a semiconductor device according to the inventive concept.

Configuration and manufacturing method according to the technical spirit of the present invention and the objects to be achieved through them will be clearly understood through the embodiments and drawings described below.

The embodiments described below are provided to enable those skilled in the art to easily convey and to practice the spirit of the present invention. Therefore, the technical idea of the present invention may be modified in various forms without being limited to the embodiments described below.

Shapes and sizes of the regions shown in the drawings described below are merely illustrated to facilitate understanding of the present invention and may be exaggerated for convenience and used in the specification of the present invention, examples and drawings. Etc. are used to help understand the technical idea and do not limit the scope of the present invention.

1 is a longitudinal cross-sectional view conceptually illustrating a semiconductor device in accordance with some example embodiments of the inventive concepts;

Referring to FIG. 1, a semiconductor device 10 according to an embodiment of the inventive concept may include a plurality of gate structures 11 parallel to each other formed on a substrate 100. Each gate structure 11 may have a constant gate line width d1 and a gate separation distance d2.

The gate structures 11 according to the exemplary embodiment of the inventive concept may include a first insulating layer pattern 101a, a first gate electrode 102a, a dielectric pattern 113, a second gate electrode 104a, and a metal. The gate electrode 105a may be included. The gate structures 11 may include a cell structure of a nonvolatile flash memory.

The first insulating layer pattern 101a may be directly formed on the substrate 100. The first insulating layer pattern 101a may include silicon thermal oxide. The first insulating layer pattern 101a may be used as the tunneling insulating layer.

The first gate electrode 102a may be directly formed on the first insulating layer pattern 101a. Side surfaces of the first gate electrode 102a and side surfaces of the first insulating layer pattern 101a may be vertically aligned. The first gate electrode 102a may include doped polycrystalline silicon. For example, it may include polycrystalline silicon including boron (B). The first gate electrode 102a may be used as a floating gate.

The dielectric pattern 113 may be directly formed on the first gate electrode 102a. The dielectric pattern 113 may include a first oxide layer pattern 113a, a nitride layer pattern 113b, and a second oxide layer pattern 113c sequentially stacked. Side surfaces of the dielectric pattern 113 and the first gate electrode 102a may be vertically aligned. The first oxide layer pattern 113a may include silicon oxide, the nitride layer pattern 113b may include silicon nitride, and the second oxide layer pattern 113c may include metal oxide or silicon oxide. For example, the metal oxide may include one of aluminum oxide (Al 2 O 3), hafnium oxide (HfO), titanium oxide (TiO 2), tantalum oxide (TaO 2), and various other metal oxides.

The second gate electrode 104a may be directly formed on the dielectric pattern 113. The side of the second gate electrode 104a and the side of the dielectric pattern 113 may be vertically aligned. The second gate electrode 104a may include doped polycrystalline silicon. For example, the second gate electrode 104a may include polycrystalline silicon including phosphorous (P) or arsenic (As). The second gate electrode 104a may be used as a control gate.

The metal gate electrode 105a may be directly formed on the second gate electrode 104a. The side of the metal gate electrode 105a and the side of the second gate electrode 104a may not be vertically aligned. For example, the side surface of the metal gate electrode 105a may be recessed in a horizontal direction than the side surface of the second gate electrode 104a. The first passivation layer pattern 107a may be formed on the recessed side surface of the metal gate electrode 105a. For example, the side surface of the first passivation layer pattern 107a and the side surface of the second gate electrode 104a may be vertically aligned. The metal gate electrode 105a may include a metal such as tungsten, a metal alloy, a metal silicide such as WSi, or a metal compound such as WN. The first passivation layer pattern 107a may include silicon nitride (SiN).

Gate structures 11 according to an embodiment of the inventive concept may further include a hard mask pattern 116. The hard mask pattern 116 may include a first hard mask pattern 116a formed on the metal gate electrode 105a and a second hard mask pattern 116b formed on the first hard mask pattern 116a. The second hard mask pattern 116b may be thicker than the first hard mask pattern 116a. Upper corners of the second hard mask pattern 116b may be rounded. The first hard mask pattern 116a may include silicon nitride (SiN) or silicon oxynitride (SiON). The second hard mask pattern 116a may include silicon oxynitride (SiON) or silicon nitride (SiN).

The semiconductor device 10 according to an embodiment of the inventive concept may include a second insulating layer pattern 109 surrounding outer walls of the gate structures 11. The second insulating layer pattern 109 may include a side of the first insulating layer pattern 101a, a side of the first gate electrode 102a, a side of the dielectric pattern 113, a side of the second gate electrode 104a, and a metal gate electrode ( Conformally formed on the side of 105a) and / or the side of the hard mask pattern 116. The second insulating layer pattern 109 may be continuously connected in a bridge form or materially between the hard mask patterns 116 of the gate structures 11. The second insulating layer pattern 109 may be formed in an overhang shape between the hard mask patterns 116 of the gate structures 11. The second insulating layer pattern 109 may include silicon oxide.

The semiconductor device 10 according to an embodiment of the inventive concept may include an air gap 110 formed between the gate structures 11. The air gap 110 may be defined by the second insulating layer pattern 109. Since the air has the lowest dielectric constant, the gate structures 11 according to an embodiment of the inventive concept may prevent or alleviate mutual inducing and coupling effects.

2 to 15 are longitudinal cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with some example embodiments of the inventive concepts.

2, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include preparing a substrate 100. The substrate 100 may include a single crystal silicon substrate or a silicon on insulator (SOI) substrate.

Referring to FIG. 3, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include forming a first insulating layer 101 on a substrate 100. The first insulating layer 101 may be conformally formed directly on the surface of the substrate 100. The first insulating layer 101 may include silicon oxide (SiO 2). Forming the first insulating layer 101 may include performing an oxidation process to oxidize the surface of the substrate 100 using a gas containing oxygen injected at a predetermined temperature. Forming the first insulating film 101 may include a dry oxidation method. Thereafter, the method of manufacturing a semiconductor device according to an embodiment of the inventive concept may further include performing a cleaning process. The cleaning process may include removing contaminants, particles, impurities, and natural oxide films on the first insulating layer 101.

Referring to FIG. 4, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include forming a first conductive layer 102 on the first insulating layer 101. . The first conductive film 102 may include doped polycrystalline silicon. Forming the first conductive film 102 may include performing low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD).

Referring to FIG. 5, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include forming a dielectric film 103 on a first conductive film 102. Forming the dielectric film 103 forms the first oxide film 103a on the first conductive film 102, the nitride film 103b on the first oxide film 103a, and the nitride film 103b. It may include forming the second oxide film 103c. Forming the first oxide film 103a may include depositing silicon oxide. Forming the nitride film 103b may include forming silicon nitride. Forming the second oxide film 103c may include forming a metal oxide. Forming the dielectric film 103 may include performing low pressure chemical vapor deposition, plasma chemical vapor deposition, or atomic layer deposition.

Referring to FIG. 6, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include forming a second conductive film 104 on the dielectric film 103. The second conductive film 104 may include doped polycrystalline silicon. Forming the second conductive film 104 may include performing low pressure chemical vapor deposition or plasma chemical vapor deposition.

Referring to FIG. 7, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include forming a metal film 105 on a second conductive film 104. The metal film 105 may include tungsten or a metal compound. Forming the metal film 105 may include performing a sputtering method.

Referring to FIG. 8, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include forming a hard mask layer 106 on a metal layer 105. The hard mask film 106 may include a first hard mask film 106a and a second hard mask film 106b. The first hard mask layer 106a may include silicon nitride (SiN). The second hard mask layer 106b may include silicon oxynitride (SiON).

9, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include forming a hard mask pattern 116. The hard mask pattern 116 may include a first hard mask pattern 116a and a second hard mask pattern 116b. Forming the hard mask pattern 116 may include performing an exposure process and an etching process using a photolithography process.

Referring to FIG. 10, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include forming a metal gate electrode 105a. Forming the metal gate electrode 105a may include etching the metal film 105 using the hard mask pattern 116 as a patterning mask. The etching may include an anisotropic dry etching method using a plasma or the like. In this process, a portion of the second conductive film 104 may be removed to recess the surface. The recessed surface of the second conductive layer 104 may include vertical surfaces aligned vertically with the side surfaces of the metal gate electrode 105a. An edge of the top surface of the second hard mask pattern 116b may be rounded.

Referring to FIG. 11, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include partially removing side surfaces of the metal gate electrode 105a. The metal gate line width d3 of the metal gate electrode 105a having the side surface partially removed may be smaller than the gate line width d1 of the gate structures 11. Partly removing the side of the metal gate electrode 105a may include performing a wet etching process.

Referring to FIG. 12, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include conformally forming a first passivation layer 107 on an entire surface thereof. The first passivation layer 107 may include silicon nitride (SiN). The first passivation layer 107 may cover exposed surfaces of the hard mask pattern 116, the metal gate electrode 105a, and the second conductive layer 104. For example, the first passivation layer 107 may cover the top and side surfaces of the second hard mask pattern 116b. The first passivation layer 107 may cover side surfaces of the first hard mask pattern 106a. The first passivation layer 107 may cover side surfaces of the metal gate electrode 105a. The first passivation layer 107 may cover the surface of the second conductive layer 104. The first passivation layer 107 may cover recess portions of the second conductive layer 104, that is, vertical surfaces aligned vertically with side surfaces of the metal gate electrode 105a. Forming the first passivation layer 107 may include performing a low pressure chemical vapor deposition method, a plasma chemical vapor deposition method, or an atomic layer deposition method.

Referring to FIG. 13, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include forming a second gate electrode 104a. Forming the second gate electrode 104a may include performing an etching process. Forming the second gate electrode 104a may include etching the second conductive layer 104 using the hard mask pattern 116 as a patterning mask. In this process, most of the first passivation film 107 can be removed. For example, only a portion of the first passivation layer 107 may remain on the recessed side surface of the metal gate electrode 105a to be formed as the first passivation layer pattern 107a. Also, part of the dielectric film 103 can be removed in this process. Forming the second gate electrode 104a may include an anisotropic dry etching process using plasma or the like.

Referring to FIG. 14, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include conformally forming a second passivation layer 108 on the entire surface. The second passivation layer 108 may protect the first passivation layer pattern 107a to prevent generation of metal by-products during the subsequent etching process of the first conductive layer 102. The second passivation layer 108 may prevent damage when the first gate electrode 102a is formed. The second passivation layer 108 may include silicon oxide (SiO 2). The second passivation layer 108 may cover the exposed surfaces of the hard mask pattern 116, the metal gate electrode 105a, the second conductive layer 104, and the dielectric layer 103. For example, the second passivation layer 108 may cover the top and side surfaces of the second hard mask pattern 116b. The second passivation layer 108 may cover side surfaces of the first hard mask pattern 116a. The second passivation layer 108 may cover side surfaces of the first passivation layer pattern 107a. The second passivation layer 108 may cover the surface of the second gate electrode 104a. The second passivation layer 108 may cover the exposed top surface of the dielectric layer 103. Forming the second passivation layer 108 may include performing a low pressure chemical vapor deposition method, a plasma chemical vapor deposition method, or an atomic layer deposition method.

Referring to FIG. 15, a method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include forming a dielectric pattern 113 and a first gate electrode 102a. Forming the first gate electrode 102a may include an etching process. Forming the dielectric pattern 113 and the first gate electrode 102a may etch portions of the second passivation layer 108, the dielectric layer 103, the first conductive layer 102, and the first insulating layer 101. It may include. Forming the first gate electrode 102a may include an anisotropic dry etching process using plasma or the like.

Referring back to FIG. 1, the method of manufacturing a semiconductor device according to an embodiment of the inventive concept may include forming a second insulating layer pattern 109. The second insulating layer pattern 109 may include silicon oxide (SiO 2). The second insulating layer pattern 109 may cover the top surface of the second hard mask pattern 116b. The second insulating layer pattern 109 may cover side surfaces of the second hard mask pattern 116b. The second insulating layer pattern 109 may cover side surfaces of the first hard mask pattern 116a. The second insulating layer pattern 109 may cover exposed surfaces of the first passivation layer pattern 105a. The second insulating layer pattern 109 may cover the surface of the second gate electrode 104a. The second insulating layer pattern 109 may cover the exposed surface of the dielectric pattern 113. The second insulating layer pattern 109 may cover the surface of the first gate electrode 102a. The second insulating layer pattern 109 may cover the exposed surface of the first insulating layer pattern 101a. The second insulating layer pattern 109 may be formed on the top surface of the substrate 100 exposed between the gate structures 11. The second insulating layer pattern 109 may be formed thicker on the upper surface and the corners of the upper surface than the side surfaces of the gate structures 11. The second insulating layer patterns 109 on the corners of the upper surfaces of the gate structures 11 may be connected to each other to form an air gap between the gate structures 11. For example, the lower surface of the connection portion of the second insulating layer pattern 109 may be concave with respect to the substrate 100. The upper surface of the connection portion of the second insulating layer pattern 109 may be symmetrical with respect to the lower surface. Forming the second insulating layer pattern 109 may include performing a low pressure chemical vapor deposition method, a plasma chemical vapor deposition method, or an atomic layer deposition method.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

10: semiconductor device 11: gate structures
d1: gate line width d2: gate separation distance
d3: metal gate line width 100: substrate
101: first insulating film 101a: first insulating film pattern
102: first conductive film 102a: first gate electrode
103: dielectric film 103a: first oxide film
103b: nitride film 103c: second oxide film
104: second conductive film 104a: second gate electrode
105: metal film 105a: metal gate electrode
106: hard mask film 106a: first hard mask film
106b: second hard mask film 107: first protective film
107a: first protective film pattern 108: second protective film
109: second insulating film pattern 110: air gap
113: dielectric pattern 113a: first oxide film pattern
113b: nitride film pattern 113c: second oxide film pattern
116: hard mask pattern 116a: first hard mask pattern
116b: second hard mask pattern

Claims (10)

A first insulating film, a first conductive film, a dielectric film, a second conductive film, a metal film, and a hard mask film are sequentially formed on the substrate,
Patterning the hard mask layer to form a hard mask pattern,
Patterning the metal layer using the hard mask pattern as a patterning mask to form a metal gate electrode with exposed side surfaces,
Forming a first passivation layer on the exposed side surface of the metal gate electrode,
Patterning the second conductive layer using the hard mask pattern as a patterning mask to form a second gate electrode with exposed side surfaces,
Forming a second passivation layer on the exposed side of the second gate electrode, and
And forming a gate structure by forming the dielectric pattern and the first gate electrode by patterning the dielectric layer and the first conductive layer using the hard mask pattern as a patterning mask. The method according to claim 1,
Forming the hard mask film,
Forming a first hard mask film on the metal film, and
A method of manufacturing a semiconductor device comprising forming a second hard mask film on the first hard mask film. The method of claim 2,
The first protective film,
Conformal top surfaces and side surfaces of the second hard mask pattern, side surfaces of the first hard mask pattern, side surfaces of the metal gate electrode, surfaces of the second conductive layer, and vertical surfaces aligned vertically with side surfaces of the metal gate electrode. Method for manufacturing a semiconductor device to be covered. The method of claim 2,
The second protective film,
A semiconductor device conformally covering top and side surfaces of the second hard mask pattern, side surfaces of the first hard mask pattern, side surfaces of the first passivation layer pattern, side surfaces of the second gate electrode, and an exposed top surface of the dielectric layer. Manufacturing method. The method according to claim 1,
Forming the metal gate electrode,
And removing a portion of the surface of the second conductive film to recess it. The method according to claim 1,
Forming the metal gate electrode,
And partially removing the side surface of the metal film. The method according to claim 1,
Forming the first protective film,
The portions formed on the top and side surfaces of the second hard mask pattern, the side surfaces of the first hard mask pattern, the side surfaces of the metal gate electrode, and the surface of the second conductive layer are removed and formed on the side surfaces of the metal gate electrode. A method of manufacturing a semiconductor device comprising leaving a portion. The method according to claim 1,
Forming the first gate electrode,
A method of manufacturing a semiconductor device comprising removing all of the second protective film. The method according to claim 1,
The method may further include forming a second insulating layer pattern covering the gate structures.
The second insulating film pattern,
Covering side surfaces of the gate structures and an upper surface of the exposed substrate, and
And a second insulating layer pattern formed on side surfaces and top surfaces of the hard mask patterns of the adjacent gate structures. 10. The method of claim 9,
And an air gap is defined between the gate structures by the second insulating layer pattern.
KR1020120003561A 2012-01-11 2012-01-11 Methods of fabricating semiconductor devices KR20130082374A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022007521A1 (en) * 2020-07-10 2022-01-13 长鑫存储技术有限公司 Preparation method for semiconductor structure and semiconductor structure
US11935925B2 (en) 2020-07-10 2024-03-19 Changxin Memory Technologies, Inc. Method for manufacturing semiconductor structure and semiconductor structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022007521A1 (en) * 2020-07-10 2022-01-13 长鑫存储技术有限公司 Preparation method for semiconductor structure and semiconductor structure
US11935925B2 (en) 2020-07-10 2024-03-19 Changxin Memory Technologies, Inc. Method for manufacturing semiconductor structure and semiconductor structure

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