KR20130077463A - Nonvolatile memory device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A nonvolatile memory device and a method for fabricating the same are provided to easily perform an erasing process by supplying enough holes to a memory cell in the erasing process of the memory cell. CONSTITUTION: A channel layer (140) is vertically protruded from a substrate. A hole supplying layer (125) and a gate electrode (150A) are alternately laminated on the channel layer. The hole supplying layer includes a P-type semiconductor. A memory layer is formed between the channel layer and the gate electrode. An insulating layer is formed between the hole supplying layer and the gate electrode.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a nonvolatile memory device,

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device having a three-dimensional structure in which a plurality of memory cells are stacked in a vertical direction from a substrate and a method of manufacturing the same.

A nonvolatile memory device is a memory device in which stored data is retained even if the power supply is interrupted. Currently, various nonvolatile memory devices such as flash memory are widely used.

In particular, recently, as the degree of integration of a non-volatile memory device having a two-dimensional structure for forming memory cells in a single layer on a semiconductor substrate reaches a limit, a plurality of memory cells are formed along a channel layer protruding vertically from the semiconductor substrate A nonvolatile memory device having a three-dimensional structure has been proposed.

However, the conventional three-dimensional nonvolatile memory device generally forms a channel layer with undoped polysilicon and forms a source region and a drain region through n-type doping. Accordingly, there is a problem that the erase operation of the memory cell is not performed smoothly because the hole supply source that can sufficiently supply the holes is not provided in the memory cell.

In order to solve this problem, a method of erasing a memory cell using a GIDL (Gate Induced Drain Leakage) current has been proposed, but it is also difficult to sufficiently supply holes for erasing a memory cell. In addition, when the GIDL current is used, there arises a problem that the characteristic of the device deteriorates due to program / erase cycling.

An embodiment of the present invention can smoothly perform the erase operation without using the GIDL current by sufficiently supplying holes to the memory cell in the erase operation of the memory cell by forming the hole supply layer between the memory cells, / Non-volatile memory device capable of preventing characteristic deterioration due to erase repetition and a method of manufacturing the same.

A nonvolatile memory device according to an embodiment of the present invention includes: a channel layer vertically protruded from a substrate; A plurality of hole supply layers and a plurality of gate electrodes alternately stacked along the channel layer; A memory film interposed between the channel layer and the gate electrode; And an insulating layer interposed between the hole supply layer and the gate electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, including: forming an interlayer insulating film on a substrate; Depositing a plurality of hole supply layers and a plurality of sacrificial layers alternately on the interlayer insulating film; Forming a channel hole exposing the substrate by selectively etching the hole supply layer and the sacrificial layer; Forming a channel layer in the channel hole; Forming a part of the hole supply layer on both sides of the channel hole and a slit hole passing through the sacrificial layer; Removing the sacrificial layer exposed by the slit hole; And sequentially forming a memory film and a gate electrode in a space in which the sacrificial layer is removed.

According to this technology, it is possible to smoothly perform the erase operation without using the GIDL current by sufficiently supplying the holes to the memory cell during the erase operation of the memory cell by forming the hole supply layer between the memory cells, Can be prevented.

1A to 1E are cross-sectional views illustrating a nonvolatile memory device and a method of manufacturing the same according to a first embodiment of the present invention.
2A to 2D are cross-sectional views illustrating a nonvolatile memory device and a method of manufacturing the same according to a second embodiment of the present invention.
3A to 3G are cross-sectional views illustrating a nonvolatile memory device and a method of manufacturing the same according to a third embodiment of the present invention.

Hereinafter, the most preferred embodiment of the present invention will be described. In the drawings, the thickness and the spacing are expressed for convenience of explanation, and can be exaggerated relative to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. It should be noted that, in the case of adding the reference numerals to the constituent elements of the drawings, the same constituent elements have the same number as much as possible even if they are displayed on different drawings.

1A to 1E are cross-sectional views illustrating a nonvolatile memory device and a method of manufacturing the same according to a first embodiment of the present invention. Particularly, FIG. 1E is a cross-sectional view showing a non-volatile memory device according to the first embodiment of the present invention, and FIGS. 1A to 1D are cross-sectional views showing an example of an intermediate process step for manufacturing the device shown in FIG. 1E.

Referring to FIG. 1A, an interlayer insulating layer 120 is formed on a substrate 100. The substrate 100 may be a semiconductor substrate such as monocrystalline silicon and may include a predetermined substructure (not shown). In addition, the interlayer insulating film 120 may be formed of an oxide film or a nitride film material.

Subsequently, a plurality of hole supplying layers 125 and a plurality of sacrificial layers 130 are alternately laminated on the interlayer insulating film 120. Hereinafter, for convenience of explanation, a structure in which a plurality of hole supplying layers 125 and a plurality of sacrificial layers 130 are alternately stacked will be referred to as a stacked structure. At this time, the hole supplying layer 125 may be disposed at the lowermost portion and the uppermost portion of the stacked structure.

Here, the hole supply layer 125 may be formed of a p-type semiconductor, for example, p + polysilicon, to sufficiently supply holes to the memory cell during an erase operation of the memory cell. The sacrifice layer 130 is removed in a subsequent process to serve as a mold for providing a space for forming a gate electrode, which will be described later, as a hole supply layer 125 and a material having an etch selectivity, (SiO ₂ ), or the like. Meanwhile, although four sacrificial layers 130 are shown in this cross-sectional view, this is merely an example, and may be formed more than or less than four.

Referring to FIG. 1B, the stacked structure and the interlayer insulating layer 120 are selectively etched to form a channel hole H1 for exposing the substrate 100. The channel hole H1 may have a circular or elliptic shape when viewed on a plane, and a plurality of the channel holes H1 may be arranged in a matrix form.

Subsequently, a channel layer 140 is formed in the channel hole H1. The channel layer 140 may be formed of a semiconductor material, such as polysilicon. The channel layer 140 may be formed to have a thickness enough to completely fill the channel hole H1 but the present invention is not limited thereto. In another embodiment, the channel layer 140 may be formed in the channel hole H1, It may be formed to have a thin thickness that does not completely fill the space.

1C, the remaining hole supplying layer 125 and the sacrificing layer 130 except for the hole supplying layer 125 located at the lowermost part of the stacked structure are selectively etched to form a hole supplying layer 125 and the sacrificial layer 130 are formed. A plurality of the slit holes T may be arranged in a slit shape extending in a direction intersecting the main end face and the remaining hole supply layer 125 may be referred to as a hole supply layer pattern 125A.

When the interlayer insulating layer 120 is formed of a material having an etch selectivity with respect to the sacrificial layer 130, for example, a material having a nitride-based material, the material is etched to the hole supply layer 125 located at the lowermost portion of the stacked structure, T may be used to separate all the hole supplying layers 125 from each other.

Then, the sacrificial layer 130 exposed by the slit hole T is removed. At this time, a wet etching process using an etching selectivity with the hole supply layer pattern 125A may be performed to remove the sacrifice layer 130. The hole supply layer 125 positioned at the lowermost portion of the stack structure may be formed by a dry etching process, Thereby preventing the substrate 120 from being etched.

Referring to FIG. 1D, a memory film 145 is formed along the inner space of the space where the sacrificial layer 130 is removed through the slit hole T. FIG.

Here, the memory film 145 may be formed by sequentially depositing a tunnel insulating film, a charge trap film, and a charge blocking film. For example, the tunnel insulating film may be made of, for example, an oxide film. The charge trapping film may be formed of, for example, a nitride film for trapping charges to store data. For example, an oxide film. That is, the memory layer 145 may have a triple-layered structure of ONO (Oxide-Nitride-Oxide).

Then, a conductive film 150 for a gate electrode is formed on the memory film 145 so that the sacrificial layer 130 is buried in the removed space. The conductive film 150 for the gate electrode includes a metal or a metal nitride that can be conformally deposited by a conductive material such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD) can do.

1E, the memory film 145 in the slit hole T and the conductive film 150 for the gate electrode are etched to form the memory film 145 and the conductive film 150 for the gate electrode into the slit hole T . As a result of this process, the gate electrode 150A is formed between the hole supply layer patterns 125A, and the remaining memory film 145 is referred to as a memory film pattern 145A.

Although the memory layer pattern 145A may be interposed between the channel layer 140 and the gate electrode 150A and between the hole supply layer pattern 125A and the gate electrode 150A in the present embodiment, And a single insulating film such as an oxide film or a nitride film may be interposed between the hole supplying layer pattern 125A and the gate electrode 150A in place of the memory film pattern 145A.

By the above-described manufacturing method, the nonvolatile memory device according to the first embodiment of the present invention as shown in FIG. 1E can be manufactured.

1E, the nonvolatile memory device according to the first embodiment of the present invention includes a channel layer 140 vertically protruded from a substrate 100, a plurality of holes alternately stacked along the channel layer 140, A supply layer pattern 125A and a plurality of gate electrodes 150A, a memory film pattern 145A interposed between the channel layer 140 and the gate electrode 150A, and a hole supply layer pattern 125A and a gate electrode 150A And an insulating film interposed therebetween.

Here, the hole supplying layer pattern 125A may be a p-type semiconductor, for example, p + polysilicon for sufficiently supplying holes required for the erasing operation of the memory cell.

2A to 2D are cross-sectional views illustrating a nonvolatile memory device and a method of manufacturing the same according to a second embodiment of the present invention. In the following description of the present embodiment, a detailed description of parts that are substantially the same as those of the above-described first embodiment will be omitted. First, the process of FIG. 1A is performed as in the first embodiment, and the processes of FIGS. 2A to 2D are performed.

2A, a structure in which a plurality of hole supply layers 125 and a plurality of sacrificial layers 130 are alternately stacked and an interlayer insulating layer 120 are selectively etched to form a channel hole H1 ). The channel hole H1 may have a circular or elliptic shape when viewed on a plane, and a plurality of the channel holes H1 may be arranged in a matrix form.

Next, a protective film 135 is formed on the sidewall of the channel hole H1, and a channel layer 140 is formed in the channel hole H1. The channel layer 140 may be formed of a semiconductor material, such as polysilicon.

Here, the protective layer 135 prevents the channel layer 140 from being etched in a subsequent process for removing the sacrificial layer 130, and may be formed of an oxide layer or a nitride layer material. Particularly, it is possible to tunnel the holes by adjusting the thickness of the protective layer 135, or completely isolate the hole supply layer 125 and the channel layer 140 from each other.

2B, the remaining hole supplying layer 125 and the sacrificing layer 130 except for the hole supplying layer 125 located at the lowermost portion of the stacked structure are selectively etched to form a hole supplying layer 125 on both sides of the channel hole H1 ) And the sacrificial layer 130 are formed. A plurality of the slit holes T may be arranged in parallel to each other in a slit shape extending in a direction crossing the main end face and the remaining hole supply layer 125 is referred to as a hole supply layer pattern 125A.

Then, the sacrificial layer 130 exposed by the slit hole T is removed. At this time, in order to remove the sacrificial layer 130, a wet etching process using an etching selection ratio with the hole supply layer pattern 125A may be performed.

Referring to FIG. 2C, the memory layer 145 is formed along the inner space of the space where the sacrificial layer 130 is removed through the slit hole T. The memory layer 145 may be formed by sequentially depositing a tunnel insulating layer, a charge trap layer, and a charge blocking layer, and may have a triple-layered structure of ONO (Oxide-Nitride-Oxide). On the other hand, the protective layer 135 may serve as a tunnel insulating layer. In this case, the deposition process of the tunnel insulating layer may be omitted.

Then, a conductive film 150 for a gate electrode is formed on the memory film 145 so that the sacrificial layer 130 is buried in the removed space. The conductive film 150 for the gate electrode may comprise a conductive material such as a metal or metal nitride that can be conformally deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) techniques.

The memory film 145 in the slit hole T and the conductive film 150 for the gate electrode are etched to form the memory film 145 and the conductive film 150 for the gate electrode into the slit hole T . As a result of this process, the gate electrode 150A is formed between the hole supply layer patterns 125A, and the remaining memory film 145 is referred to as a memory film pattern 145A.

The second embodiment differs from the first embodiment in that the protective film 135 surrounding the side surface of the channel layer 140 is formed.

3A to 3G are cross-sectional views illustrating a nonvolatile memory device and a method of manufacturing the same according to a third embodiment of the present invention. In the following description of the present embodiment, a detailed description of portions that are substantially the same as those of the above-described first or second embodiment will be omitted.

Referring to FIG. 3A, a first pass gate electrode layer 105 is formed on a substrate 100. The substrate 100 may be a semiconductor substrate such as monocrystalline silicon and the first pass gate electrode layer 105 may be formed of a conductive material such as doped polysilicon or metal.

Next, the first pass gate electrode layer 105 is selectively etched to form a trench, and then a sacrificial film pattern 110 is formed in the trench.

Here, the sacrificial pattern 110 is removed in a subsequent process to provide a space for forming a sub-channel hole, which will be described later, and a second pass gate electrode layer, an interlayer insulating film, a hole supply layer, a sacrificial layer, (105) and an etch selectivity ratio. In addition, the sacrificial film pattern 110 may be arranged in a matrix form when viewed on a plane, and may have an island shape having a major axis in the main section direction and a minor axis in the direction crossing the main section.

Next, a second pass gate electrode layer 115 is formed on the first pass gate electrode layer 105 and the sacrificial layer pattern 110. The second pass gate electrode layer 115 may be formed of a conductive material such as doped polysilicon or metal. On the other hand, the first and second pass gate electrode layers 105 and 115 may have a form surrounding the sacrificial pattern 110 as a gate electrode of the pass transistor.

3B, an interlayer insulating layer 120 is formed on the second pass gate electrode layer 115, and a plurality of hole supplying layers 125 and a plurality of sacrificial layers 130 are formed on the interlayer insulating layer 120 Stack alternately. The interlayer insulating film 120 may be formed of an oxide film or a nitride film material.

Here, the hole supply layer 125 may be formed of a p-type semiconductor, for example, p + polysilicon, to sufficiently supply holes to the memory cell during the erase operation of the memory cell. In addition, the sacrificial layer 130 may be formed of a material having an etch selectivity with the hole supply layer 125, for example, an oxide based material, as a layer which is removed in a subsequent process and provides a space for forming a gate electrode described later .

Referring to FIG. 3C, a pair of channel holes H1 are formed to selectively expose the sacrificial layer pattern 110 by selectively etching the stacked structure, the interlayer insulating layer 120, and the second pass gate electrode layer 115. The channel holes H1 may be arranged for each sacrificial pattern 110 as a space for forming a channel layer to be described later.

Then, the sacrificial film pattern 110 exposed by the pair of channel holes H1 is removed. At this time, in order to remove the sacrificial layer pattern 110, a wet etching process using the etch selectivity ratio between the first and second pass gate electrode layers 105 and 115, the interlayer insulating layer 120, and the stacked structure may be performed. As a result of this process, the sub-channel hole H2 connecting the pair of channel holes H1 is formed in the space where the sacrificial film pattern 110 is removed.

Referring to FIG. 3D, a passivation layer 135 is formed along inner walls of the pair of channel holes H1 and the sub-channel holes H2. The protective layer 135 formed on the inner wall of the channel hole H1 serves to prevent the channel layer 140 from being etched in a subsequent process for removing the sacrificial layer 130, The protective film 135 formed on the gate insulating film 140 serves as a gate insulating film of the pass transistor.

Subsequently, a channel layer 140 is formed in the pair of channel holes H1 and the sub-channel holes H2. The channel layer 140 may be divided into a main channel layer used as a channel of a memory cell or a selection transistor, and a sub channel layer used as a channel of a pass transistor, and may be formed of a semiconductor material such as polysilicon.

3E, the remaining hole supplying layer 125 and the sacrificing layer 130 except for the hole supplying layer 125 located at the lowermost portion of the stacked structure are selectively etched to form the hole supplying layer 125 ) And the sacrificial layer 130 are formed. A plurality of the slit holes T may be arranged in a slit shape extending in a direction intersecting the main end face and the remaining hole supply layer 125 may be referred to as a hole supply layer pattern 125A.

Then, the sacrificial layer 130 exposed by the slit hole T is removed. At this time, in order to remove the sacrificial layer 130, a wet etching process using an etching selection ratio with the hole supply layer pattern 125A may be performed.

Referring to FIG. 3F, the memory layer 145 is formed along the inner wall of the space where the sacrificial layer 130 is removed through the slit hole T. FIG. The memory layer 145 may be formed by sequentially depositing a tunnel insulating layer, a charge trap layer, and a charge blocking layer, and may have a triple-layered structure of ONO (Oxide-Nitride-Oxide). On the other hand, the protective layer 135 may serve as a tunnel insulating layer. In this case, the deposition process of the tunnel insulating layer may be omitted.

Then, a conductive film 150 for a gate electrode is formed on the memory film 145 so that the sacrificial layer 130 is buried in the removed space. The conductive film 150 for the gate electrode may comprise a conductive material such as a metal or metal nitride that can be conformally deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) techniques.

3G, the memory film 145 in the slit hole T and the conductive film 150 for the gate electrode are etched to form the memory film 145 and the conductive film 150 for the gate electrode in the slit hole T . As a result of this process, the gate electrode 150A is formed between the hole supply layer patterns 125A, and the remaining memory film 145 is referred to as a memory film pattern 145A.

In the third embodiment, a pass gate electrode composed of first and second pass gate electrode layers 105 and 115 is formed below the interlayer insulating film 120, and the pass gate electrode is provided with a sub- Which is different from the second embodiment in that it has a channel layer.

According to the nonvolatile memory device and the method for fabricating the nonvolatile memory device according to an embodiment of the present invention described above, a hole supplying layer is formed between memory cells, so that holes can be sufficiently supplied to the memory cells during the erasing operation of the memory cells. Accordingly, the erase operation can be performed smoothly without using a GIDL (Gate Induced Drain Leakage) current, and characteristic deterioration due to program / erase cycling can be prevented.

It should be noted that the technical spirit of the present invention has been specifically described in accordance with the above-described preferred embodiments, but the above-described embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

100: substrate 105: first pass gate electrode layer
110: a sacrificial layer pattern 115: a second pass gate electrode layer
120: interlayer insulating film 125A: hole supplying layer pattern
130: sacrificial layer 135: protective film
140: channel layer 145A: memory film pattern
150A: gate electrode H1: channel hole
H2: Sub channel hole T: Slit hole

Claims (10)

A channel layer vertically protruding from the substrate;
A plurality of hole supply layers and a plurality of gate electrodes alternately stacked along the channel layer;
A memory film interposed between the channel layer and the gate electrode; And
And an insulating film interposed between the hole supply layer and the gate electrode
A non-volatile memory device.
The method according to claim 1,
Wherein the hole supplying layer includes a p-type semiconductor
A non-volatile memory device.
The method according to claim 1,
And a protective film surrounding the channel layer side surface
A non-volatile memory device.
The method according to claim 1,
A sub channel layer connecting the pair of channel layers to each other; And
And a pass gate electrode contacting the sub-channel layer via a gate insulating film
A non-volatile memory device.
5. The method of claim 4,
Wherein the pass gate electrode comprises a conductive layer over the sub-channel layer
A non-volatile memory device.
Forming an interlayer insulating film on the substrate;
Depositing a plurality of hole supply layers and a plurality of sacrificial layers alternately on the interlayer insulating film;
Forming a channel hole exposing the substrate by selectively etching the hole supply layer and the sacrificial layer;
Forming a channel layer in the channel hole;
Forming a part of the hole supply layer on both sides of the channel hole and a slit hole passing through the sacrificial layer;
Removing the sacrificial layer exposed by the slit hole; And
And sequentially forming a memory film and a gate electrode in a space in which the sacrificial layer is removed
A method of manufacturing a nonvolatile memory device.
The method according to claim 6,
The hole-supplying layer is formed of a p-type semiconductor
A method of manufacturing a nonvolatile memory device.
The method according to claim 6,
Before the channel layer forming step,
And forming a protective film on the sidewall of the channel hole
A method of manufacturing a nonvolatile memory device.
The method according to claim 6,
Before the step of forming the interlayer insulating film,
Further comprising forming a pass gate electrode on the substrate
A method of manufacturing a nonvolatile memory device.
10. The method of claim 9,
After the channel hole forming step,
And forming a sub-channel hole in the pass gate electrode to connect a pair of the channel holes to each other
A method of manufacturing a nonvolatile memory device.

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