KR20130077069A - Manufacturing method of led package - Google Patents

Manufacturing method of led package Download PDF

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Publication number
KR20130077069A
KR20130077069A KR1020110145581A KR20110145581A KR20130077069A KR 20130077069 A KR20130077069 A KR 20130077069A KR 1020110145581 A KR1020110145581 A KR 1020110145581A KR 20110145581 A KR20110145581 A KR 20110145581A KR 20130077069 A KR20130077069 A KR 20130077069A
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South Korea
Prior art keywords
substrate
conductive
conductive solder
layer
solder bumps
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KR1020110145581A
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Korean (ko)
Inventor
지현아
Original Assignee
하나 마이크론(주)
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Priority to KR1020110145581A priority Critical patent/KR20130077069A/en
Publication of KR20130077069A publication Critical patent/KR20130077069A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
    • H01L33/502—Wavelength conversion materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/56—Materials, e.g. epoxy or silicone resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Device Packages (AREA)

Abstract

PURPOSE: A method for manufacturing an LED package is provided to electrically connect chips without performing a wire bonding process by using a solder bump and an electrode pattern formed on an upper glass substrate. CONSTITUTION: A conductive pad (270) is formed on a substrate. A first substrate (260) is formed on the conductive pad. A second substrate (210) having a second conductive solder bump is formed. The first substrate is bonded to the second substrate. A resin layer (280) is formed between the first substrate and the second substrate.

Description

Manufacturing method of LED package {Manufacturing method of LED Package}

The present invention relates to a method of manufacturing an LED package, and more particularly, to a method of manufacturing an LED package that can be electrically connected to form an electrode pattern on the upper glass substrate and without the wire bonding process of the LED chip through the solder bumps.

In general, a light emitting diode (LED) is a semiconductor device that emits light when a current flows, and converts electrical energy into light energy using a PN junction diode made of GaAs and GaN optical semiconductors.

Factors determining such LED characteristics include color, brightness, and light conversion efficiency. The characteristics of these products are determined by the compound semiconductor material and its structure used in the LED chip, but also by the structure for mounting the LED chip. It is greatly affected.

Therefore, in order to obtain a luminous effect according to the user's demand, it is necessary to improve the structure of the LED package and the material used therein, in addition to the material or structure of the LED chip. In particular, as the application range of LED packages is gradually expanded from small lights, such as mobile terminals, to indoor and outdoor general lighting, automotive lighting, and large liquid crystal display (LCD) backlights, high efficiency and brightness Efforts are underway to improve this.

1 is a view schematically showing the structure of a conventional ceramic LED package. As shown in FIG. 1, in the conventional ceramic LED package, the LED chip 104 is mounted on the heat dissipation via hole 102 formed at the center of the substrate 101, and the substrate 101 is connected to the substrate 101 through the conductive wire 105. The LED chip 104 is electrically connected.

Next, the LED package is completed by forming the molding layer 107 by the lens portion 108 of the transparent resin including the phosphor on the substrate on which the LED chip 104 is formed.

However, such a conventional LED package 100 has a problem that the bonding of the wire is easily generated by the LED chip 104 and the conductive wire is formed on top.

The technical problem to be solved by the present invention is to provide a method of manufacturing an LED package that can be formed by forming an electrode pattern on the upper glass substrate and electrically connected through a solder bump without a wire bonding process of the LED chip.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, unless further departing from the spirit and scope of the invention as defined by the appended claims. It will be possible.

In the manufacturing method of the LED package according to the present invention for solving the above technical problem, a conductive pad is formed by applying a conductive material on a substrate in a predetermined pattern, the first conductive solder bumps are formed on the conductive pad at predetermined intervals Providing a first substrate, mounting a LED chip, and preparing a second substrate having a second conductive solder bump corresponding to a position at which the first conductive solder pump is formed; Bonding the first substrate and the second substrate so that the second conductive solder bumps correspond to each other, and underfilling a resin layer to be formed between the first substrate and the second substrate. It has that feature.

In particular, the preparing of the second substrate may include forming sequentially an insulating layer, a metal layer, and a PSR layer on the metal substrate; Etching the metal layer to expose one region of the metal substrate, and forming a predetermined pattern on the PSR layer to expose a predetermined region of the metal layer; Mounting an LED chip on a region where the metal substrate is exposed; And forming a second conductive solder bump on a predetermined region where the metal layer is exposed.

In particular, the PSR layer is characterized in that a predetermined pattern is formed such that the metal layer is exposed at a position where the second conductive solder bump is formed.

In particular, the second conductive solder bumps are characterized in that they are formed by adjusting the height to be the same as the height formed by the LED chip and the first conductive solder bumps.

Here, in particular, the resin layer is characterized in that it is formed of a mixed material of phosphor and silicon.

In addition, the manufacturing method of the LED package according to the present invention, by applying a conductive material on the substrate, the conductive pad is formed in a predetermined pattern to correspond to the plurality of LED chips, the first conductive solder bumps on the conductive pad at predetermined intervals Providing a first substrate on which is formed; Providing a second substrate on which a plurality of LED chips are mounted and a common electrode pad for electrically connecting to the plurality of LED chips is formed, and a second conductive solder bump is formed corresponding to a position where the first conductive solder pump is formed; Wow; Bonding the first substrate and the second substrate such that the first conductive solder bumps and the second conductive solder bumps correspond to each other; And underfilling the resin layer to form a space between the first substrate and the second substrate.

Here, the plurality of LED chips formed on the second substrate is characterized in that it is formed in a vertical structure or a lateral structure.

The preparing of the second substrate may include forming an insulating layer, a metal layer, and a PSR layer sequentially on the metal substrate; Etching the metal layer to expose one region of the metal substrate, and forming a predetermined pattern of the PSR layer to expose a predetermined region of the metal layer; Mounting an LED chip on a region where the metal substrate is exposed; And forming a second conductive solder bump on a predetermined region where the metal layer is exposed.

Here, the PSR layer is characterized in that a predetermined pattern is formed to expose the metal layer at a position where the second conductive solder bump is formed.

Here, the second conductive solder bumps are characterized in that the height is formed to be the same as the height formed by the LED chip and the first conductive solder bumps.

According to the present invention, a method of manufacturing an LED package may form an electrode pattern on an upper glass substrate and may be electrically connected through a solder bump without a wire bonding process of the LED chip.

In addition, chip protection and phosphors may be formed between the upper substrate and the lower substrate of the LED package through an underfill process.

In addition, it can be applied to the manufacturing method of a plurality of LED packages through the manufacturing method of the LED package.

1 is a view schematically showing the structure of a conventional ceramic LED package.
2 is a view schematically showing the structure of an LED package according to an embodiment of the present invention.
3a to 3d is a flow chart for a method of manufacturing an LED package according to the present invention.
Figure 4 schematically shows the structure of a multi-LED package of the lateral structure according to the present invention.
5 is a view schematically showing the structure of a multi-LED package of a vertical structure according to the present invention.
6A to 6C are flowcharts illustrating a method of manufacturing an LED package according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the detailed description of known functions and configurations incorporated herein will be omitted when it may unnecessarily obscure the subject matter of the present invention.

The same reference numerals are used for portions having similar functions and functions throughout the drawings.

In addition, in the entire specification, when a part is referred to as being 'connected' to another part, it may be referred to as 'indirectly connected' not only with 'directly connected' . Also, to include an element does not exclude other elements unless specifically stated otherwise, but may also include other elements.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a view schematically showing the structure of an LED package according to an embodiment of the present invention. As shown in FIG. 2, the LED package according to the present invention includes an LED chip 211, a first substrate 260 having a conductive pad 270 formed in a predetermined pattern, and spaced apart from the first substrate 260. A conductive solder bump 250 disposed to electrically connect the second substrate 210 to mount the LED chip 211 and the LED chip 211 through a conductive pad 270 of the first substrate 210. ) And an underfill resin layer 280 filled between the first substrate 260 and the second substrate 210.

The first substrate 260 is formed of a glass material, and a conductive material is coated on one surface of the first substrate 260 corresponding to the second substrate 210 to be etched in a predetermined pattern to form a conductive pad 270. ). That is, the conductive pad 270 may be electrically connected to the LED chip 211 without wire bonding.

The second substrate 210 may include a base substrate 210 formed of a metal material, an insulating layer 220, a metal layer 230, and a PSR layer 240 sequentially formed to expose a region of the base substrate, and LED chip 211 is mounted on one exposed area of the base substrate.

In more detail, the second substrate 210 forms an insulating layer 220 by applying an insulating material on a base substrate, which is a metal substrate, and forms a metal layer 230 by applying a metal material again. In this case, the metal layer 230 is formed to be electrically connected to an external electrode.

The insulating layer 220, the metal layer 230, and the PSR layer 240 sequentially formed on the second substrate 210 may etch a predetermined area so that the LED chip 211 may be mounted to form the cavity 212. To form. In addition, the PSR layer 240 forms a predetermined pattern at a position where the conductive solder bumps 250b are provided to prevent the conductive solder bumps 250b from flowing to the outside. The metal layer 230 is exposed and electrically connected to the conductive solder bumps 250.

The LED chip 211 is mounted on the cavity 212 of the second substrate 210 by an adhesive, and both electrodes formed on the LED chip 211 are electrically connected by conductive solder bumps 250a. . The LED chip 211 may be composed of a GaAs-based or GaN-based LED chip.

The conductive solder bumps 250 may include a first conductive solder bump 250a formed to connect one end of the conductive pad 270 of the first substrate 260 to the electrodes of the LED chip 211, respectively, and the first The second conductive solder bump 250b is formed between the other end of the conductive pad of the substrate 260 and the metal layer 230 connecting to the external electrode of the second substrate 210. In this case, the height of the second conductive solder bump 250b is preferably formed to be the same as the height formed by the LED chip 211 and the first conductive solder bump 250a.

The underfill resin layer 280 is formed of a mixed material of phosphor and silicon. That is, the underfill resin layer 280 is preferably made of a mixture of a phosphor and a transparent resin so that the light emitted from the LED chip 211 can be transmitted.

In the process of injecting the underfill resin layer 280, a vacuum is generated, and an underfill material is injected through the inlet. The underfill material is assisted by the vacuum and the injection pressure of the material, flowing into all the cavities through the channels between the cavities. At this time, the vacuum removes almost all the air in the interior and may be filled with the underfill material. It can then be heated to cure the underfill material or can be cured with UV light.

3A to 3D are flowcharts illustrating a method of manufacturing the LED package according to the present invention. As illustrated in FIG. 3A, a conductive material is coated on a substrate to form a conductive pad 270 in a predetermined pattern, and a first conductive solder bump 250a is formed on the conductive pad 270 at predetermined intervals. The step of preparing the first substrate 260 is performed. In other words, the first substrate 260 is made of glass, and the conductive pad 270 is formed on one surface of the first substrate 260 corresponding to the second substrate 210 by using a sputtering method. Form. That is, the conductive pad 270 may be electrically connected to the LED chip 211 without wire bonding. Here, the conductive pad 270 is preferably formed of indium tin oxide (ITO), but is not necessarily limited thereto.

The first conductive solder bumps 250a are formed at predetermined intervals such that one end of the conductive pad 270 of the first substrate 260 and the electrodes of the LED chip 211 are connected to each other. Here, it is preferable to use Ag in the conductive metal material as the first conductive solder bump 250a.

Next, as shown in FIG. 3B, the second substrate 210 on which the LED chip 211 is mounted and the second conductive solder bumps 250b are formed corresponding to the position where the first conductive solder pump 250a is formed. ) Is performed.

More specifically, the second substrate 210 is composed of a metal disc, an insulating layer, and a metal layer, and the metal layer is generally copper (Cu), and may be coated with Ag to prevent corrosion of Cu and increase reflectivity. In this case, the metal layer may be etched in a desired pattern to be electrically connected to the external electrode.

The insulating layer 220, the metal layer 230, and the PSR layer 240 sequentially formed on the second substrate 210 may etch a predetermined area so that the LED chip 211 may be mounted to form the cavity 212. To form. In addition, the PSR layer 240 forms a predetermined pattern at a position where the second conductive solder bumps 250b are provided to prevent the second conductive solder bumps 250b from flowing to the outside. The metal layer 230 is exposed by a predetermined pattern to be electrically connected to the second conductive solder bumps 250b. In this case, the second conductive solder bumps 250b are not formed in the region where the LED chip is located, but only in the outer region of the LED chip. The height of the second conductive solder bumps 250b may be the same as the height of the LED chip 211 and the first conductive solder bumps 250a.

The LED chip 211 is mounted on the cavity 212 of the second substrate 210 by an adhesive, and both electrodes formed on the LED chip 211 are electrically connected to each other by the first conductive solder bump 250a. Connected. The LED chip 211 may be composed of a GaAs-based or GaN-based LED chip.

3C, the first substrate 260 and the second substrate 210 are bonded to each other such that the first conductive solder bumps 250a and the second conductive solder bumps 250b correspond to each other. Step is performed.

Finally, as shown in FIG. 3D, an underfill is performed such that a resin layer is formed between the first substrate 260 and the second substrate 210.

In more detail, the underfill resin layer 280 is formed of a mixed material of phosphor and silicon. That is, the underfill resin layer 280 is preferably made of a mixture of a phosphor and a transparent resin so that the light emitted from the LED chip 211 can be transmitted.

In the process of injecting the underfill resin layer 280, a vacuum is generated, and an underfill material is injected through the inlet. The underfill material is assisted by the vacuum and the injection pressure of the material, flowing into all the cavities through the channels between the cavities. At this time, the vacuum removes almost all the air in the interior and may be filled with the underfill material. It can then be heated to cure the underfill material or can be cured with UV light.

4 is a diagram schematically illustrating a structure of a multi-LED package having a lateral structure according to the present invention, and FIG. 5 is a diagram schematically illustrating a structure of a multi LED package having a vertical structure according to the present invention. The multi-LED package structure shown in FIGS. 4 and 5 will be referred to the structure of FIG. 2 and the detailed description thereof will be omitted. 4 and 5 exemplarily illustrate a structure of forming a plurality of LED packages.

6A through 6C are flowcharts illustrating a method of manufacturing an LED package according to another embodiment of the present invention. Here, a detailed description of the LED package manufacturing method will be omitted with reference to FIGS. 3A to 3D.

As shown in FIG. 6A, a conductive material is coated on a substrate to form conductive pads corresponding to the plurality of LED chips in a predetermined pattern, and the first conductive solder bumps and the outer portions are formed on the conductive pads at predetermined intervals. The preparing of the first substrate 560 on which the second conductive solder bumps 530 are formed is performed. In this case, the second conductive solder bump is preferably formed by adjusting the height so as to be the same as the height formed by the LED chip and the first conductive solder bump.

In addition, the fluorescent layer 570 is formed on the first substrate 560 through spray coating, and does not perform a separate underfill process.

As shown in FIG. 6B, a step of preparing a second substrate 510 on which a plurality of LED chips 540 are mounted and a common electrode pad 520 is formed to electrically connect the plurality of LED chips is performed. .

More specifically, the insulating layer, the metal layer and the PSR layer are sequentially formed on the metal substrate, the metal layer is etched to form a cavity so that one region of the metal substrate is exposed, and the PSR is exposed so that a predetermined region of the metal layer is exposed. The layer is formed in a predetermined pattern. The LED chip is mounted on one region where the metal substrate is exposed. Here, the plurality of LED chips formed on the second substrate may be variously formed, such as a vertical structure or a lateral structure.

On the other hand, the PSR layer is preferably etched to expose the metal layer to the portion where the conductive solder bumper and the common electrode pad of the second substrate is formed.

Finally, as shown in FIG. 6C, the first conductive solder bumps correspond to the positive electrodes of each LED chip, and the second conductive solder bumps 530 correspond to the common electrode pads 520 of the second substrate 510. The first substrate 560 and the second substrate 510 are bonded to each other.

While the present invention has been particularly shown and described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of course, this is possible. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the equivalents as well as the claims that follow.

Description of the Related Art
210, 510 --- Second substrate 220 --- Insulation layer
230 --- metal layer 240 --- PSR layer
250, 530 --- conductive solder bumps 260, 560 --- first substrate
270 --- conductive pad 280 --- underfill resin layer
520 --- Common electrode pad 570 --- Fluorescent layer

Claims (11)

Applying a conductive material on the substrate to form a conductive pad in a predetermined pattern, and preparing a first substrate having first conductive solder bumps formed on the conductive pad at predetermined intervals;
Mounting a LED chip and providing a second substrate having a second conductive solder bump corresponding to a position at which the first conductive solder pump is formed;
Bonding the first substrate and the second substrate such that the first conductive solder bumps and the second conductive solder bumps correspond to each other;
And underfilling the resin layer to form a space between the first substrate and the second substrate.
The method of claim 1,
Preparing the second substrate,
Sequentially forming an insulating layer, a metal layer, and a PSR layer on the metal substrate;
Etching the metal layer to expose one region of the metal substrate, and forming the PSR layer in a predetermined pattern to expose a predetermined region of the metal layer;
Mounting an LED chip on a region where the metal substrate is exposed;
And forming a second conductive solder bump on a predetermined region where the metal layer is exposed.
The method of claim 2,
The PSR layer is a manufacturing method of the LED package, characterized in that the predetermined pattern is formed so that the metal layer is exposed to the position where the second conductive solder bump is formed.
The method of claim 1,
The second conductive solder bumps are formed by adjusting the height to be the same as the height formed by the LED chip and the first conductive solder bumps.
The method of claim 1,
The resin layer is a method of manufacturing an LED package, characterized in that formed of a mixture of phosphor and silicon.
A conductive pad is coated on a substrate to form a conductive pad corresponding to the plurality of LED chips in a predetermined pattern, and a first conductive solder bump and a second conductive solder bump are formed on the conductive pad at predetermined intervals. Providing a substrate;
Providing a second substrate on which a plurality of LED chips are mounted and a common electrode pad is formed to electrically connect the plurality of LED chips;
Bonding the first substrate and the second substrate such that the first conductive solder bumps correspond to both electrodes of each LED chip, and wherein the second conductive solder bumps correspond to a common electrode pad of a second substrate. Method of making the package.
The method according to claim 6,
The plurality of LED chips formed on the second substrate is a manufacturing method of the LED package, characterized in that formed in a vertical structure or a lateral structure.
The method according to claim 6,
Preparing the second substrate,
Sequentially forming an insulating layer, a metal layer, and a PSR layer on the metal substrate;
Etching the metal layer to expose a region of the metal substrate to form a cavity, and forming the PSR layer in a predetermined pattern to expose a predetermined region of the metal layer;
And mounting an LED chip on the exposed area of the metal substrate.
The method of claim 8,
The PSR layer is a method of manufacturing an LED package, characterized in that for etching the portion where the conductive solder bumper and the common electrode pad of the second substrate is formed to expose the metal layer.
The method according to claim 6,
The second conductive solder bumps are formed by adjusting the height to be the same as the height formed by the LED chip and the first conductive solder bumps.
The method according to claim 6,
The method of manufacturing an LED package, characterized in that the fluorescent layer is formed on the first substrate.
KR1020110145581A 2011-12-29 2011-12-29 Manufacturing method of led package KR20130077069A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109257872A (en) * 2018-10-23 2019-01-22 广东晶科电子股份有限公司 A kind of Mini LED module and preparation method thereof
KR20190127026A (en) * 2018-05-03 2019-11-13 엘지이노텍 주식회사 Vertical-cavity surface-emitting laser package and an automatic focus device
KR20190128831A (en) * 2018-05-09 2019-11-19 엘지이노텍 주식회사 Vertical-cavity surface-emitting laser package and automatic focusing device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190127026A (en) * 2018-05-03 2019-11-13 엘지이노텍 주식회사 Vertical-cavity surface-emitting laser package and an automatic focus device
KR20190128831A (en) * 2018-05-09 2019-11-19 엘지이노텍 주식회사 Vertical-cavity surface-emitting laser package and automatic focusing device
CN109257872A (en) * 2018-10-23 2019-01-22 广东晶科电子股份有限公司 A kind of Mini LED module and preparation method thereof
CN109257872B (en) * 2018-10-23 2024-03-26 广东晶科电子股份有限公司 Mini LED module and manufacturing method thereof

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