KR20130072014A - Epitaxial wafer and method for preparing pattern - Google Patents

Epitaxial wafer and method for preparing pattern Download PDF

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Publication number
KR20130072014A
KR20130072014A KR1020110139552A KR20110139552A KR20130072014A KR 20130072014 A KR20130072014 A KR 20130072014A KR 1020110139552 A KR1020110139552 A KR 1020110139552A KR 20110139552 A KR20110139552 A KR 20110139552A KR 20130072014 A KR20130072014 A KR 20130072014A
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KR
South Korea
Prior art keywords
pattern
layer
substrate
coating
pattern forming
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Application number
KR1020110139552A
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Korean (ko)
Inventor
황민영
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엘지이노텍 주식회사
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Priority to KR1020110139552A priority Critical patent/KR20130072014A/en
Publication of KR20130072014A publication Critical patent/KR20130072014A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

The pattern forming method according to the embodiment may include preparing a substrate including an epi layer; Forming a coating layer on the epi layer; Heat-treating the coating layer; And etching the epi layer.
An epitaxial substrate according to an embodiment includes a substrate; And an epi layer disposed on the substrate, wherein the epi layer includes a pattern.

Description

Epitaxial substrate and pattern formation method {EPITAXIAL WAFER AND METHOD FOR PREPARING PATTERN}

Embodiments relate to epitaxial substrates and pattern formation methods.

Optical devices are devices that convert light energy into electrical energy when light is used as an energy transmission means or a reception means, and technology and development using light have been actively performed. In the case of a light receiving device that receives light from such an optical device, it is important to increase the light efficiency by widening the surface area and receiving more light.

Therefore, a pattern may be formed on the light receiving unit to increase the surface area. However, when the pattern is formed, a process time and a process cost increase.

The embodiment is to provide a pattern forming method that can improve the surface area.

The pattern forming method according to the embodiment may include preparing a substrate including an epi layer; Forming a coating layer on the epi layer; Heat-treating the coating layer; And etching the epi layer.

An epitaxial substrate according to an embodiment includes a substrate; And an epi layer disposed on the substrate, wherein the epi layer includes a pattern.

In the pattern forming method according to the embodiment, the coating particles formed through the heat treatment of the coating layer can be easily patterned because they act as a mask during etching. Therefore, a process advantage can be secured.

Through the pattern forming method according to the embodiment and the epitaxial substrate according to the embodiment, the pattern may be irregularly formed to increase the surface area of the epi layer. Therefore, when the substrate and the epi layer are applied to the optical element, it is possible to receive a lot of light through the pattern, and to secure an optical element of high efficiency.

1 to 5 are cross-sectional views illustrating a method of forming a pattern according to an embodiment.

In the description of embodiments, each layer, region, pattern, or structure may be “on” or “under” the substrate, each layer, region, pad, or pattern. Substrate formed in ”includes all formed directly or through another layer. The criteria for top / bottom or bottom / bottom of each layer are described with reference to the drawings.

The thickness or the size of each layer (film), region, pattern or structure in the drawings may be modified for clarity and convenience of explanation, and thus does not entirely reflect the actual size.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 5, the pattern formation method according to the embodiment and the epitaxial substrate according to the embodiment will be described in detail. 1 to 5 are cross-sectional views illustrating a method of forming a pattern according to an embodiment.

The pattern forming method according to the embodiment includes preparing a substrate 10, forming a coating layer 30, performing a heat treatment, and etching.

First, referring to FIG. 1, in the preparing of the substrate 10, the substrate 10 including the epi layer 20 may be prepared.

The substrate 10 may include silicon carbide. Since the substrate 10 includes silicon carbide, it is possible to secure a low reflectance and to be applied to an optical device.

The epi layer 20 may be located on the substrate 10. The epitaxial layer 20 may grow on the substrate 10. The epitaxial layer 20 may be grown on the substrate 10 by various methods. For example, the epi layer 20 may be formed through an epitaxial growth method. The epitaxial growth method is a method of forming a single crystal layer by stacking a new layer on the single crystal substrate 10. In this case, when the material of the substrate 10 and the stacked material are the same, it is called a homoepitaxy. The epi layer 20 may include silicon carbide. The epi layer 20 may serve as a light receiving unit that receives light when it is later applied to an optical device.

Subsequently, referring to FIG. 2, the coating layer 30 may be formed. In the forming of the coating layer 30, a coating layer 30 may be formed on the epitaxial layer 20. The coating layer 30 may include a metal. Specifically, the coating layer 30 may include gold (Au) or silver (Ag). The thickness of the coating layer 30 may be 20 nm to 80 nm. When the thickness of the coating layer 30 is less than 20 nm, the bottom up growth of the coating layer 30 may not easily occur later. In addition, when the thickness of the coating layer 30 exceeds 80 nm, the cost may increase.

3, the heat treatment is performed. In the heat treatment step, the substrate 10 may be heat treated at 200 ° C to 500 ° C.

In the heat treatment step, the coating layer 30 may be bottomed up. That is, the coating layer 30 may be grown to form coating particles 32. Specifically, when the heat treatment on the surface of the coating layer 30 and the epi layer 20, the coating particles 32 included in the coating layer 30 is formed. The coating particles 32 may be spaced apart from each other. Specifically, as shown in FIG. 3, the coating layer 30 formed on the entire surface of the epi layer 20 may be grown as the coating particles 32 to expose a part of the surface of the epi layer 20.

Here, the height of the coating particles 32 may be 100 nm to 2000 nm. In addition, the diameter of the coating particles 32 may be 10 nm to 200 nm.

Next, referring to FIG. 4, etching is performed. In the etching step, the epi layer 20 may be plasma treated. In the etching step, an exposed portion of the epi layer 20 may be etched. That is, since the coating particles 32 are not located, etching may occur at the portion where the epitaxial layer 20 is exposed. That is, the top surface of the epitaxial layer 20 in which the coating particles 32 are positioned may act as a mask as the coating particles 32 may not be etched.

In the etching step, the pattern 40 may be formed. The pattern 40 may have a recessed shape from an upper surface of the epi layer 20. That is, the pattern 40 may be in the form of a recess. The depth of the pattern 40 may be 1 um to 4 um.

The pattern 40 may include an inclined surface inclined from an upper surface of the epi layer 20. It is possible to reduce the reflectance of light through the inclined surface.

Subsequently, referring to FIG. 5, the coating particles 32 are removed. In the step of removing the coating particles 32 can be removed using aqua regia. Thus, referring to FIG. 5, the etching may be partially formed to form the pattern 40.

That is, the epitaxial substrate according to the embodiment may include the epitaxial layer 20 including the pattern 40. The pattern 40 may have a recessed recess shape as shown in FIG. 5.

The pattern 40 may be irregularly formed to increase the surface area of the epitaxial layer 20. Therefore, when the substrate 10 and the epi layer 20 are applied to an optical device, efficiency can be improved.

In the pattern forming method according to the embodiment, since the coating particles 32 formed through the heat treatment of the coating layer 30 serve as a mask during etching, the patterning method can be easily patterned.

 The features, structures, effects and the like described in the foregoing embodiments are included in at least one embodiment of the present invention and are not necessarily limited to one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the present invention. It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments may be modified. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

Claims (20)

Preparing a substrate including an epi layer;
Forming a coating layer on the epi layer;
Heat-treating the coating layer; And
Etching the epitaxial layer. The method of claim 1,
The coating layer is a pattern forming method comprising a metal. The method of claim 2,
The coating layer is a pattern forming method comprising gold (Au) or silver (Ag). The method of claim 1,
The thickness of the coating layer is a pattern forming method of 20 nm to 80 nm. The method of claim 1,
In the heat treatment step, the substrate is heat-treated at 200 ℃ to 500 ℃ pattern forming method. The method of claim 1,
In the heat treatment step, the coating layer is grown to form a coating particle pattern. The method of claim 1,
In the heat treatment step, the coating layer is bottom-up (bottom up) growth pattern forming method. The method according to claim 6,
The coating particles are spaced apart from each other pattern formation method. The method according to claim 6,
The height of the coating particles is 100 nm to 2000 nm pattern forming method. The method according to claim 6,
The coating particle diameter is 10 nm to 200 nm pattern forming method. The method of claim 1,
And etching the plasma layer in the etching step. The method of claim 1,
The pattern is formed in the etching step,
The depth of the pattern is 1 um to 4 um pattern forming method. The method of claim 1,
The pattern is a pattern forming method comprising an inclined surface inclined from the upper surface of the epi layer. The method of claim 1,
In the etching step, the exposed portion of the epi layer is etched. The method according to claim 6,
And removing the coating particles after the etching step. 16. The method of claim 15,
In the step of removing the coating particles, a pattern forming method for removing using aqua regia. The method of claim 1,
The substrate and the epi layer comprises a pattern of silicon carbide (SiC). Board; And
An epi layer located on the substrate,
The epitaxial substrate comprises a pattern. 19. The method of claim 18,
The pattern is an epitaxial substrate having a recess shape. 19. The method of claim 18,
An epitaxial substrate having a depth of 1 um to 4 um.
KR1020110139552A 2011-12-21 2011-12-21 Epitaxial wafer and method for preparing pattern KR20130072014A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070063731A (en) * 2005-12-15 2007-06-20 엘지전자 주식회사 Method of fabricating substrate with nano pattern and light emitting device using the substrate
KR20070076829A (en) * 2006-01-20 2007-07-25 엘지전자 주식회사 Method for crystal growth of nitride semiconductor
KR20110013325A (en) * 2009-07-30 2011-02-09 에피스타 코포레이션 Nano patterning substrate and epitaxy structure
KR20110097005A (en) * 2010-02-24 2011-08-31 엘지전자 주식회사 Nitride semiconductor device and method for fabricating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070063731A (en) * 2005-12-15 2007-06-20 엘지전자 주식회사 Method of fabricating substrate with nano pattern and light emitting device using the substrate
KR20070076829A (en) * 2006-01-20 2007-07-25 엘지전자 주식회사 Method for crystal growth of nitride semiconductor
KR20110013325A (en) * 2009-07-30 2011-02-09 에피스타 코포레이션 Nano patterning substrate and epitaxy structure
KR20110097005A (en) * 2010-02-24 2011-08-31 엘지전자 주식회사 Nitride semiconductor device and method for fabricating the same

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