KR20130064508A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to control arrangement of liquid crystal molecular arranged at the edge of the liquid crystal display device, by generating vertical electric field between a first a signal electrode formed at the edge of a first substrate and a second light shielding pattern formed at the edge of a second substrate. CONSTITUTION: A first light shielding pattern(181a) is formed in a lattice form on a second substrate(180), and shields a gate line, a data line(130) and a thin film transistor of each sub pixel corresponding to a first substrate(102). A second light shielding pattern(181b) shields a non-display area including a number of dummy pixels. Liquid crystal molecules are driven in a display area. The liquid crystal molecules are arranged in the non-display area. [Reference numerals] (183a) Red; (183b) Green

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of preventing light leakage.

As the information society develops, Plasma Display Panel (PDP), Organic Electro Luminescence Display (OELD) and Liquid Crystal Display (LCD) are used in cathode ray tube (CRT) displays. Flat panel display devices such as the

Among flat panel displays, in particular, liquid crystal displays are most commonly used as image display devices such as monitors, televisions, and three-dimensional video televisions because of their excellent image quality and various advantages such as light weight, thinness, and low power consumption.

The liquid crystal display device is driven by using the optical anisotropy and polarization properties of the liquid crystal. The liquid crystal molecules are oriented in an array because their structures are thin and long, and artificially apply an electric field to the liquid crystal molecules. You can control the orientation of the array.

When the arrangement of the liquid crystal molecules is changed using the electric field as described above, light is refracted in the arrangement direction of the liquid crystal molecules due to optical anisotropy of the liquid crystal, thereby displaying an image.

The liquid crystal display includes an array substrate manufacturing process for forming a gate wiring, a data wiring, a thin film transistor (TFT) and a pixel electrode on a first substrate, which is an array substrate, and a light shielding pattern on a second substrate, which is a color filter substrate. And a color filter substrate manufacturing process for forming a color filter and a common electrode, the first substrate and the second substrate are bonded together, cut into cell units, and a liquid crystal is injected between the first substrate and the second substrate in the cell unit unit panel. And a module process of attaching a driving integrated circuit (IC) and a printed circuit board (PCB) to a unit panel and assembling with a backlight unit.

Such a liquid crystal display device uses a vertical electric field to drive a liquid crystal by a vertical electric field generated by forming a common electrode and a pixel electrode on different substrates, and a horizontal electric field generated by forming a common electrode and a pixel electrode on the same substrate. It can be divided into a horizontal electric field driving method.

The vertical field type liquid crystal display device has excellent transmittance and aperture ratio characteristics, but has a disadvantage of poor viewing angle characteristics. The horizontal field type liquid crystal display device has excellent viewing angle characteristics as a common electrode and a pixel electrode are formed on the same substrate. It has advantages and is widely used.

FIG. 1 is a schematic cross-sectional view of a liquid crystal panel included in a horizontal electric field type liquid crystal display device, and FIGS. 2A and 2B are cross-sectional views illustrating a liquid crystal arrangement state of the liquid crystal panel of FIG. 3 is a diagram illustrating a screen of a liquid crystal display device in which light leakage occurs.

As shown in FIG. 1, the liquid crystal display device 1 includes a first substrate 20, which is an array substrate, a second substrate 80, which is a color filter substrate spaced apart from each other, and these substrates 20, 80. And a liquid crystal panel including the liquid crystal layer 90 interposed therebetween.

The common electrode 73 and the pixel electrode 70 having a bar shape are alternately formed on the same plane on the first substrate 20, and the liquid crystal molecules of the liquid crystal layer 90 It is operated by the horizontal electric field L by the common electrode 73 and the pixel electrode 70.

In the off state where no voltage is applied, since the horizontal electric field is not formed between the common electrode 73 and the pixel electrode 70 as shown in FIG. 2A, the arrangement state of the liquid crystal molecules 91a and 91b does not change. Do not. In this case, the arrangement direction of the liquid crystal molecules 91a and 91b may vary according to the alignment layer rubbing direction or the optical alignment direction. For example, the liquid crystal molecules 91a and 91b are the same as the electrode direction.

Next, in a voltage-on state, as shown in FIG. 2B, there is no phase change of the liquid crystal molecules 91a at positions corresponding to the common electrode 73 and the pixel electrode 70, but the common electrode ( The liquid crystal molecules 91b positioned in the section between the 73 and the pixel electrode 70 are formed by the horizontal electric field L formed by applying a voltage between the common electrode 73 and the pixel electrode 70. It will be arranged in the same direction as L). That is, in the liquid crystal panel, since the liquid crystal molecules 91b operate by the horizontal electric field, the viewing angle is widened.

As a result, when the liquid crystal display device 1 is viewed from the front, the liquid crystal display device 1 may be visible without reversal in the vertical, horizontal, and right directions of about 80 to 89 degrees.

On the other hand, the liquid crystal display device has a backlight unit for supplying light to the liquid crystal panel to the back of the liquid crystal panel, the arrangement of some liquid crystal molecules in the liquid crystal panel during the module process or after the module process between the liquid crystal panel and the backlight unit There is a problem that the light leakage phenomenon occurs.

In detail, the arrangement of the liquid crystal molecules at the edges of the liquid crystal panel may be distorted when pressure is applied to the edge region of the liquid crystal panel by the assembly during the module process, or the liquid crystal display manufactured by the module process may be applied to the external environment. Under the influence, the edge region of the liquid crystal panel is bent and the arrangement of liquid crystal molecules at the edge is distorted.

As such, when voltage is applied while the array of edge liquid crystal molecules, which is the non-display area, is misaligned, some light may leak to the display area through the misaligned liquid crystal molecules.

As a result, as shown in FIG. 3, light leakage is generated from the edge of the liquid crystal panel so that the boundary between the display area DA and the non-display area NDA bordering the display area DA is partially uneven. There is a problem.

Accordingly, an object of the present invention for solving the above problems is to provide a liquid crystal display device that prevents light leakage by controlling the arrangement of the liquid crystal molecules of the non-display area bordering the display area of the liquid crystal panel.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a first substrate having a display area including a plurality of subpixels and a non-display area including a plurality of dummy pixels; Gate wiring and data wiring crossing each other on the first substrate and defining a plurality of subpixels and a plurality of dummy pixels; A thin film transistor formed at an intersection point of the gate line and the data line; A protective film covering the thin film transistor; A pixel electrode and a common electrode formed on the passivation layer of each subpixel and formed in a plurality of bar shapes that alternate with each other to form a horizontal electric field; A signal electrode formed on the passivation layer of each dummy pixel; A second substrate facing and facing the first substrate; A first light blocking pattern formed in a lattice shape on the second substrate so as to cover the gate wiring, the data wiring and the thin film transistor of each subpixel corresponding to the first substrate; A second light blocking pattern having an opening between the first light blocking pattern and covering the non-display area including a plurality of dummy pixels and forming a vertical electric field with the signal electrode; It includes a liquid crystal layer interposed between the first substrate and the second substrate.

The first and second light blocking patterns may be formed of different materials through different mask processes.

The first and second light blocking patterns may be formed of the same material through the same mask process.

The second light blocking pattern has a dielectric constant of 10 to 30 and is formed of a material having a low resistance of 10 ⁴ kPa or less.

The second light shielding pattern may be formed of an opaque material selected from a resin, a metal, and a metal oxide-based group.

The second light blocking pattern may be supplied with a driving voltage corresponding to twice the common voltage Vcom.

The signal electrodes may be formed at positions corresponding to the plurality of bar-shaped pixel electrodes and the common electrodes, respectively, and may have the same number as the sum of the pixel electrodes and the common electrodes.

The signal electrode is formed to have a wider width than the common electrode and is formed in the same number as the number of the common electrodes.

The opening may include a first opening that cuts off a connection between the first light blocking pattern and the second light blocking pattern formed to cover the gate wiring, the first light blocking pattern and the first blocking pattern formed to cover the data wiring and the thin film transistor. And a second opening that blocks a connection between the secondary light blocking patterns, wherein the first and second openings are positioned in the non-display area.

A color filter layer in which red, green, and blue color filters are disposed in order to sequentially repeat the sub-pixels on the first light blocking pattern, a first overcoat layer for planarization on the color filter layer, and the second light blocking A second overcoat layer is further included on the pattern to compensate for the step difference with the display area.

As described above, according to the liquid crystal display device according to the present invention, a signal electrode is formed at the edge of the first substrate, and a vertical electric field is generated between the electrodes using the second light shielding pattern formed at the edge of the second substrate. This makes it possible to control the arrangement of the liquid crystal molecules arranged at the edge of the liquid crystal display device.

Accordingly, the display area has excellent viewing angle characteristics by using a liquid crystal driving method using a horizontal electric field, and the light leakage phenomenon can be prevented by vertically aligning the arrangement of liquid crystal molecules through a vertical electric field in the non-display area.

As such, by using the second light blocking pattern as the electrode, there is no need to separately form the electrode, thereby simplifying the manufacturing process and reducing the process cost.

1 is a schematic cross-sectional view of a liquid crystal panel included in a horizontal electric field type liquid crystal display device;
2A and 2B are cross-sectional views showing an arrangement of liquid crystals in the off and on states of the liquid crystal panel of FIG.
3 is a view illustrating a liquid crystal display screen on which light leakage occurs.
4 is a plan view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
5 is a plan view illustrating a structure of a subpixel in a liquid crystal display according to an exemplary embodiment of the present invention.
6 is a cross-sectional view of a liquid crystal display according to a preferred embodiment of the present invention.
7A is a cross-sectional view illustrating a liquid crystal array state in an off state in a general liquid crystal display device.
FIG. 7B is a cross-sectional view illustrating a liquid crystal array in which a data voltage of a display area is off and a signal electrode and a light shielding pattern signal of a dummy pixel area are on in a liquid crystal display according to a preferred embodiment of the present invention. FIG.
FIG. 7C is a cross-sectional view illustrating a liquid crystal arrangement in which a data voltage of a display area is on and a signal electrode of a dummy pixel area and a signal of a light shielding pattern are on in a liquid crystal display according to an exemplary embodiment of the present invention. FIG.
8 is a plan view showing a structure of a light shielding pattern according to a preferred embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

4 is a plan view schematically showing a liquid crystal display according to a preferred embodiment of the present invention, FIG. 5 is a plan view showing one pixel structure in a liquid crystal display according to a preferred embodiment of the present invention, and FIG. A cross-sectional view of a liquid crystal display according to a preferred embodiment of the invention.

First, as shown in FIG. 4, the liquid crystal display device 100 includes a plurality of subpixels SP arranged in a matrix, and the display area DA displaying an image and the display area DA bordering the display area DA. And may be divided into a non-display area NDA that shields light.

The non-display area NDA includes a dummy pixel area DPA in which a plurality of dummy pixels DP are disposed at a boundary with the display area DA.

The plurality of sub-pixels SP correspond to actual pixels for realizing an image on a screen of the liquid crystal display 100, and the plurality of dummy pixels DP correspond to extra pixels. NDA).

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to one subpixel SP of the plurality of subpixels SP of the display area DA with reference to FIGS. 5 and 6.

As shown in FIG. 5 and FIG. 6, the liquid crystal display device 100 according to the present invention faces the first substrate 102 at the lower side thereof and faces the second substrate 180 at the upper side of the liquid crystal display device at a predetermined interval. And a liquid crystal layer 190 interposed between these two substrates 102 and 180.

The outermost portion between the first substrate 102 and the second substrate 180 to prevent leakage of the liquid crystal layer 190 interposed in the spaced space between the first substrate 102 and the second substrate 180. As the seal pattern (not shown) printed along the edge is included, the first substrate 102 and the second substrate 180 are joined to form a liquid crystal panel.

Here, the first substrate 102, commonly referred to as a lower substrate or an array substrate, defines a non-display area DPA including a display area DA for displaying an image and a dummy pixel area DPA. The display area DA and the non-display area DPA are also defined in the second substrate 180 facing the 102 and called the upper substrate or the color filter substrate.

The display area DA of the first substrate 102 includes a TFT array layer formed on the transparent first insulating substrate 102a.

In detail, the gate wiring 103 extending in the first direction and the data wiring 130 extending in the second direction crossing the first direction are formed, and the gate wiring 103 and the data wiring 130 are formed. Intersect each other and define a plurality of subpixels SP.

Here, the gate line 103 is connected to a gate electrode (not shown).

The common wiring 109 is formed in parallel with the gate wiring 103, and the common auxiliary wiring 110 is formed at the outermost portion of each subpixel SP by branching from the common wiring 109. The common auxiliary line 110 is formed side by side at predetermined intervals along both edges in the second direction of each sub-pixel SP. As a result, the common auxiliary line 110 is formed side by side in a state in which the common auxiliary line 110 is spaced apart at predetermined intervals on both sides of the adjacent sub pixels around the data line 130 forming the boundary of each sub pixel.

The gate wiring 103, the common wiring 109, the common auxiliary wiring 110, and the gate electrode (not shown) may be formed of a relatively low resistivity metal material, for example, aluminum (Al), aluminum alloy (AlNd), or copper ( Cu), copper alloy, molybdenum (Mo), molybdenum (MoTi) any one or two or more of the material may be made of a single layer or a multi-layer structure.

In addition, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is disposed on the gate wiring 103, the common wiring 109, the common auxiliary wiring 110, and the gate electrode (not shown). A gate insulating film 115 is formed on the entire surface.

In addition, in the switching region TrA on the gate insulating layer 115, a semiconductor layer (not shown) including an active layer (not shown) made of pure amorphous silicon and an ohmic contact layer (not shown) made of impurity amorphous silicon in a form spaced apart from each other. O) is formed.

The source and drain electrodes 133 and 136 are formed on the semiconductor layer (not shown) and more precisely on the ohmic contact layer (not shown) spaced apart from each other and exposing the active layer (not shown).

In this case, the source electrode 133 may be formed in a bar type on the gate electrode 105, or may be formed to have a “U” shape with a recess in the gate electrode 105. 136 may be formed to form a channel structure of the "U" shape by forming a shape embedded in the recessed portion of the source electrode 133, the source and drain electrodes 133, 136 is not limited to this modified in various forms Can be.

In addition, the storage electrode extending from the drain electrode 136 to the portion where the common wiring 109 is formed may form a storage capacitor StgC together with the common wiring 109.

The semiconductor layers (not shown) formed of the gate electrodes (not shown), the gate insulating layer 115, and the ohmic contact layers (not shown) spaced apart from each other are sequentially spaced apart from each other. The source and drain electrodes 133 and 136 form a thin film transistor Tr, which is a switching element, and a region in which the thin film transistor Tr is formed is called a switching region.

A data line 130 is formed on the gate insulating layer 115 to cross the gate line 103 to define the subpixel SP. In this case, the data line 130 and the source electrode 133 are connected to each other.

Next, the first protective layer 140 made of an organic insulating material, for example, photoacrylic or benzocyclobutene and having a flat surface on the front surface of the data line 130 and the source and drain electrodes 133 and 136. Is formed.

In this case, a second protective layer (not shown) made of an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) may be further formed below the first protective layer 140.

The first passivation layer 140 includes a drain contact hole 147 exposing the drain electrode 136 in the switching area in each subpixel SP, and together with the first passivation layer 140, The gate insulating layer 115 disposed below the common insulating hole 149 exposing the common auxiliary line 110 is provided.

In addition, one of molybdenum (Mo), molybdenum (MoTi), and titanium (Ti) is formed on the first passivation layer 140 in each of the subpixels SP, and the drain electrode is formed through the drain contact hole 147. A plurality of pixel electrodes 170 having a bar shape in contact with 136 are formed at regular intervals. One end of the pixel electrode 170 is all connected by the pixel auxiliary pattern 169.

In addition, a plurality of bar-shaped pixel electrodes 170 formed on the first passivation layer 140 may be formed on the same layer and alternate with the plurality of bar-shaped pixel electrodes 170. The plurality of common electrodes 170 having a bar shape are formed in contact with the common auxiliary line 110 through the common contact hole 179. In this case, ends of the plurality of common electrodes 170 are connected by the common auxiliary pattern 172.

Meanwhile, the plurality of common electrodes 170 may be divided into an outermost common electrode 173a positioned at the outermost portion of each subpixel SP and an inner common electrode 173b formed inside the outermost common electrode 173a. The outermost common electrode 173a may be formed to overlap the common auxiliary line 110 and the data line 130.

In the drawing, the data line 130, the common electrodes 173a and 173b, and the pixel electrode 170 are symmetrically bent with respect to the center of each subpixel SP. By implementing a dual domain in one subpixel SP, color shift due to azimuth change can be suppressed. In this case, the shape of the data line 130, the common electrodes 173a and 173b, and the pixel electrode 170 may be variously changed without being limited to the shape of each of the subpixels SP.

The second substrate 180, which is located on the upper side corresponding to the first substrate 102 having the above-described configuration and is called an upper substrate or a color filter substrate, has a gate wiring 103 formed on the transparent second insulating substrate 180a. A lattice-shaped first light blocking pattern 181a bordering each subpixel SP to cover non-display elements such as the common auxiliary line 110, the data line 130, and the thin film transistor Tr; The color filter layer 183 in which the red, green, and blue color filter patterns 183a, 183b (not shown) are arranged in a repeating manner in correspondence to each subpixel SP in the grid-shaped first light blocking pattern 181a. ) Is formed.

In this case, a boundary between the red, green, and blue color filter patterns 183a, 183b (not shown) may be formed on the gate line 103 and the data line 130 forming the boundary of the subpixel SP of the first substrate 102. Preferably, the color filter layer 183 is formed to be positioned.

Although not shown in the drawings, an overcoat layer for planarization may be formed on the entire surface of the second insulating substrate 180a under the color filter layer 183. The overcoat layer is made of a transparent organic insulating material, for example, benzocyclobutene or photoacryl, and may be formed to a thickness of about 2 μm to 4 μm.

On the other hand, the liquid crystal layer 190 between the first substrate 102 and the second substrate 180 described above serves to maintain the separation gap therebetween and is formed with a first spacer (not shown) formed at a first height. A plurality of second spacers (not shown) formed between the first spacers (not shown) may be provided and have a second height lower than the first height and serve to restore the pressed surface when the screen is pressed. It may be provided over. In this case, the second spacer (not shown) is preferably formed on the second substrate 180, but is not limited thereto and may be formed on the first substrate 102.

In addition, first and second polarizing plates (not shown) for selectively transmitting only light in a specific direction may be provided on the outer surfaces of each of the first substrate 102 and the second substrate 180. ) May be provided with a back-light unit (not shown) including a light source for supplying light to the liquid crystal panel.

Hereinafter, the structure of the dummy pixel area DPA in the liquid crystal display will be described with reference to FIG. 6. In this case, since the structures of the subpixel SP of the display area DA and the dummy pixel DP included in the dummy pixel area DPA are similar to each other, detailed description of the same configuration will be omitted. The structure of the dummy pixel area DPA having a difference from the display area DA will be described in detail.

As shown in FIG. 6, the dummy pixel area DPA of the first substrate 102 may include the gate wiring 103 extending in the first direction on the first insulating substrate 102a similarly to the display area DA. And a data line 130 extending in a second direction crossing the first direction so that the gate line 103 and the data line 130 cross each other to define a plurality of dummy pixels DP, and each dummy pixel. Each of the DPs includes a TFT array layer in which a thin film transistor (TFT) (Tr) is formed.

Here, the thin film transistor Tr, like the subpixel of FIG. 5, sequentially includes a gate electrode, a gate insulating layer 115, a semiconductor layer composed of an ohmic contact layer spaced apart from the active layer, and source and drain electrodes spaced apart from each other. It is laminated.

Meanwhile, the first protective layer 140 made of an organic insulating material, for example, photoacrylic or benzocyclobutene and having a flat surface on the front surface of the data line 130 and the source and drain electrodes 133 and 136 is formed. And a plurality of bar-shaped signal electrodes 175 formed on the first protective layer 140.

The plurality of signal electrodes 175 are formed on the first passivation layer 140, which is the same layer and made of the same material as the common electrodes 173a and 173b of the display area DA.

Here, the plurality of signal electrodes 175 may be formed in various forms. For example, the plurality of signal electrodes 175 formed in one dummy pixel DP may include the pixel electrodes 170 formed in one sub pixel SP. ) And the common electrode 173 may correspond to each of the pixel electrode 170 and the common electrode 173 formed in one subpixel SP.

In another example, each of the plurality of signal electrodes 175 is formed to be wider than the width of the common electrode 173 formed in the subpixel SP, so that the same number of common electrodes 173 formed in one subpixel SP may be formed. Can be.

As another example, the signal electrode 175 may be formed over the first protective layer 140 over the dummy pixel area DPA.

The plurality of signal electrodes 175 may contact the common auxiliary line 110 through the common contact hole 179, and the ends of the plurality of signal electrodes 175 may be connected by the common auxiliary pattern 172.

In the dummy pixel area DPA of the second substrate 180 corresponding to the dummy pixel area DPA of the first substrate 102 on which the signal electrode 175 is formed, a plurality of dummy pixels DP are disposed. An opaque second light blocking pattern 181b is provided.

The second light blocking pattern 181b corresponds to an edge light shielding pattern formed to shield the non-display area NDA including the dummy pixel area DPA in the liquid crystal display 100.

That is, in the display area DA of the second substrate 180, the gate wiring 103, the common auxiliary wiring 110, the data wiring 130, and the thin film transistor Tr of the first substrate 102 corresponding thereto. The first light blocking pattern 181a is formed around the subpixel SP to cover the non-display elements such as the second display element, while the second pixel 180 is entirely formed in the dummy pixel area DPA of the second substrate 180. A light blocking pattern 181b is formed to cover the non-display area NDA.

Each of the first light blocking pattern 181a and the second light blocking pattern 181b is formed of an opaque color to absorb external light reflections to block light. And the non-display area NDA, the first light blocking pattern 181a and the second light blocking pattern 181b are not connected to each other.

This is because the second light blocking pattern 181b serves as an electrode to form a vertical electric field together with the signal electrode 175 of the first substrate 102.

The second light shielding pattern 181b has a dielectric constant of 10 to 30 and has a relatively low resistivity of 10 ⁴ kW or less, for example, formed of one of a resin or a metal and a metal oxide-based inorganic pigment to serve as a conductor. do.

In addition, the second light blocking pattern 181b may be connected to a voltage applying terminal to receive a driving voltage from an external source. The driving voltage may vary depending on the common voltage Vcom of the display area or the driving voltage of the driving unit. Preferably, the driving voltage corresponding to twice the common voltage Vcom may be supplied.

In this case, the first light blocking pattern 181a provided in the display area DA and the second light blocking pattern 181b provided in the non-display area NDA may be formed through different mask processes or may use the same mask process. It can be formed through.

For example, when the first light blocking pattern 181a and the second light blocking pattern 181b are formed of different materials through different mask processes, the first light blocking pattern 181a may have a resistance of the second light blocking pattern 181b. It is possible to prevent the horizontal electric field between the common electrode 173 and the pixel electrode 170 of the display area DA from being formed to have a resistance value of at least 10 ⁵ kΩ or more higher than the value.

As another example, when the first light blocking pattern 181a and the second light blocking pattern 181b are formed of the same material through the same mask process, the first light blocking pattern 181a and the second light blocking pattern 181b may be It may be formed of a material having a dielectric constant of 10 to 30 and a relatively low resistivity of 10 ⁴ kPa or less. In this case, since the first light blocking pattern 181a and the second light blocking pattern 181b may be formed together through one mask process, the number of processes may be shortened to simplify the process.

As described above, in the display area DA, the liquid crystal molecules are driven by a horizontal electric field generated between the common electrode 173 and the pixel electrode 170 of the first substrate 102 to realize an image, and the non-display area. In the dummy pixel area DPA (NDA), liquid crystal characters are driven by a vertical electric field generated by the signal electrode 175 of the first substrate 102 and the second light blocking pattern 181b of the second substrate 180. As a result of vertical alignment, light leakage caused by an external environment can be prevented.

This will be described in more detail with reference to the drawings.

FIG. 7A is a cross-sectional view illustrating a liquid crystal array in an off state in a general liquid crystal display, and FIG. 7B is a signal electrode of a dummy pixel region in which a data voltage of a display area is off in a liquid crystal display according to an exemplary embodiment of the present invention. And FIG. 7C is a cross-sectional view illustrating a liquid crystal array in a state in which a signal of a light blocking pattern is turned on, and FIG. 7C is a diagram illustrating a data voltage of a display area in a liquid crystal display according to a preferred embodiment of the present invention, and light blocking of a signal electrode in a dummy pixel area. It is sectional drawing which shows the liquid crystal arrangement state of the state in which the signal of the pattern was on. Here, the data voltage corresponds to a driving voltage applied to implement an image in the liquid crystal display.

As shown in FIG. 7A, when the data voltage is off, a horizontal electric field is formed between the common electrode 173 and the pixel electrode 170 formed on the first substrate 102 in the display area DA. Therefore, the arrangement state of the liquid crystal molecules 191a does not change, and similarly, in the dummy pixel area DPA, the second light blocking pattern formed on the signal electrode 175 formed on the first substrate 102 and on the second substrate 180. Since no vertical electric field is formed between the 181b regions, the arrangement state of the liquid crystal molecules 191a does not change. However, if the arrangement state of some of the liquid crystal molecules 191a at the edge is changed by the external magnetic pole, the screen of the liquid crystal display device is affected even in the off state where no voltage is applied.

However, in the liquid crystal display according to the present invention, even when the data voltage is not applied, as shown in FIG. 7B, the driving voltage is applied to the second light blocking pattern 181b and the signal electrode 175 formed on the first substrate 102. Is applied.

Accordingly, since no data voltage is applied, no horizontal electric field is formed between the common electrode 173 and the pixel electrode 170 formed on the first substrate 102 in the display area DA, so that the liquid crystal molecules 191a are arranged. However, since the driving voltage is applied to the dummy pixel area DPA, a vertical electric field is formed between the signal electrode 175 formed on the first substrate 102 and the second light blocking pattern 181b formed on the second substrate 180. Since the liquid crystal molecules 191c are vertically arranged therebetween, light is blocked to prevent light leakage that occurs at the boundary between the display area DA and the non-display area NDA.

Meanwhile, when the liquid crystal display according to the present invention is in an image-on state, as shown in FIG. 7C, the liquid crystal display according to the present invention may be connected to the signal electrode 175 formed on the second light blocking pattern 181b and the first substrate 102. The driving voltage is applied and the data voltage is also applied. Accordingly, as the data voltage is applied in the display area DA, a horizontal electric field is formed between the common electrode 173 and the pixel electrode 170 formed on the first substrate 102 so that the liquid crystal molecules 191b therebetween are horizontal. The image is realized by being arranged, and as the driving voltage is applied in the dummy pixel area DPA, between the signal electrode 175 formed on the first substrate 102 and the second light blocking pattern 181b formed on the second substrate 180. Since a vertical electric field is formed and the liquid crystal molecules 191c are vertically arranged therebetween, light is blocked to prevent light leakage occurring at the boundary between the display area DA and the non-display area NDA.

That is, even when the arrangement state of the liquid crystal molecules, especially the edge liquid crystal molecules, is changed by the external magnetic pole, the driving voltage is always applied to the dummy pixel region DPA, and thus, the first substrate 102 of the dummy pixel region DPA. The vertical electric field is always formed between the signal electrode 175 formed on the second electrode 180 and the second light blocking pattern 181b formed on the second substrate 180 so that the arrangement of the liquid crystal molecules 191c may form a vertical state therebetween. Therefore, it is possible to prevent the light leakage phenomenon generated as the conventional liquid crystal molecules are turned.

Although not shown, an overcoat layer may be further provided on the second light blocking pattern 181b to compensate for the step difference with the display area DA. The overcoat layer is formed of a low resistance organic insulating material to form a second light blocking pattern. The vertical electric field may be better formed between the 181b and the signal electrode 175.

FIG. 8 is a plan view illustrating a structure of a light shielding pattern according to an exemplary embodiment of the present invention, see FIGS. 4 to 6.

As shown in FIG. 8, the connection between the first light blocking pattern 181a and the second light blocking pattern 181b is blocked through the first and second openings 182a and 182b. Here, the first light shielding pattern 181a is provided on the second substrate 180 (180 of FIGS. 5 and 6), the gate wiring 103 (103), the common auxiliary wiring (110 of FIG. 6), and the data wiring (FIG. 6). 130) and a pattern that borders each of the subpixels SP of the first substrate (102 of FIGS. 5 and 6) so as to cover non-display elements such as a thin film transistor (Tr of FIG. 5). 181b is a pattern provided on the second substrate (180 of FIGS. 5 and 6) to cover the non-display area NDA including the dummy pixel area DPA.

In this case, a first blocking pattern 181a is formed to cover the gate wiring 103 in the first direction and a second blocking pattern 181b bordering the non-display area NDA including the dummy pixel area DPA is formed. A first opening 182a for blocking a connection between the primary light blocking pattern 181a and the second light blocking pattern 181b is included.

Also, a non-display area including the first light blocking pattern 181a and the dummy pixel area DPA formed to cover the common auxiliary line (11 of FIG. 6), the data line 130, and the thin film transistor Tr in the second direction. A second opening 182b for blocking a connection between the first light blocking pattern 181a and the second light blocking pattern 181b is included between the second light blocking pattern 181b bordering the NDA.

The first and second openings 182a and 182b are provided on the non-display area NDA, respectively, so that the connection between the first and second light blocking patterns 181a and 181b is blocked. 182a and 182b may be provided to prevent light leakage that may occur.

The embodiments of the present invention as described above are merely exemplary, and those skilled in the art may freely modify the present invention without departing from the gist of the present invention. Therefore, the protection scope of the present invention shall include modifications of the present invention within the scope of the appended claims and equivalents thereof.

103: gate wiring 109: common wiring
110: common auxiliary wiring 130: data wiring
170: pixel electrode 173: common electrode
175: signal electrode 189a: first light blocking pattern
189b: second light blocking pattern

Claims (10)

A first substrate having a display area including a plurality of subpixels and a non-display area including a plurality of dummy pixels;
Gate wiring and data wiring crossing each other on the first substrate and defining a plurality of subpixels and a plurality of dummy pixels;
A thin film transistor formed at an intersection point of the gate line and the data line;
A protective film covering the thin film transistor;
A pixel electrode and a common electrode formed on the passivation layer of each subpixel and formed in a plurality of bar shapes that alternate with each other to form a horizontal electric field;
A signal electrode formed on the passivation layer of each dummy pixel;
A second substrate facing and facing the first substrate;
A first light blocking pattern formed in a lattice shape on the second substrate so as to cover the gate wiring, the data wiring and the thin film transistor of each subpixel corresponding to the first substrate;
A second light blocking pattern having an opening between the first light blocking pattern and covering the non-display area including a plurality of dummy pixels and forming a vertical electric field with the signal electrode;
Liquid crystal layer interposed between the first substrate and the second substrate
Liquid crystal display comprising a.
The method of claim 1,
The first and second light blocking patterns
Liquid crystal display device made of different materials through different mask processes.
The method of claim 1,
The first and second light blocking patterns
A liquid crystal display device made of the same material through the same mask process.
The method according to any one of claims 1 to 3,
The second light blocking pattern is
A liquid crystal display device having a dielectric constant of 10 to 30 and having a low resistance of 10 ⁴ kPa or less.
5. The method of claim 4,
The second light blocking pattern is
Liquid crystal display device formed of an opaque material selected from the group consisting of resin, metal and metal oxide.
The method of claim 1,
The second light blocking pattern is
Liquid crystal display device receiving a driving voltage corresponding to twice the common voltage (Vcom).
The method of claim 1,
The signal electrode is
And a plurality of bar electrodes formed at positions corresponding to each of the plurality of bar-shaped pixel electrodes and the common electrode.
The method of claim 1,
The signal electrode is
And a width greater than that of the common electrode, and the same number as the number of the common electrodes.
The method of claim 1,
The opening
A first opening configured to block a connection between the first light blocking pattern and the second light blocking pattern formed to cover the gate wiring;
And a second opening that cuts off the connection between the first light blocking pattern and the second light blocking pattern formed to cover the data line and the thin film transistor.
The first and second openings
And a liquid crystal display device positioned in the non-display area.
The method of claim 1,
A color filter layer on which the red, green, and blue color filters are disposed in order to sequentially repeat the sub-pixels on the first light blocking pattern;
A first overcoat layer for planarization over the color filter layer;
And a second overcoat layer over the second light blocking pattern to compensate for a step with the display area.

Images