KR20130055329A - Oxide thin film transistor and method for manufacturing the same - Google Patents

Abstract

PURPOSE: An oxide thin film transistor and a method for manufacturing the same are provided to minimize parasitic capacitance by removing the overlapping region of a gate with a source/drain electrode. CONSTITUTION: A reactive metal layer(110) is formed on both ends of an active layer. A source/drain electrode(114a,114b) is formed on the reactive metal layer. A gate electrode is overlapped with an interlayer dielectric pattern(108). A protection layer includes a contact hole for exposing a part of the drain electrode. A pixel electrode(118a) is formed on the protection layer.

Description

Oxide thin film transistor and method for manufacturing the same

The present invention relates to an oxide thin film transistor and a method for manufacturing the same, and more particularly, to an oxide thin film transistor and a method for manufacturing the oxide thin film transistor which can minimize the parasitic capacitance by removing the overlapping region of the gate, source electrode and drain electrode.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Recently, liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting diodes Various flat display devices such as organic light emitting diodes (OLEDs) are being utilized.

Among these flat panel display devices, the organic light emitting device is a device that emits light by dissipating electrons and holes after pairing when an electric charge is injected into the organic light emitting layer formed between the electron injection electrode (cathode) and the hole injection electrode (anode). Research is being actively conducted due to the advantage of being able to drive at a lower voltage (for example, 10V or less) than a plasma display panel or an inorganic light emitting device.

FIG. 1 schematically shows the structure of an organic light emitting diode. As shown in the drawing, the anode 1 and the cathode 3 of the organic light emitting diode 5 are formed on a transparent substrate such as glass. It is disposed to face each other under an interposition, and light is emitted from the organic light emitting layer 5 by a voltage applied between the anode electrode 1 and the cathode electrode 3. In this case, the anode electrode 1 is formed of a thin film of ITO (indium-tinoxide), which is a transparent conductive material so that the holes and the light emitted from the organic light emitting layer can be transmitted well, and the anode electrode can supply electrons smoothly. So that the work function is formed of a low metal.

Therefore, when positive and negative voltages are applied to the anode electrode 1 and the cathode electrode 3, the holes injected from the anode electrode 1 and the electrons injected from the cathode electrode 3 are in the organic light emitting layer. Recombine at and light is emitted. At this time, the emission color is changed according to the material forming the organic light emitting layer (5). That is, the light emitting colors of R (red), G (green), and B (blue) are changed by the organic light emitting layer 5.

On the other hand, in the organic light emitting display device, the unit pixels are arranged in a matrix form, and the organic light emitting display device selectively displays the image by driving the organic light emitting diode of the unit pixel through the driving device and the switching device provided in each unit pixel. The device and the switching device consist of a thin film transistor.

2 is a cross-sectional view schematically illustrating a structure of a conventional oxide thin film transistor.

As shown in FIG. 2, a buffer layer (not shown) is formed on the insulating substrate 10, a gate electrode 12 is formed on the buffer layer, and a gate insulating layer 14 is formed on the gate electrode 12. have.

An active layer 15 is formed on the gate insulating layer 14, an etch stopper layer 18 is formed on the active layer 15, and a source electrode 22 overlapping the gate electrode 12 on the etch stopper layer 18. ) And the drain electrode 24 are formed. The active layer 15 may be formed of, for example, IGZO, which is a compound in which a zinc oxide compound is doped with indium and gallium.

A passivation layer 26 is formed on the source electrode 22 and the drain electrode 24, and a contact hole 28 exposing a portion of the drain electrode 24 is formed in the passivation layer 26, and a contact is formed on the passivation layer 26. The hole 28 forms a pixel electrode 32 electrically connected to the drain electrode 24.

As described above, the oxide thin film transistor having the gate electrode 12 formed under the insulating substrate 10 has a structure in which a part of the gate electrode 12 overlaps the source electrode 22 and the drain electrode 24 formed thereon. Has That is, the first region a1 in which a portion of the gate electrode 12 and a portion of the source electrode 22 overlap and the second region a2 in which a portion of the gate electrode 12 and a portion of the drain electrode 24 overlap each other. Has

In this case, the parasitic capacitance Cgs increases due to the first and second regions a1 and a2. As a result, performance of a high resolution high speed driving liquid crystal display device having a large area is reduced.

The present invention is to solve the above problems, to provide an oxide thin film transistor and a method of manufacturing the same that can minimize the parasitic capacitance by removing the region overlapping the gate, source electrode and drain electrode.

Other objects and features of the present invention will be described in the following description of the invention and claims.

In order to achieve the above objects, an oxide thin film transistor according to an embodiment of the present invention is a gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, an active layer formed on the gate insulating film, both sides inside the active layer First and second regions formed on the conductive layer, a reactive metal layer formed on both ends of the active layer, a source electrode and a drain electrode formed on the reactive metal layer, and formed on the active layer and overlap the gate electrode. A passivation layer formed on the entire surface of the substrate including the formed interlayer insulating layer pattern, the interlayer insulating layer pattern, and including a contact hole exposing a predetermined region of the drain electrode and a drain formed on the passivation layer. And a pixel electrode electrically connected to the electrode.

The reactive metal layer is a material for reducing the active layer, and the reactive metal layer is a reducing agent.

The first and second regions are formed through a reduction reaction of the active layer and the reactive metal layer by performing a heat treatment process on the substrate.

The width of the active layer is greater than the width of the gate electrode.

The active layer is formed of any one selected from the group consisting of ZnO, Ga ₂ O ₃ , In ₂ O ₃ , and Sn0 ₂ .

The reactive metal layer is formed of any one selected from the group consisting of Al, Ti, and MoTi.

In addition, the method of manufacturing an oxide thin film transistor according to an embodiment of the present invention comprises the steps of forming a gate electrode on an insulating substrate, forming a gate insulating film on the gate electrode, forming an active layer on the gate insulating film, Forming an interlayer insulating layer pattern on the active layer, sequentially forming a reactive metal layer, a source electrode, and a drain electrode material on the entire surface of the substrate including the interlayer insulating layer pattern; and forming a first conductive layer on both sides of the active layer. And forming a second region, sequentially etching the source electrode and drain electrode material and the reactive metal layer to form a source electrode and a drain electrode so as to overlap both ends of the active layer, the source electrode and the drain electrode A region of the drain electrode on the front surface of the substrate including a And forming a pixel electrode connected to the exposed by the contact hole in the step of forming a protective film comprising a contact hole exposing the protective film and the drain electrode.

 The reactive metal layer is a material for reducing the active layer, and the reactive metal layer is a reducing agent.

The forming of the first and second regions may be performed by performing a heat treatment process on the substrate to form the first and second regions through a reduction reaction between the active layer and the reactive metal layer.

The width of the active layer is greater than the width of the gate electrode.

The active layer is formed of any one selected from the group consisting of ZnO, Ga ₂ O ₃ , In ₂ O ₃ , and Sn0 ₂ .

The reactive metal layer is formed of any one selected from the group consisting of Al, Ti, and MoTi.

The reactive metal layer is removed by dry etch, and the source electrode and drain electrode material is removed by wet etch.

Between the source electrode and drain electrode material is sequentially formed and the interlayer insulating layer pattern is formed, the source electrode and the drain electrode material are etched to overlap the both ends of the active layer. Forming an electrode, performing a heat treatment process on the substrate to form conductive first and second regions on both sides of the active layer, and remaining reactive except for the reactive metal layer under the source and drain electrodes Etching away the metal layer.

As described above, the oxide thin film transistor and the method of manufacturing the same according to the present invention provide an effect of minimizing parasitic capacitance by removing an overlapping region of the gate, the source electrode, and the drain electrode.

In addition, the oxide thin film transistor and the method for manufacturing the same according to the present invention can solve the problems such as afterimage induction and inability to drive the liquid crystal panel which may occur when the liquid crystal display device is driven at high speed by removing the parasitic capacitance (Cgs) of the oxide thin film transistor. Provide the effect.

1 is a schematic configuration diagram of a general organic light emitting device.
Figure 2 is a cross-sectional view schematically showing the structure of a conventional oxide thin film transistor.
3 is a cross-sectional view showing an oxide thin film transistor according to an embodiment of the present invention.
4A to 4F are cross-sectional views sequentially illustrating a method of manufacturing an oxide thin film transistor according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of an oxide thin film transistor and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view illustrating an oxide thin film transistor according to an exemplary embodiment of the present invention.

As shown in FIG. 3, in the oxide thin film transistor according to an exemplary embodiment, a gate electrode 102a is formed on an insulating substrate 100, and a gate insulating layer 104 is formed on the gate electrode 102a. It is.

An active layer 106 is formed on the gate insulating film 104, a reactive metal layer 110 is formed on the active layer 106, and a source electrode and a drain electrode are formed on the reactive metal layer 110. .

Here, the width of the active layer 106 is larger than the width of the gate electrode 102a, and the reactive metal layer 110, the source electrode 114a, and the drain electrode 114b are formed to overlap both ends of the active layer. It is. In this case, the active layer 106 may be formed of any one selected from, for example, ZnO, Ga ₂ O ₃ , In ₂ O ₃ , and Sn0 ₂ . In addition, the reactive metal layer 110 may be formed of any one selected from the group consisting of, for example, Al, Ti, and MoTi, and may be used as long as it is a material that conductors the active layer 106.

An interlayer insulating film pattern 108 is formed on the active layer 106, and a passivation film 116 is formed on the interlayer insulating film pattern 108. In this case, the interlayer insulating film pattern 108 is formed in a pattern form to overlap the gate electrode 102a formed below, and a contact hole 116a is formed in the passivation layer 116 to expose a predetermined region of the drain electrode 114b. It is.

The pixel electrode 118a is formed on the passivation layer 116 to be electrically connected to a portion of the drain electrode 114b by the contact hole 116a.

In an embodiment of the present invention, the active layer 106 is formed wider than the gate electrode 102a, and the reactive metal layer 110, the source electrode 114a, and the drain electrode 114b are formed at both ends of the active layer 106. Formed to overlap and heat-treated the substrate 100 to form the first and second regions 115a and 115b that are conductored on both sides of the active layer 106 to form the gate electrode 102a and the source electrode 114a. ) And an area where the gate electrode 102a and the drain electrode 114b overlap with each other.

As a result, an increase in parasitic capacitance Cgs may be minimized due to an overlapping region of the gate electrode 102a and the source electrode 114a and an overlapping region of the gate electrode 102a and the drain electrode 114b.

Hereinafter, a method of manufacturing an oxide thin film transistor according to an embodiment of the present invention will be described with reference to FIGS. 4A to 4F.

4A to 4F are cross-sectional views sequentially illustrating a method of manufacturing an oxide thin film transistor according to an exemplary embodiment of the present invention.

As shown in FIG. 4A, the insulating substrate 100 includes a thin film transistor forming region a and a pad region b. First, a first metal material is deposited on the insulating substrate 100, and then selectively patterned through a photolithography process to form gate electrodes 102a and 102b.

As shown in FIG. 4B, the gate insulating layer 104 is formed on the entire surface of the substrate 100 including the gate electrodes 102a and 102b. The gate insulating layer 104 may be formed of an inorganic insulating layer such as a silicon nitride film (SiNx), a silicon oxide film (SiO 2), or a highly dielectric oxide film such as hafnium (Hf) oxide or aluminum oxide. At this time, for example, when the silicon oxide film is applied to the gate insulating film 104, it may be formed to a thickness of 300 ~ 1000 ~, dry etching may be used for the etching.

In addition, the gate insulating layer 104 may be formed by Chemical Vapor Deposition (CVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD).

Next, an active layer material is deposited on the gate insulating layer 104, and then selectively patterned through a photolithography process to form the active layer 106 wider than the gate electrode 102a.

Here, the active layer 106 is, for example, ZnO, Ga ₂ O ₃ , In ₂ O ₃ , Sn0 ₂ The same may be formed of an oxide metal in which materials are mixed. In addition, the width of the active layer 106 is formed to be larger than the width of the gate electrode 102a, so as to form the source electrode 114a and the drain electrode 114b so as to overlap both ends of the active layer 106 later. .

As shown in FIG. 4C, an interlayer insulating material is formed on the entire surface of the substrate 100 including the active layer 106, and then selectively patterned through a photolithography process so as to overlap the gate electrode 102a formed thereunder. The insulating film pattern 108 is formed.

Subsequently, the reactive metal layer 110 is formed on the entire surface of the substrate 100 including the interlayer insulating layer pattern 108. In this case, the reactive metal layer 110 may be formed of a material that conductors an oxide metal such as Al, Ti, MoTi, or the like. Here, the reactive metal layer 110 may be used as long as it is a material for reducing the active layer 106.

As shown in FIG. 4D, a source electrode and a drain electrode material are deposited on the reactive metal layer 110 and then heat treated 200 to the substrate 100 for a reduction reaction of the active layer 106 and the reactive metal layer 110. ). When the heat treatment 200 is performed in this way, the reactive metal layer 110 and the active layer 106 undergo a reduction reaction so that the first and second regions 115a and 115b conductored on both sides of the active layer 106 are formed. Is formed. Here, the reactive metal layer 110 serves as a reducing agent for accelerating the reduction reaction of the active layer 106.

Subsequently, wet etching is performed on the source electrode and the drain electrode material to form the source electrode 114a and the drain electrode 114b so as to overlap both ends of the active layer 106. Here, the data line 112 is also formed in the pad region when the source electrode 114a and the drain electrode 114b are formed.

Thereafter, dry etching is performed on the reactive metal layer 110 below using the source electrode 114a and the drain electrode 114b as an etching mask.

Here, the source electrode and the drain electrode material may use a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, nickel, chromium, molybdenum, titanium, platinum, tantalum and the like. In addition, an opaque conductive material such as indium tin oxide and indium zinc oxide may be used as the source electrode and the drain electrode material, and may be formed in a multilayer structure in which two or more conductive materials are stacked. In addition, a conductive material such as molybdenum or molybdenum alloy may be directly applied to the source and drain electrode materials, and a low resistance conductive material such as aluminum or copper may be applied after hydrogen or argon plasma treatment.

In an embodiment of the present invention, the reactive metal layer 110, the source electrode, and the drain electrode material are sequentially deposited on the active layer 106, and a heat treatment is performed on the substrate 100 to form a conductor inside the active layer 106. After forming the first and second regions 115a and 115, wet etching is performed on the source electrode and the drain electrode material to form the source electrode 114a and the drain electrode 114b, and dry on the reactive metal layer 110. The etching was described.

In addition, according to an embodiment of the present invention, the reactive metal layer 110 and the source electrode and the drain electrode material are sequentially deposited on the active layer 106, and wet etching is performed on the source electrode and the drain electrode material to perform the source electrode 114a. And forming a drain electrode 114b and then performing heat treatment on the substrate 100 to form conductive first and second regions 115a and 115 in the active layer 106 and to form the reactive metal layer 110. It is also possible to proceed with dry etching. At this time, the remaining reactive metal layer 110 except for the reactive metal layer 110 under the source electrode 114a and the drain electrode 114b is removed by etching.

As shown in FIG. 4E, the passivation layer 116 is formed on the entire surface of the substrate 100 including the source electrode 114a and the drain electrode 114b, and then selectively patterned through a photolithography process to form the passivation layer 116. A contact hole 116a exposing a predetermined region of the drain electrode 114b is formed. In this case, contact holes 116b and 116c exposing a predetermined region of the data line 112 and the gate electrode 102b formed in the pad region are also formed.

As shown in FIG. 4F, a transparent conductive material is deposited on the passivation layer 116, and then selectively patterned through a photolithography process to electrically connect the pixel electrode to the drain electrode 114b by the contact hole 116a. 118a is formed. In this case, the exposed gate electrode 102b and the data line 112 of the pad region are also electrically connected to the pixel electrodes 118b and 118c by the contact holes 116b and 116c.

Therefore, through the above process, the source electrode 112 and the drain electrode 114 are formed so as to overlap at both ends of the active layer 106, and the first and second conductors formed on both sides of the inside of the active layer 106 are formed. An oxide thin film transistor according to an embodiment of the present invention having two regions 115a and 115b is completed.

The oxide thin film transistor according to an embodiment of the present invention can be applied to a liquid crystal display (LCD) or an organic light emitting display device.

In an embodiment of the present invention, the active layer 106 is formed wider than the gate electrode 102a, and the source electrode 112 and the drain electrode 114 are formed to overlap both ends of the active layer 106, and the active By forming the conductive first and second regions 115a and 115b on both sides of the inside of the layer 106, the region where the gate electrode 102a and the source electrode 114a and the drain electrode 114b overlap can be removed. have.

Accordingly, an increase in the parasitic capacitance Cgs due to the overlapping region of the gate electrode 102a, the source electrode 114a, and the drain electrode 114b can be minimized.

In addition, in the related art, as shown in FIG. 2, since the gate electrode 12 is formed below the source electrode 22 and the drain electrode 24, a portion of the gate electrode 12 and a portion of the source electrode 22 are formed. The parasitic capacitance Cgs increases due to the overlapping first region a1, the portion of the gate electrode 12, and the portion of the drain electrode 24 overlapping the second region a2. As a result, when the LCD is driven at a high speed, the charging time is shortened during the 1H cycle, thereby causing insufficient charge to be charged in the pixel electrode connected to the oxide thin film transistor, thereby causing an afterimage of the liquid crystal panel and an inability to drive the LCD panel. There was a disadvantage.

On the other hand, in an exemplary embodiment of the present invention, a region where a portion of the gate electrode 102a and a portion of the source electrode 114a overlap and a region where a portion of the gate electrode 102a and a portion of the drain electrode 114b overlap are removed. It can be seen that the parasitic capacitance Cgs is removed.

Accordingly, in one embodiment of the present invention, the parasitic capacitance Cgs of the oxide thin film transistor is removed, thereby solving problems such as afterimage generation and inability to drive the liquid crystal panel, which may occur when the LCD is driven at high speed.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Accordingly, the invention is not to be determined by the embodiments described, but should be determined by equivalents to the claims and the appended claims.

100: insulating substrate 102a: gate electrode
104: gate insulating film 106: active layer
108: interlayer insulating film pattern 110: reactive metal layer
114a: source electrode 114b: drain electrode
115a: first region 115b: second region
116: protective film 116a, 116b, 116c: contact hole
118a, 118b, 118c: pixel electrode

Claims (17)

A gate electrode formed on the insulating substrate;
A gate insulating film formed on the gate electrode;
An active layer formed on the gate insulating layer;
First and second conductive regions formed on both sides of the inside of the active layer;
Reactive metal layers formed on both ends of the active layer;
A source electrode and a drain electrode formed on the reactive metal layer;
An interlayer insulating layer pattern formed on the active layer and overlapping the gate electrode;
A passivation layer formed on an entire surface of the substrate including the interlayer insulating layer pattern and including a contact hole exposing a predetermined region of the drain electrode; And
And a pixel electrode formed on the passivation layer and electrically connected to the exposed drain electrode by the contact hole. The method of claim 1,
The reactive metal layer is an oxide thin film transistor, characterized in that the material for reducing the active layer. The method of claim 1,
The reactive metal layer is an oxide thin film transistor, characterized in that the reducing agent. The method of claim 1,
And the first and second regions are formed through a reduction reaction between the active layer and the reactive metal layer by performing a heat treatment process on the substrate. The method of claim 1,
And the width of the active layer is greater than that of the gate electrode. The method of claim 1,
The active layer is an oxide thin film transistor, characterized in that formed of any one selected from the group consisting of ZnO, Ga ₂ O ₃ , In ₂ O ₃ , Sn0 ₂ . The method of claim 1,
The reactive metal layer is an oxide thin film transistor, characterized in that formed of any one selected from the group consisting of Al, Ti, MoTi. Forming a gate electrode on the insulating substrate;
Forming a gate insulating film on the gate electrode;
Forming an active layer on the gate insulating film;
Forming an interlayer insulating film pattern on the active layer;
Sequentially forming a reactive metal layer, a source electrode, and a drain electrode material on the entire surface of the substrate including the interlayer dielectric pattern;
Forming conductive first and second regions on both sides of the inside of the active layer;
Sequentially etching the source electrode and drain electrode material and the reactive metal layer to form a source electrode and a drain electrode to overlap both ends of the active layer;
Forming a passivation layer including a contact hole exposing a predetermined region of the drain electrode on an entire surface of the substrate including the source electrode and the drain electrode; And
And forming a pixel electrode electrically connected to the exposed drain electrode by the contact hole on the passivation layer. 9. The method of claim 8,
The reactive metal layer is a method of manufacturing an oxide thin film transistor, characterized in that the material for reducing the active layer. 9. The method of claim 8,
The reactive metal layer is a manufacturing method of the oxide thin film transistor, characterized in that the reducing agent. 9. The method of claim 8,
The forming of the first and second regions may be performed by performing a heat treatment process on the substrate to form the first and second regions through a reduction reaction between the active layer and the reactive metal layer. Manufacturing method. 9. The method of claim 8,
And the width of the active layer is greater than the width of the gate electrode. 9. The method of claim 8,
The active layer is ZnO, Ga ₂ O ₃ , In ₂ O ₃ , Sn0 _{2 The} method of manufacturing an oxide thin film transistor, characterized in that formed of any one selected from the group consisting of. 9. The method of claim 8,
The reactive metal layer is a method of manufacturing an oxide thin film transistor, characterized in that formed of any one selected from the group consisting of Al, Ti, MoTi. 9. The method of claim 8,
The reactive metal layer is a method of manufacturing an oxide thin film transistor, characterized in that removed by dry etching (dry etch). 9. The method of claim 8,
And the source electrode and the drain electrode material are removed by wet etch. 9. The method of claim 8,
Between the source electrode and drain electrode material is sequentially formed and the interlayer insulating layer pattern is formed, the source electrode and the drain electrode material are etched to overlap the both ends of the active layer. Forming an electrode;
Heat-treating the substrate to form conductive first and second regions on both sides of the active layer; And
And removing the remaining reactive metal layer by removing the reactive metal layer under the source electrode and the drain electrode.

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