KR20130046680A - Display device - Google Patents

Display device Download PDF

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Publication number
KR20130046680A
KR20130046680A KR1020110111209A KR20110111209A KR20130046680A KR 20130046680 A KR20130046680 A KR 20130046680A KR 1020110111209 A KR1020110111209 A KR 1020110111209A KR 20110111209 A KR20110111209 A KR 20110111209A KR 20130046680 A KR20130046680 A KR 20130046680A
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KR
South Korea
Prior art keywords
voltage
external memory
memory unit
data driver
data
Prior art date
Application number
KR1020110111209A
Other languages
Korean (ko)
Inventor
김태군
Original Assignee
엘지디스플레이 주식회사
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Priority to KR1020110111209A priority Critical patent/KR20130046680A/en
Publication of KR20130046680A publication Critical patent/KR20130046680A/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve

Abstract

PURPOSE: A display device is provided to prevent damage to stored data caused by external noises and unintended writing work by performing only a reading function of an external memory unit. CONSTITUTION: Data operating units(130a-130c) are operated according to the control of a timing control unit(110). The data operating units generate a gamma voltage by receiving a gamma reference voltage from a gamma reference voltage generating unit(135). A display panel displays an image by a data signal supplied from the data operating unit. An external memory unit(120) provides stored data to the timing control unit. The external memory unit includes a partial pressure circuit(125) reducing the gamma voltage to a logic-high voltage.

Description

Display device {DISPLAY DEVICE}

An embodiment of the present invention relates to a display device.

As information technology grows, the market of display devices, which are the connecting medium between users and information, grows, and thus, organic light emitting display (OLED), liquid crystal display (LCD), and plasma display devices The use of display devices such as plasma display panels (PDPs) is increasing.

As described above, the display device is utilized in various industrial fields such as a computer or a mobile phone such as a notebook in a home appliance field such as a television or a video.

The display device includes a display panel displaying an image and driving devices supplying various driving signals to the display panel. The driving devices are various, such as a data driver, a scan driver, a timing controller, and a power supply.

The timing controller performs various image processing based on data stored in the external memory in cooperation with an external memory (EEPROM). The external memory includes a write protection terminal that controls the write / write function.

In general, an external memory used in a conventional display device needs to change data at any time, so that the light protection terminal is connected to the ground line or left in a floating state. However, when the light protection terminal of the external memory is connected to the ground wiring or in the floating state as in the conventional display device, there is a high possibility that the stored data may be distorted or damaged due to unintended write operation or external noise. .

Accordingly, a conventional display device requires a method for improving a problem in which data stored in an external memory due to an unintended write operation or external noise is distorted or damaged.

Embodiments of the present invention to solve the above-described problems of the background art, a display device that can improve the problem that the data stored in the external memory interlocked with the timing controller is not distorted or damaged due to unintended write operations and external noise, etc. To provide.

In accordance with the above-mentioned problem solving means, an embodiment of the present invention, the timing control unit; A data driver for driving under the control of the timing controller; A display panel displaying an image by a data signal supplied from a data driver; And an external memory unit connected to one of the terminals of the data driving unit and providing data stored therein in cooperation with the timing control unit.

The light protection terminal of the external memory unit may be connected to one of the output terminals of the data driver.

The external memory unit may control the read / write function by the voltage output from the data driver.

The external memory unit may perform only a read function by the gamma voltage output from the gamma buffer terminal of the data driver.

The external memory unit may include a voltage dividing circuit for lowering the gamma voltage output from the gamma buffer terminal of the data driver to a lower logic high voltage.

The voltage dividing circuit may include a first voltage divider having one end connected to the gamma buffer terminal of the data driver, and a second voltage divider having one end connected to the other end of the first voltage divider and the other end connected to the ground wiring.

The external memory unit may include a first resistor having one end connected to the light protection terminal and a divider circuit having a dividing node connected to the other end of the first resistor.

The external memory unit may include a voltage change circuit for changing the first potential voltage output from the data driver to a lower second potential voltage.

The external memory unit may include a first resistor having one end connected to the light protection terminal and a voltage change circuit having an output terminal connected to the other end of the first resistor.

The display panel may be one of a liquid crystal display panel and an organic light emitting display panel.

The embodiment of the present invention has an effect of providing a display device capable of improving the problem that data stored in an external memory interworking with a timing controller is not distorted or damaged due to an unintended write operation or external noise.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.
2 and 3 are exemplary circuit diagrams of the subpixel illustrated in FIG. 1.
4 is a layout view of the display device illustrated in FIG. 1.
5 is a diagram for describing a main configuration of a display device according to an exemplary embodiment of the present invention.
6 is an exemplary view using some of the components shown in FIG. 5.
FIG. 7 is an exemplary circuit diagram illustrating some components of FIG. 6. FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention. FIGS. 2 and 3 are exemplary circuit diagrams of a subpixel shown in FIG. 1, and FIG. 4 is a display device shown in FIG. 1. Is an example of arrangement.

As shown in FIG. 1, the display device according to the exemplary embodiment includes a timing controller 110, an external memory unit 120, a data driver 130, a gate driver 140, and a display panel 150. Included.

The timing controller 110 controls the operation timing of the data driver 130 and the gate driver 140 using timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. Since the timing controller 110 may determine the frame period by counting the data enable signal of one horizontal period, the vertical synchronization signal and the horizontal synchronization signal supplied from the outside may be omitted.

The control signals generated by the timing controller 110 include a gate timing control signal GDC for controlling the operation timing of the gate driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130. ) Is included. The gate timing control signal GDC includes a gate start pulse, a gate shift clock, a gate output enable signal, and the like. The data timing control signal DDC includes a source start pulse, a source sampling clock, a source output enable signal, and the like.

The external memory unit 120 provides data stored therein to the timing controller 110 in cooperation with the timing controller 110. In conjunction with the external memory unit 120, the timing controller 110 may receive various data and perform signal processing or data compensation based thereon.

The data driver 130 samples and latches the data signal DATA supplied from the timing controller 110, converts the digital data signal into an analog data signal of a parallel data system according to the gamma voltage, and converts the converted data signal into a subpixel. Are supplied through the data lines DL1 to DLn connected to the data points SP.

The data driver 130 may be mounted on one side of the display panel 150 in the form of an integrated circuit (IC) or in the form of a tape carrier package (TCP) according to the structure of the display panel 150, and may be mounted on the display panel 150. It may be composed of a number depending on the size of).

The gate driver 140 sequentially generates a gate signal while shifting a level of the signal to a swing width of a gate driving voltage at which the transistors can operate, and gate lines GL1 ˜to which the generated gate signal is connected to the subpixels SP. Supply via GLm).

The gate driver 140 may be formed in the display panel 150 along with a thin film transistor process using a gate-in panel method or may be mounted in an integrated circuit (IC) form according to the structure of the display panel 150. According to the size of the display panel 150, the display panel 150 may be configured in plurality.

When the gate driver 140 is mounted in the form of an integrated circuit, the gate driver 140 includes a shift register, a level shifter, a shift register, a plurality of AND gates, and an inverter 64. The shift register sequentially shifts the gate start pulse according to the gate shift clock using a plurality of cascaded D-flip flops. The AND gates generate an output by ANDing the output signal of the shift register and the inverted signal of the gate output enable signal, respectively. The inverter inverts the gate output enable signal and supplies it to the AND gates. The level shifter shifts the output voltage swing width of the AND gate to the swing width of the scan voltage in which the transistors included in the display panel 150 can operate. The gate signal output from the level shifter is sequentially supplied to the gate lines GL1 to GLm.

The display panel 150 displays an image. Sub-pixels SP including red, green, and blue are formed in the display panel 150. The subpixels SP define a display area, and an area other than the display area is defined as a non-display area.

The display panel 150 is one of a liquid crystal display panel and an organic light emitting display panel. Accordingly, the subpixels SP formed on the display panel 150 may be formed of a liquid crystal device including a liquid crystal layer or an organic light emitting diode including an organic light emitting diode.

When the subpixels SP are formed of a liquid crystal device, it may have a circuit configuration as shown in FIG. 2. The switching transistor TFT has a gate connected to the gate line GL1 to which the gate signal is supplied, one end thereof to the data line DL1 to which the data signal is supplied, and the other end thereof to the first node n1. The pixel electrode 1 positioned on one side of the liquid crystal cell Clc is connected to the first node n1 connected to the other end of the switching transistor TFT, and the common electrode 2 positioned on the other side of the liquid crystal cell Clc. ) Is connected to the common voltage wiring (Vcom). One end of the storage capacitor Cst is connected to the first node n1 and the other end thereof is connected to the common voltage wiring Vcom.

The subpixels SP formed of the liquid crystal device change the transmission amount of light from the backwriting unit according to the gate signal supplied through the gate line GL1 and the data signal supplied through the data line DL1, thereby causing an image. Can be displayed.

On the contrary, when the subpixels SP are formed of an organic light emitting diode, it may have a circuit configuration as shown in FIG. 3. The switching transistor T1 has a gate connected to the gate line GL1 to which the gate signal is supplied, one end thereof to the data line DL1 to which the data signal is supplied, and the other end thereof to the first node n1. The driving transistor T2 has a gate connected to the first node n1 and one end connected to a second node n2 connected to a power supply line VDD supplied with a high potential power supply Vdd, and a third node n3. The other end is connected. One end of the storage capacitor Cst is connected to the first node n1 and the other end thereof is connected to the second node n2. The organic light emitting diode D has a cathode connected to a ground line VSS to which an anode is connected to the third node n3 connected to the other end of the driving transistor T2 and a low potential power supply Vss is supplied.

The subpixels SP composed of the organic light emitting diodes change the amount of emission of light generated from the light emitting layer according to the gate signal supplied through the gate line GL1 and the data signal supplied through the data line DL1. An image can be displayed.

In the above description, FIGS. 2 and 3 merely illustrate and describe a typical circuit configuration to help understanding the subpixels SP, but one embodiment of the present invention is not limited thereto.

As illustrated in FIG. 4, the gate driver 140 may be formed in one non-marking area NA of the display area AA of the display panel 150 in a gate-in-panel manner. The data driver 130 may be mounted in the form of an integrated circuit on the tape carrier package 160. The timing controller 110 and the external memory unit 120 may be mounted on the printed circuit board 170 in the form of an integrated circuit.

Data stored inside the external memory unit 120 should be changed to match the characteristics of the display panel 150. Therefore, in the related art, even after the external memory unit 120 is mounted on the printed circuit board 170, the light protection terminal WP is processed in a ground wiring or a non-connected state (None Connect; NC). However, if the write protection terminal WP is grounded or unconnected, data stored in the external memory 120 may be distorted or damaged due to unintended write operation or external noise. High possession.

Therefore, an embodiment of the present invention improves the problem in which data stored in the external memory unit 120 is distorted or corrupted due to an unintended write operation or external noise as follows.

Hereinafter, the main configuration of the display device according to the exemplary embodiment of the present invention will be described in more detail.

FIG. 5 is a diagram illustrating a main configuration of a display device according to an exemplary embodiment of the present invention, FIG. 6 is an exemplary view using some components shown in FIG. 5, and FIG. 7 is a partial configuration shown in FIG. 6. An example of a circuit configuration for.

As shown in FIG. 5, the timing controller 110 receives various data in association with the external memory unit 120. The external memory unit 120 includes a nonvolatile memory (EEPROM), which is one of read / write storage devices.

 The external memory unit 120 is connected to one of the terminals of the second data driver 130b, which is one of the data drivers 130a to 130b. In more detail, the write protection terminal WP of the external memory unit 120 is connected to one of the terminals of the second data driver 130b.

When the voltage output from the second data driver 130b is supplied to the write protection terminal WP of the external memory unit 120, the read / write function of the external memory unit 120 is controlled according to the type of the voltage. For example, when the write protection terminal WP of the external memory unit 120 is connected to or disconnected from the ground line to which the low potential power is supplied, read / write is possible, while connected to the power line to which the high potential power is supplied. Once in the state, only reads are possible.

Meanwhile, a voltage higher than a logic voltage required by the external memory unit 120 is input or output to the terminal of the second data driver 130b. Therefore, the voltage supplied to the write protection terminal WP of the external memory unit 120 should be a logic voltage level corresponding to 2.5V to 5.5V. Therefore, the external memory unit 120 includes a voltage change circuit 125 for changing the voltage output from the second data driver 130b to a logic high voltage required by the external memory unit 120. That is, the voltage change circuit 125 changes the first potential voltage output from the second data driver 130b to a lower second potential voltage.

The external memory unit 120 includes the voltage change circuit 125 as described above, and the voltage output from the terminal of the second data driver 130b is changed to a logic high voltage required by the external memory unit 120 so that the external memory When supplied to the write protection terminal WP of the unit 120, the external memory unit 120 performs only a read function.

In an embodiment of the present invention, a gamma voltage output from the gamma buffer terminal of the second data driver 130b is used as an example of the voltage supplied to the voltage change circuit 125 of the external memory unit 120. The gamma buffer terminal is included in all of the first to third data drivers 130a to 130c.

The first to third data drivers 130a to 130c including the gamma buffer terminal generate a gamma voltage based on the gamma reference voltage generated from the gamma reference voltage generator 135 mounted on the printed circuit board. As such, the structure in which the gamma buffer terminals are included in the first to third data drivers 130a to 130c can supply a constant voltage continuously and stably even when the external load changes instantaneously.

However, since the gamma voltage output from the gamma buffer terminal of the second data driver 130b is higher than the logic high voltage required by the external memory unit 120, it is down by the voltage change circuit 125 as shown in FIG. 5. After that, it is supplied to the write protection terminal WP of the external memory unit 120.

As shown in FIG. 6, the voltage change circuit 125 causes the gamma voltage GMAi output from the gamma buffer terminal of the second data driver 130b to be lowered to a logic high voltage required by the external memory unit 120. The voltage divider circuit 125 is configured.

In the voltage dividing circuit 125, one end is connected to the first voltage divider DR1 connected to the gamma buffer terminal of the second data driver 130b and the other end of the first voltage divider DR1 and the other end is connected to the ground wiring. The second voltage divider DR2 is included. The voltage dividing circuit 125 outputs a voltage down through the voltage dividing node DN positioned between the first voltage dividing resistor DR1 and the second voltage dividing resistor DR2. That is, the output terminal of the voltage dividing circuit 125 becomes the voltage dividing node DN.

The gamma voltage output from the gamma buffer terminal of the second data driver 130b may be different for each terminal. Therefore, the resistance values of the first voltage divider DR1 and the second voltage divider DR2 are selected according to the level of the gamma voltage supplied through one end of the first voltage divider DR1.

The external memory unit 120 includes a first resistor R1 having one end connected to the light protection terminal WP and a voltage divider circuit 125 having a divided node DN connected to the other end of the first resistor R1. do. Here, the write protection terminal WP of the external memory unit 120 receives the voltage output from the voltage dividing node DN of the voltage dividing circuit 125 through the first resistor R1. (R1) may be omitted.

As illustrated in FIG. 7, the external memory unit 120 is composed of a nonvolatile memory (EEPROM) having eight terminals A0, A1, A2, GND, VCC, WP, SCL, and SDA. The first to third terminals A0 to A2 of the external memory unit 120 are address terminals, the fourth terminal GND is a ground wiring terminal, and the fifth terminal VCC is a power wiring terminal, and the sixth terminal WP is a light protection terminal, and seventh and eighth terminals SCL and SDA are serial data communication terminals.

Ground wires are connected to the first, third, and fourth terminals A0, A2, and GND of the external memory unit 120. The fifth terminal VCC is connected to the power supply line VCC through the third resistor R3. The sixth terminal WP is connected to the voltage dividing node DN of the voltage dividing circuit 125 to receive the dummy power supply voltage DUMMY_VCC through the first resistor R1. The seventh and eighth terminals SCL and SDA are connected to a timing controller not shown, and the wires thereof are connected to the fifth terminal VCC through the fourth and fifth resistors R4 and R5.

One end of the first voltage divider DR1 of the voltage divider circuit 125 receives the gamma voltage GMAi through the gamma buffer terminal of the data driver as described above, and the gamma voltage together with the second voltage divider DR2 connected to the ground line. The GMAi is divided to output the dummy power voltage DUMMY_VCC through the divided node DN.

As described above, when the external memory unit 120 and the divider circuit 125 are configured, the divider circuit 125 may generate the dummy power supply voltage DUMMY_VCC by lowering the gamma voltage to a logic high voltage. Accordingly, since the external memory unit 120 can receive the voltage required by the external memory unit 120 through the sixth terminal WP, which is a write protection terminal, the external memory unit 120 only performs a read function. do.

By the above configuration, since the external memory unit 120 performs only a read function, the problem that the stored data is distorted or damaged due to an unintended write operation or external noise is prevented.

On the other hand, in the embodiment of the present invention, the voltage provided to the voltage dividing circuit 125 of the external memory unit 120 is an example of the gamma buffer terminal of the data driver. However, the voltage provided to the voltage dividing circuit 125 of the external memory unit 120 may be configured circuitry and electrically to use another voltage.

As described above, the present invention has an effect of providing a display device capable of improving a problem in which data stored in an external memory interworking with a timing controller is not distorted or corrupted due to an unintended write operation or external noise.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

110: timing control unit 120: external memory unit
130: data driver 140: gate driver
150: display panel WP: light protection terminal
125: voltage divider circuit DR1: first voltage divider
DR2: second voltage divider

Claims (10)

A timing controller;
A data driver driving under the control of the timing controller;
A display panel for displaying an image by a data signal supplied from the data driver; And
And an external memory unit coupled to the timing controller to provide data stored therein to the timing controller and connected to one of the terminals of the data driver. The method of claim 1,
The light protection terminal of the external memory unit
And a display device connected to one of the output terminals of the data driver. The method of claim 1,
The external memory unit
And a read / write function is controlled by a voltage output from the data driver. The method of claim 1,
The external memory unit
And a read function is performed only by the gamma voltage output from the gamma buffer terminal of the data driver. The method of claim 1,
The external memory unit
And a voltage divider circuit for lowering the gamma voltage output from the gamma buffer terminal of the data driver to a lower logic high voltage. The method of claim 5,
The voltage divider circuit
A first voltage divider having one end connected to the gamma buffer terminal of the data driver;
And a second voltage divider resistor having one end connected to the other end of the first voltage divider resistor and the other end connected to the ground wiring. The method according to claim 6,
The external memory unit
A first resistor having one end connected to the light protection terminal;
And a voltage divider circuit connected to a voltage divider node at the other end of the first resistor. The method of claim 1,
The external memory unit
And a voltage change circuit for changing the first potential voltage output from the data driver to a lower second potential voltage. 9. The method of claim 8,
The external memory unit
A first resistor having one end connected to the light protection terminal;
And a voltage change circuit having an output terminal connected to the other end of the first resistor. The method of claim 1,
The display panel
A display device comprising one of a liquid crystal display panel and an organic light emitting display panel.
KR1020110111209A 2011-10-28 2011-10-28 Display device KR20130046680A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160031579A (en) * 2014-09-12 2016-03-23 엘지디스플레이 주식회사 Display Device
KR20160082730A (en) * 2014-12-29 2016-07-11 엘지디스플레이 주식회사 Display device
KR20170050620A (en) * 2015-10-30 2017-05-11 엘지디스플레이 주식회사 Memory Interface Device And Method For Driving the Same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160031579A (en) * 2014-09-12 2016-03-23 엘지디스플레이 주식회사 Display Device
KR20160082730A (en) * 2014-12-29 2016-07-11 엘지디스플레이 주식회사 Display device
KR20170050620A (en) * 2015-10-30 2017-05-11 엘지디스플레이 주식회사 Memory Interface Device And Method For Driving the Same

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