KR20130046239A - Method of manufacturing a electronic component embedded printed circuit board - Google Patents

Method of manufacturing a electronic component embedded printed circuit board Download PDF

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KR20130046239A
KR20130046239A KR1020110110701A KR20110110701A KR20130046239A KR 20130046239 A KR20130046239 A KR 20130046239A KR 1020110110701 A KR1020110110701 A KR 1020110110701A KR 20110110701 A KR20110110701 A KR 20110110701A KR 20130046239 A KR20130046239 A KR 20130046239A
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South Korea
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electronic component
cavity
printed circuit
circuit board
layer
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KR1020110110701A
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Korean (ko)
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정연경
고영주
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아페리오(주)
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

PURPOSE: An electronic component embedded type printed circuit board manufacturing method is provided to align and accommodates an electronic component in a designated location within a cavity without using an adhesion layer. CONSTITUTION: An insulation layer forms a cavity to embed an electronic component. An electronic component(170) is accommodated in the cavity. When the electronic component is accommodated, a semi-hardened state first insulation layer(180) and a first copper thin film layer(190) are stacked on both up and down sides and laminated by heating and pressurizing. . Via holes(220,230) electrically connect the IO terminal bump of the electronic component with the first copper thin film layer in the surface by performing copper plating after selectively etching the first copper thin film layer of the surface of an outer layer and the first insulation layer or an insulation layer of an inner layer.

Description

전자부품 내장형 인쇄회로기판 제조방법{METHOD OF MANUFACTURING A ELECTRONIC COMPONENT EMBEDDED PRINTED CIRCUIT BOARD} METHODS OF MANUFACTURING A ELECTRONIC COMPONENT EMBEDDED PRINTED CIRCUIT BOARD

본 발명은 전자부품 내장형(electronic component-embedded) 인쇄회로기판(printed circuit board; PCB) 또는 패키지기판(package board) 제조방법에 관한 것으로, 특히 캐비티(cavity) 속의 제 위치에 전자부품을 정렬해서 수납시키는 방법에 관한 것이다. 더욱 상세하게는, 종래기술이 사용하는 접착테이프 또는 접착 페이스트를 사용하지 아니하고도 캐비티 속에 전자부품을 정렬해서 안착시킬 수 있는 전자부품 내장형 인쇄회로기판 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electronic component-embedded printed circuit board (PCB) or a package board, and in particular, arranges and stores electronic components in place in a cavity. It is about how to let. More specifically, the present invention relates to an electronic component embedded printed circuit board manufacturing method capable of aligning and seating electronic components in a cavity without using an adhesive tape or an adhesive paste used in the prior art.

최근 들어, 웨이퍼 레벨의 칩(chip)을 인쇄회로기판 속에 직접 내장하여 제작하는 내장형 인쇄회로기판(Embedded Printed Circuit Board) 기술에 대한 연구개발이 활발히 진행되고 있다. 칩을 기판 속에 내장하게 되면, 전자부품의 사이즈가 축소되어 전자기기의 소형화 및 경량화에 도움이 되며, 기생성분을 제거할 수 있어서 회로의 동작주파수를 증대시킬 수 있음은 물론, 잡음을 일으키는 외부 전자파의 영향을 차단하는 장점이 있다. Recently, research and development of embedded printed circuit board technology, which directly fabricates a wafer-level chip in a printed circuit board, has been actively conducted. When the chip is embedded in the substrate, the size of the electronic components is reduced, which helps to reduce the size and weight of the electronic device, and eliminates parasitic components, thereby increasing the operating frequency of the circuit, as well as generating external electromagnetic waves. It has the advantage of blocking the effects of.

더욱이, 스마트폰 또는 스마트 패드 등과 같은 휴대용 전자기기의 시장이 폭발적으로 커지면서, 경박단소 제품에 대처할 수 있는 칩 내장형 인쇄회로기판 제조가 절실히 요구되고 있다. 인쇄회로기판을 경박단소화하기 위해서 다양한 종류의 전자부품, 예를 들어 반도체 칩과 같은 능동소자뿐 아니라, 저항 및 캐패시터와 같은 수동소자들을 인쇄회로기판에 내장시키고 있다. In addition, as the market for portable electronic devices such as smart phones or smart pads has exploded, there is an urgent need for manufacturing chip embedded printed circuit boards that can cope with light and thin products. In order to reduce the size of the printed circuit board, various types of electronic components, for example, active devices such as semiconductor chips, as well as passive devices such as resistors and capacitors are embedded in the printed circuit board.

이하, 본 발명의 명세서에서는 기판에 내장할 수 있는 반도체 칩, 다이, 모듈, 저항, 캐패시터 등 다양한 전자소자들을 모두 총칭해서 '전자부품(electronic component)'이라 칭하기로 한다. Hereinafter, in the specification of the present invention, various electronic devices, such as semiconductor chips, dies, modules, resistors, and capacitors, which can be embedded in a substrate, are collectively referred to as "electronic components."

내층에 캐비티를 가공해서 전자부품을 캐비티 속에 내장하는 기술은, 본원 출원발명의 출원인의 선등록 특허발명, 예를 들어 대한민국 특허공개 제10-2008-79391호, 대한민국 특허공개 제10-2008-79384호, 대한민국 특허공개 제10-2008-79388호에 상세히 설명되어 있다. The technique of processing the cavity in the inner layer and embedding the electronic component in the cavity is disclosed in the applicant's prior registered patent invention, for example, Korean Patent Publication No. 10-2008-79391, Korean Patent Publication No. 10-2008-79384 Korean Patent Publication No. 10-2008-79388.

전술한 선행기술 중 대한민국 특허공개 제10-2008-79388호에 개시된 전자부품내장 기술문헌을 살펴보면, 동박적층판(CCL; copper cladded laminate)을 가공해서 절연층에 캐비티를 제작하고, 절연층 하단에 접착테이프를 부착한 후, 전자부품을 캐비티 속으로 밀어넣어 접착테이프 위에 안착시키고, 그 위에 프리프레그(PREPREG)와 같은 반경화상태의 유동성 수지를 적층하고 가열 압착함으로써 캐비티 틈새를 수지로 밀봉하여 전자부품을 캐비티 속에 고정한 후 접착테이프를 물리적으로 벗겨내어 제거하는 기술을 개시하고 있다. Looking at the electronic component embedded technical document disclosed in the Republic of Korea Patent Publication No. 10-2008-79388 of the above prior art, to produce a cavity in the insulating layer by processing a copper cladded laminate (CCL), adhered to the bottom of the insulating layer After attaching the tape, the electronic part is pushed into the cavity to be seated on the adhesive tape, and the cavity gap is sealed with a resin by laminating and heat-pressing a semi-cured fluid such as a prepreg on the electronic part. After the fixing in the cavity is disclosed a technique for physically peeling off the adhesive tape.

그런데, 접착테이프의 표면은 상당한 접착력을 지니고 있어서, 적층 성형 후 접착필름을 물리적으로 벗겨내는 과정에서, 표면에 접착된 전자부품이 함께 붙어서 박리되는 경우가 발생하기도 하고, 또는 끈적끈적(sticky)한 접착물질이 기판 또는 부품 표면에 남아 있게 되는 경우도 발생하고, 물리적 분리과정에서 테이프의 접착력으로 인해서 기판이 휘거나 기판 표면이 손상되는 경우도 발생한다. 그 결과, 전자부품을 내장해서 가열 가압 적층성형 하는 과정 중은 물론, 적층 공정을 완료하고 수축하는 과정에서, 작업 불량발생으로 인해 생산수율이 떨어지는 문제가 발생한다. However, since the surface of the adhesive tape has considerable adhesive strength, in the process of physically peeling off the adhesive film after lamination, the electronic components adhered to the surface may stick together and peel off, or may be sticky. In some cases, the adhesive material may remain on the substrate or the component surface, and the substrate may be bent or the substrate surface may be damaged due to the adhesive force of the tape during physical separation. As a result, there is a problem in that the production yield is lowered due to defective work during the process of heating and press lamination by embedding the electronic component, as well as the completion and contraction of the lamination process.

따라서, 본 발명의 목적은 전자부품을 캐비티에 고정해서 수납시키는 과정 중에 접착층을 사용하지 아니하고도, 캐비티(cavity) 속의 제 위치에 전자부품을 정렬해서 수납할 수 있는 제조방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a manufacturing method in which electronic components can be aligned and stored in place in a cavity without using an adhesive layer during the process of fixing and storing the electronic components in the cavity.

상기 목적을 달성하기 위하여, 본 발명은 캐비티 속에 전자부품을 삽입하고, 상하 양면에 반경화상태의 에폭시 수지 또는 필름을 밀착시켜 적층한 후, 가열 가압 라미네이트 함으로써 전자부품을 캐비티에 수납시키는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized in that the electronic component is inserted into the cavity, the epoxy resin or the film of the semi-cured state on the upper and lower surfaces in close contact and laminated, and the electronic component is accommodated in the cavity by heating and pressure lamination. do.

본 발명에 따라 가열 가압 라미네이트 과정 중에, B 스테이지의 에폭시 수지 또는 필름은 녹아내려 흐름성을 지니게 되며, 레진이 흘러나와 캐비티의 틈새를 채우게 된다. 전자부품이 캐비티 내부로 삽입할 당시에 캐비티 정중앙에 위치하지 못하고 약간 비뚤어져 안착이 되었다 하더라도, 겔(gel) 상태의 유동성을 가진 레진의 유입으로 캐비티 중앙으로 자기자리를 바로잡아 안착하는 효과가 발생한다.During the hot press lamination process according to the present invention, the epoxy resin or film of the B stage melts to have flowability, and the resin flows out to fill the gap of the cavity. Even if the electronic parts are not positioned at the center of the cavity and are slightly crooked at the time when the electronic component is inserted into the cavity, the flow of the resin in the gel state corrects the seat to the center of the cavity.

스틱키(sticky)한 접착 테이프를 사용하는 종래기술과 달리, 본 발명은 인쇄회로기판 업계에서 통용되는 B 스테이지의 에폭시 수지를 사용해서 전자부품을 안착시키므로, 기판 표면에 스틱키한 접착재료가 묻어 남거나, 기판이 휘거나, 크랙이 생기거나 또는 박리(delamination), 워피지(warpage)가 발생하는 것을 방지할 수 있다. Unlike the prior art using sticky adhesive tape, the present invention uses the B stage epoxy resin commonly used in the printed circuit board industry to mount electronic components. Remaining, bending of the substrate, cracking, delamination, warpage can be prevented.

도1a 내지 도1i은 본 발명에 따라 전자부품 내장형 인쇄회로기판을 제작하는 과정을 나타낸 도면.1A to 1I illustrate a process of manufacturing an electronic component embedded printed circuit board according to the present invention.

본 발명은 전자부품을 내장한 인쇄회로기판을 제조하는 방법에 있어서, (a) 경화상태의 절연층에 전자부품을 내장할 캐비티를 형성하는 단계; (b) 상기 캐비티 속에 전자부품을 수납하는 단계; (c) 상기 단계 (b)의 결과 구조물 상하 양면에 반경화상태의 제1 절연층과 제1 동박을 적층하고 가열 가압하여 라미네이트 하는 단계; (d) 외층 표면 제1 동박과 상기 제1 절연층 및 내층의 절연층을 선택적으로 식각한 후 동도금을 실시해서, 전자부품의 입출력단자 범프와 표면 제1 동박을 선택적으로 전기접속하는 비아홀을 형성하는 단계를 포함하고, 상기 단계(b)의 수납 단계에서 전자부품을 캐비티에 고정하기 위해 테이프, 페이스트 등 부품고정재료를 사용하지 않음을 특징으로 하는 전자부품 내장형 인쇄회로기판 제조방법을 제공한다. 이하에서는 첨부도면 도1a 내지 도1i를 참조해서 본 발명의 양호한 실시예를 상세히 설명하기로 한다.The present invention provides a method of manufacturing a printed circuit board containing electronic components, the method comprising: (a) forming a cavity for embedding an electronic component in an insulating layer in a cured state; (b) receiving an electronic component in the cavity; (c) laminating the first insulating layer and the first copper foil in a semi-cured state on the upper and lower surfaces of the structure of the step (b) and laminating by heating and pressing; (d) After etching the outer surface of the first copper foil and the insulating layer of the first insulating layer and the inner layer selectively copper plating is performed to form a via hole for selectively electrically connecting the input and output terminal bumps of the electronic component and the surface first copper foil. It provides a method of manufacturing an electronic component-embedded printed circuit board, comprising the step of using, and in the storing step of the step (b) does not use a component fixing material such as tape, paste to fix the electronic component in the cavity. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, FIGS. 1A to 1I.

본 발명의 바람직한 실시예로서, 동박적층판(CCL; copper cladded laminate)과 같은 원자재에서 시작할 수 있으나, 반드시 이에 국한할 필요는 없다. 도1a는 본 발명의 양호한 실시예로서, 경화상태(C 스테이지)의 절연층(100) 양면에 동박(110a, 110b)이 덮여 있는 자재를 나타내고 있다. As a preferred embodiment of the present invention, it is possible to start with a raw material such as a copper cladded laminate (CCL), but it is not necessarily limited thereto. FIG. 1A illustrates a material in which copper foils 110a and 110b are covered on both sides of the insulating layer 100 in a hardened state (C stage) as a preferred embodiment of the present invention.

도1b를 참조하면, 기판에 드릴 공정을 수행해서 향후 후속 공정에서 정렬을 위해 사용할 가이드 홀(guide hole; 120)을 가공하는 과정을 볼 수 있다. 이어서, 도1c를 참조하면, 기판의 양면 동박(100a, 100b)을 선택적으로 식각 함으로써 향후 후속 공정에서 사용할 정렬마크(fiducial mark; 130)를 형성한다. 본 발명의 양호한 실시예로서, 도1c에 나타낸 정렬마크(130)는, 향후 전자부품을 제 위치에 정확히 안착하는 단계, 비아홀을 형성하는 단계 등과 같이 정렬이 필요한 단계에 정렬을 위한 레퍼런스(reference)로 사용하게 된다. 절연층(100)은 C 스테이지로 경화된 에폭시 수지가 사용될 수 있으며, 섬유질이 보강된 수지층이 사용될 수 있다. Referring to FIG. 1B, a process of drilling a guide hole 120 to be used for alignment in a subsequent process may be performed by performing a drill process on a substrate. Subsequently, referring to FIG. 1C, the double-sided copper foils 100a and 100b of the substrate are selectively etched to form a fiducial mark 130 to be used in a subsequent process. As a preferred embodiment of the present invention, the alignment mark 130 shown in FIG. Will be used. As the insulating layer 100, an epoxy resin cured in a C stage may be used, and a resin layer reinforced with fiber may be used.

도1d를 참조하면, 전자부품(칩)을 안착해서 내장하고자 하는 부위를 식각 제거함으로써 캐비티(150)를 형성한다. 캐비티 가공은 기계적 드릴, 레이저 드릴 또는 기타 화학적 식각 방식으로 가공할 수 있다. Referring to FIG. 1D, the cavity 150 is formed by etching and removing an area to be embedded by mounting an electronic component (chip). Cavity machining can be performed by mechanical drills, laser drills or other chemical etching methods.

그리고 나면, 내층의 캐비티(150)에 전자부품(170)을 밀어넣어 적당한 위치에 자리 잡도록 하고, 내층 기판의 상하 양면에 반경화성 에폭시 수지 또는 에폭시 필름을 적층한다. Then, the electronic component 170 is pushed into the cavity 150 of the inner layer so as to be positioned at an appropriate position, and a semi-curable epoxy resin or an epoxy film is laminated on both upper and lower surfaces of the inner layer substrate.

도1e를 참조하면, 내층의 캐비티(150) 속에 삽입된 전자부품(170)과 상하 양면에 적층된 절연층(180, 200)을 도시하고 있다. 절연층(180, 200)은 B 스테이지의 반경화성 수지로서, 프리프레그(PREPREG) 또는 에폭시 수지 필름이 사용될 수 있다. B 스테이지의 에폭시 수지는 열을 받는 경우 녹아내려 레진이 흘러나오게 되며, 레진이 전자부품이 장착된 캐비티 속의 틈새로 흘러들어가 채우게 된다.Referring to FIG. 1E, an electronic component 170 inserted into a cavity 150 of an inner layer and insulating layers 180 and 200 stacked on both upper and lower sides are illustrated. The insulating layers 180 and 200 are semi-curable resins of the B stage, and a prepreg or an epoxy resin film may be used. The epoxy resin in the B stage melts when heated and the resin flows out, and the resin flows into the gap in the cavity in which the electronic component is mounted to fill.

가열 가압 라미네이트 과정에서 겔(gel) 상태로 변한 수지 절연물질, 즉 흐름성을 지닌 레진은 틈새로 이동을 하면서 전자부품 위치를 변경시키게 되며, 확률적으로 전자부품을 캐비티의 정중앙으로 이동시켜 제 위치에 자리 잡도록 한다.The resin insulating material, which is changed into a gel state during the hot press lamination process, that is, the resin having flowability, changes the position of the electronic component as it moves through the gap, and it moves the electronic component to the center of the cavity in a stochastic manner. Make sure you are seated at.

도1f는 내층 기판 양면에 동박(190, 210)을 형성한 도면이다. 본 발명의 양호한 실시예로서, 도1e의 적층 단계에서, 절연층(180, 200)과 동박(190, 210)을 함께 적층 성형할 수 있다. 이어서, 도1g를 참조하면, 정렬마크(130) 상부에 위치한 동박(190)을 국부적으로 제거함으로써, 정렬마크(130)를 노출시켜 후속공정에서 정렬마크로 계속하여 사용할 수 있도록 한다.1F is a view in which copper foils 190 and 210 are formed on both sides of an inner layer substrate. In a preferred embodiment of the present invention, in the lamination step of FIG. 1E, the insulating layers 180 and 200 and the copper foils 190 and 210 may be laminated together. Subsequently, referring to FIG. 1G, by locally removing the copper foil 190 located above the alignment mark 130, the alignment mark 130 is exposed so that it can continue to be used as the alignment mark in a subsequent process.

도1h를 참조하면, 외층의 동박(190, 210)과 내장된 전자부품(170) 사이의 전기접속, 외층 동박(190, 210) 사이의 전기적 접속을 위해 비아홀(220, 230)을 가공한다. 비아홀 가공이 완료되면, 도1i에 도시된 대로, 비아홀 도금을 실시하여 전기 접속을 시도한다. Referring to FIG. 1H, the via holes 220 and 230 are processed for electrical connection between the copper foils 190 and 210 of the outer layer and the embedded electronic component 170 and electrical connection between the outer copper foils 190 and 210. When via hole processing is complete, via hole plating is performed to attempt electrical connection, as shown in FIG. 1I.

전술한 내용은 후술할 발명의 특허 청구 범위를 더욱 잘 이해할 수 있도록 본 발명의 특징과 기술적 장점을 다소 폭넓게 개선하였다. 본 발명의 특허 청구 범위를 구성하는 부가적인 특징과 장점들이 이하에서 상술 될 것이다. 개시된 본 발명의 개념과 특정 실시예는 본 발명과 유사 목적을 수행하기 위한 다른 구조의 설계나 수정의 기본으로서 즉시 사용될 수 있음이 당해 기술 분야의 숙련된 사람들에 의해 인식되어야 한다. The foregoing has somewhat improved the features and technical advantages of the present invention in order to better understand the claims of the invention described below. Additional features and advantages that constitute the claims of the present invention will be described in detail below. It should be appreciated by those skilled in the art that the disclosed concepts and specific embodiments of the invention can be used immediately as a basis for designing or modifying other structures to accomplish the invention and similar purposes.

또한, 본 발명에서 개시된 발명 개념과 실시예가 본 발명의 동일 목적을 수행하기 위하여 다른 구조로 수정하거나 설계하기 위한 기초로서 당해 기술 분야의 숙련된 사람들에 의해 사용될 수 있을 것이다. 또한, 당해 기술 분야의 숙련된 사람에 의한 그와 같은 수정 또는 변경된 등가 구조는 특허 청구 범위에서 기술한 발명의 사상이나 범위를 벗어나지 않는 한도 내에서 다양한 진화, 치환 및 변경이 가능하다. In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures to accomplish the same purpose of the present invention. It will be apparent to those skilled in the art that various modifications, substitutions and alterations can be made hereto without departing from the spirit or scope of the invention as defined in the appended claims.

이상과 같이, 본 발명은 스틱키(sticky)한 접착 테이프를 사용하는 종래기술과 달리, 본 발명은 인쇄회로기판 업계에서 통용되는 B 스테이지의 에폭시 수지를 사용해서 전자부품을 안착시키므로, 기판 표면에 스틱키한 접착재료가 묻어 남거나, 기판이 휘거나, 크랙이 생기거나 또는 박리(delamination), 워피지(warpage)가 발생하는 것을 방지할 수 있다. 본 발명은 인쇄회로기판 제작, 특히 반도체 칩 내장형 인쇄회로기판 또는 패키지기판 제조 시에 응용할 수 있어 제품의 수율을 증가시키고 신뢰성을 증대시킬 수 있는 장점이 있다. As described above, the present invention, unlike the prior art using a sticky adhesive tape, the present invention uses the epoxy resin of the B stage commonly used in the printed circuit board industry, so that the electronic component is seated on the substrate surface It is possible to prevent the sticky adhesive material from remaining, to bend the substrate, to crack, or to cause delamination and warpage. The present invention can be applied to the production of printed circuit board, in particular, semiconductor chip embedded printed circuit board or package substrate has the advantage of increasing the yield of the product and increase the reliability.

100, 180, 200 : 절연층
110a, 110b, 190, 210 : 동박
120 : 가이드 홀
130 : 정렬마크
150 : 캐비티
170 : 전자부품
171 : 범프
220, 230 : 비아홀100, 180, 200: insulation layer
110a, 110b, 190, 210: copper foil
120: guide hole
130: alignment mark
150: cavity
170: electronic component
171: bump
220, 230: Via Hole

Claims (1)

전자부품을 내장한 인쇄회로기판을 제조하는 방법에 있어서,
(a) 경화상태의 절연층에 전자부품을 내장할 캐비티를 형성하는 단계;
(b) 상기 캐비티 속에 전자부품을 수납하는 단계;
(c) 상기 단계 (b)의 결과 구조물 상하 양면에 반경화상태의 제1 절연층과 제1 동박을 적층하고 가열 가압하여 라미네이트 하는 단계;
(d) 외층 표면 제1 동박과 상기 제1 절연층 및 내층의 절연층을 선택적으로 식각한 후 동도금을 실시해서, 전자부품의 입출력단자 범프와 표면 제1 동박을 선택적으로 전기접속하는 비아홀을 형성하는 단계
를 포함하고, 상기 단계(b)의 수납 단계에서 전자부품을 캐비티에 고정하기 위해 테이프, 페이스트 등 부품고정재료를 사용하지 않음을 특징으로 하는 전자부품 내장형 인쇄회로기판 제조방법. In the method for manufacturing a printed circuit board containing electronic components,
(a) forming a cavity in which the electronic component is embedded in the cured insulating layer;
(b) receiving an electronic component in the cavity;
(c) laminating the first insulating layer and the first copper foil in a semi-cured state on the upper and lower surfaces of the structure of the step (b) and laminating by heating and pressing;
(d) After etching the outer surface of the first copper foil and the insulating layer of the first insulating layer and the inner layer selectively copper plating is performed to form a via hole for selectively electrically connecting the input and output terminal bumps of the electronic component and the surface first copper foil. Steps to
And a component fixing material such as a tape or a paste for fixing the electronic component to the cavity in the storing step of the step (b).
KR1020110110701A 2011-10-27 2011-10-27 Method of manufacturing a electronic component embedded printed circuit board KR20130046239A (en)

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