KR20130042733A - Liquid crystal display deivce and driving method the same - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a driving method thereof are provided to resolve the problem of an afterimage due to the DC voltage induction in liquid crystal by preventing data voltage from being deflected to a positive state or a negative state. CONSTITUTION: A data driving part(DDRV) comprises a data reversion part(156) and a data selection part(157). The data reversion part respectively reverses first positive data voltage and second negative data voltage for additionally generating data voltage including first negative data voltage and second positive data voltage. The data selection part differentiates the output order of the first positive data voltage, the first negative data voltage, the second positive data voltage, and the second negative data voltage by frame.

Description

Liquid crystal display device and driving method thereof {Liquid Crystal Display Deivce and Driving Method the same}

Embodiments of the present invention relate to a liquid crystal display and a driving method thereof.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, flat panel displays (FPDs), such as liquid crystal displays (LCDs), organic light emitting diodes (OLEDs), and plasma display panels (PDPs), may be used. Usage is increasing. Among them, liquid crystal display devices capable of realizing high resolution and capable of not only miniaturization but also enlargement are widely used.

The liquid crystal display device includes a liquid crystal panel having a liquid crystal layer positioned between a transistor substrate on which a transistor, a storage capacitor, a pixel electrode, and the like are formed, and a color filter substrate on which a color filter and a black matrix are formed. The liquid crystal panel displays an image by emitting light incident from the backlight unit by adjusting an arrangement direction of the liquid crystal layer by an electric field formed in the pixel electrode and the common electrode.

Since the liquid crystal basically has dielectric anisotropy characteristics, AC driving is performed to prevent induction of the direct current (DC) component of the liquid crystal. To this end, the data driver outputs the data voltage in a manner of alternating a positive data voltage and a negative data voltage based on the common voltage.

However, in the conventional data driver, when the luminance is set to the target gamma, the positive data voltage and the negative data voltage are non-uniformly generated and output due to the driving capability. In this case, when the LCD panel maintains the screen for a long time with a non-uniformly output data voltage, a DC voltage is induced in the liquid crystal, and an afterimage is generated.

According to an embodiment of the present invention for solving the above-described problems of the background art, the data voltage is prevented from shifting to either a positive state or a negative state so that the liquid crystal panel maintains a specific screen for a long time. It is an object of the present invention to provide a liquid crystal display device and a driving method thereof that can improve an afterimage generation problem.

Embodiments of the present invention provide a liquid crystal panel including subpixels. A gate driver supplying a gate signal through a gate line connected to the subpixel; And a data voltage including the first negative data voltage and the second positive data voltage by inverting the first positive data voltage and the second negative data voltage, respectively, to be output through the data line connected to the subpixel. A liquid crystal display device comprising a data driver for generating the first positive data voltage, the first negative data voltage, the second positive data voltage, and the second negative data voltage in different order of output.

The data driver generates a data voltage including the first negative data voltage and the second positive data voltage by inverting the first positive data voltage and the second negative data voltage respectively, which are scheduled to be output through the data line. And the output order of the first positive data voltage, the first negative data voltage, the second positive data voltage, and the second negative data voltage output from the data inversion unit for each N (N is an integer of 1 or more). It may include a different data selection unit.

The data driver may randomly output the output order of the first positive data voltage, the first negative data voltage, the second positive data voltage, and the second negative data voltage for each frame.

The first positive data voltage may have a higher level than the second positive data voltage, and the second negative data voltage may have a lower level than the first negative data voltage.

The data driver outputs the first positive data voltage in the first period, the first negative data voltage in the second period, and outputs the second positive data voltage having a lower level than the first positive data voltage in the third period. And output a second negative data voltage having a lower level than the first negative data voltage in the fourth period.

The data driver outputs a first positive data voltage in a first period, a second negative data voltage in a second period, and a second positive data voltage having a lower level than the first positive data voltage in a third period. And output a data voltage of the first sound having a higher level than the data voltage of the second sound in the fourth period.

In another aspect, an embodiment of the present invention provides a method of supplying a gate signal through a gate line connected to a subpixel; Generating a first negative data voltage and a second positive data voltage by inverting the first positive data voltage and the second negative data voltage, respectively, through the data line connected to the subpixel; And supplying the data voltage through the data line connected to the subpixel by changing the output order of the first positive data voltage, the first negative data voltage, the second positive data voltage, and the second negative data voltage. A driving method of a liquid crystal display device is provided.

In the data voltage supply step, the output order of the first positive data voltage, the first negative data voltage, the second positive data voltage, and the second negative data voltage is randomly changed for each N (N is an integer of 1 or more) frames. The first positive data voltage may have a higher level than the second positive data voltage, and the second negative data voltage may have a lower level than the first negative data voltage.

The data voltage supplying step outputs a first positive data voltage in a first period, a first negative data voltage in a second period, and a second positive data having a lower level than the first positive data voltage in a third period. The voltage may be output and a second negative data voltage having a lower level than the first negative data voltage may be output in the fourth period.

The data voltage supplying step outputs a first positive data voltage in a first period, a second negative data voltage in a second period, and a second positive data having a lower level than the first positive data voltage in a third period. The first negative data voltage having a higher level than the second negative data voltage may be output in the fourth period.

According to an exemplary embodiment of the present invention, a liquid crystal display capable of preventing a phenomenon in which a data voltage is biased in either a positive state or a negative state, thereby improving the afterimage generation problem caused by the induced voltage induced in the liquid crystal even if the liquid crystal panel maintains a specific screen for a long time. There is an effect of providing the device and its driving method.

1 is a schematic block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.
2 is an exemplary circuit configuration of a subpixel.
3 is a block diagram of a gate driver;
4 is a schematic configuration diagram of a data driver according to an embodiment of the present invention.
5 is a waveform diagram illustrating an example of a data voltage output from a data driver.
6 is a waveform diagram showing another example of the data voltage output from the data driver.
7 illustrates a liquid crystal display device driven in a frame inversion method.
8 is a view showing a liquid crystal display device driven in a dot inversion method.
9 is a view showing a liquid crystal display device driven in a line inversion method.
10 is a flowchart illustrating a method of driving a liquid crystal display according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 2 is an exemplary circuit diagram of a subpixel, and FIG. 3 is a block diagram of a gate driver.

1 to 3, a liquid crystal display according to an exemplary embodiment of the present invention includes a timing controller TCN, a power supply unit PWR, a common voltage driver VcomG, a data driver DDRV, and a gate driver SDRV), liquid crystal panel (PNL) and backlight unit (BLU).

The timing controller TCN receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal Data Enable, and the data signal DATA from the outside. The timing controller TCN operates the data driver DDRV and the gate driver SDRV using timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Control the timing.

Since the timing controller TCN may determine the frame period by counting the data enable signal DE of one horizontal period, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync supplied from the outside may be omitted. Representative control signals generated by the timing controller TCN include a gate timing control signal GDC for controlling the operation timing of the gate driver SDRV and a data timing control signal for controlling the operation timing of the data driver DDR. DDC).

The gate timing control signal GDC includes a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE. The gate start pulse GSP is supplied to a gate drive IC (Integrated Circuit) generating the first gate signal. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal DDC includes source start pulses (Source, Start Pulse, SSP), Source Sampling Clock (SSC), Source Output Enable (SOE), and the like. The source start pulse SSP controls the data sampling start time of the data driver DDRV. The source sampling clock SSC is a clock signal that controls the sampling operation of data in the data driver DDRV based on the rising or falling edge. The source output enable signal SOE controls the output of the data driver DDRV. Meanwhile, the source start pulse SSP supplied to the data driver DVV may be omitted according to the data transmission method.

The power supply unit PWR generates a driving voltage by varying the voltage Vin supplied from the system board, and generates the generated driving voltage as the timing controller TCN, the data driver DVB, the gate driver SDRV, and the common voltage driver VcomG. ) And liquid crystal panel PNL. In addition, the power supply unit PWR generates gamma voltages GMA0 to GMAn and supplies them to the data driver DDRV and the liquid crystal panel PNL.

The common voltage driver VcomG generates a common voltage using the voltage supplied from the power supply unit PWR and supplies it to the common voltage lines Vcom. The common voltage driver VcomG is formed on the liquid crystal panel PNL or is formed outside the liquid crystal panel PNL.

The liquid crystal panel PNL displays an image. The liquid crystal panel PNL includes a liquid crystal layer positioned between the thin film transistor substrate (hereinafter, abbreviated as TFT substrate) and the color filter substrate. Data lines, gate lines, common voltage lines, TFTs, storage capacitors, etc. are formed on the TFT substrate, and black matrices, color filters, etc., are formed on the color filter substrate. The polarizing plate is attached to the TFT substrate and the color filter substrate of the liquid crystal panel PNL, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed. The liquid crystal panel PNL includes subpixels SP defined by data lines and gate lines that cross each other.

The subpixel SP formed in the liquid crystal panel PNL may have a circuit configuration as shown in FIG. 2. The switching transistor TFT has a gate connected to the gate line G1 to which the gate signal is supplied, one end thereof to the data line D1 to which the data signal is supplied, and the other end thereof to the first node n1. The pixel electrode 1 positioned on one side of the liquid crystal cell Clc is connected to the first node n1 connected to the other end of the switching transistor TFT, and the common electrode 2 positioned on the other side of the liquid crystal cell Clc. ) Is connected to the common voltage wiring (Vcom). One end of the storage capacitor Cst is connected to the first node n1 and the other end thereof is connected to the common voltage wiring Vcom. The liquid crystal panel PNL having the sub pixel SP structure may be configured to provide light provided from the backlight unit BLU according to a gate signal supplied through the gate line G1 and a data signal supplied through the data line D1. An image can be displayed by causing a change in the amount of permeation.

The liquid crystal panel (PNL) operating as described above may be implemented in any liquid crystal mode as well as IPS (In Plane Switching) mode, FFS (Fringe Field Switching) mode, TN (Twisted Nematic) mode, VA (Vertical Alignment) mode. .

The backlight unit BLU provides light to the liquid crystal panel PNL. The backlight unit BLU includes a light source circuit unit including a DC power supply unit, light emitting units, transistors, and a driving control unit, and an optical unit unit including a cover bottom, a light guide plate, an optical sheet, and the like.

The backlight unit BLU may be configured in various ways such as an edge type, a dual type, a direct type, and the like. Here, the edge type is one in which light emitting diodes are arranged in a line (or string) form on one side of the liquid crystal panel PNL. The dual type is one in which light emitting diodes are arranged in a string (or string) on both sides of the liquid crystal panel PNL. In the direct type, the light emitting diodes are arranged in a block or matrix form under the liquid crystal panel PNL.

The gate driver SDRV is a swing width of a gate driving voltage at which TFTs of the subpixels SP included in the liquid crystal panel PNL can operate in response to the gate timing control signal GDC supplied from the timing controller TCN. The gate signal is sequentially generated while shifting the signal level. The gate driver SDRV supplies the gate signals generated through the gate lines GL to the subpixels SP included in the liquid crystal panel PNL.

As shown in FIG. 3, the gate driver SDRV includes gate drive ICs. The gate driver SDRV includes a shift register 61, a level shifter 63, a shift register 61, a plurality of AND gates 62, an inverter 64, and the like. The shift register 61 sequentially shifts the gate start pulse GSP according to the gate shift clock GSC using a plurality of D-flip flops connected in a cascade manner. The AND gates 62 generate an output by logically multiplying the output signal of the shift register 61 and the inverted signal of the gate output enable signal GOE. The inverter 64 inverts the gate output enable signal GOE and supplies it to the AND gates 62. The level shifter 63 shifts the output voltage swing width of the AND gate 62 to the swing width of the gate voltage at which the transistors included in the display panel PNL can operate. The gate signals output from the level shifter 63 are sequentially supplied to the gate lines GL.

The gate driver SDRV described with reference to FIG. 3 is an example of an integrated circuit IC. Therefore, when the gate driving unit SDRV is configured by a gate-in panel method formed on a substrate during a thin film transistor process, the gate driving unit SDRV has a different form.

The data driver DDRV samples, latches, and converts the data signal DATA supplied from the timing controller TCN in response to the data timing control signal DDC supplied from the timing controller TCN to convert data into a parallel data system. . The data driver DDRV converts the data signal DATA into a gamma reference voltage when converting the data into a parallel data system. The data driver DDRV supplies the data voltage DATA converted through the data lines DL to the subpixels SP included in the liquid crystal panel PNL.

The data driver DDRV inverts the first positive data voltage and the second negative data voltage, which are scheduled to be output, through the data lines DL connected to the subpixels SP, respectively. An additional data voltage including two positive data voltages is generated. The data driver DVV corrects the output order of the data voltages so that the output order of the first positive data voltage, the first negative data voltage, the second positive data voltage, and the second negative data voltage is different. This is described below.

Hereinafter, the data driver according to an embodiment of the present invention will be described in more detail.

4 is a schematic configuration diagram of a data driver according to an exemplary embodiment of the present invention, FIG. 5 is a waveform diagram illustrating an example of the data voltage output from the data driver, and FIG. 6 is a diagram of the data voltage output from the data driver. This is a waveform diagram showing another example.

As shown in FIG. 4, the data driver DDRV includes data drive ICs. The data driver DDRV includes a shift register 151, a data register 152, a first latch 153, a second latch 154, a converter 155, a data inverter 156, and a data selector 157. ) Is included.

The shift register 151 shifts the source sampling clock SSC supplied from the timing driver TCN. The shift register 151 transfers a carry signal CAR to a shift register of a source driver IC of a neighboring next stage. The data register 152 temporarily stores the data signal DATA supplied from the timing driver TCN and supplies it to the first latch 153. The first latch 153 samples and latches a data signal DATA input in series according to a clock sequentially supplied from the shift register 151, and then simultaneously outputs the latched data. The second latch 154 latches the data supplied from the first latch 153 and then latches the data latched in synchronization with the second latch 154 of the other source drive ICs in response to the source output enable signal SOE. Output at the same time. The converter 155 converts the data signal DATA input from the second latch 154 into gamma reference voltages GMA1 to GMAn. The data inversion unit 156 inverts the first positive data voltage and the second negative data voltage, which are scheduled to be output through the data lines D1 to Dm, respectively, so that the first negative data voltage and the second positive data voltage are reversed. Create additional The data selector 157 outputs the first positive data voltage, the first negative data voltage, the second positive data voltage, and the second negative data voltage output from the data inverting unit 156 by N (N). Is an integer greater than or equal to 1) and is supplied to the data lines D1 to Dm in response to the source output enable signal SOE.

In the above description, the data inverting unit 156 may use a conversion unit for converting the charge pump or gamma set value inversely. In addition, the data selection unit 157 is illustrated as a configuration including an output circuit unit for controlling the data voltage output through the data lines D1 to Dm. However, the data selector 157 and the output circuit may be configured separately.

The data driver DDRV randomly outputs the output order of the first positive data voltage, the first negative data voltage, the second positive data voltage, and the second negative data voltage at least one frame. Here, the first positive data voltage has a higher level than the second positive data voltage, and the second negative data voltage has a lower level than the first negative data voltage.

5 illustrates an example of a data voltage output from the data driver DDRV. As shown in FIG. 5 (II), the data driver DDRV uses the first positive data voltage ⓐ to be output during the first frame Frame1 as shown in FIG. 5 (I). In addition to ①), a first negative data voltage ② is generated. Then, as shown in FIG. 5 (II), the output of the data voltage such that the first positive data voltage ① and the first negative data voltage ② are divided into the first period P1 and the second period P2. The order is different. Here, the first positive data voltage ① has a high level of positive voltage based on the common voltage Vcom, and the first negative data voltage ② has a high level of negative voltage based on the common voltage Vcom. Has a voltage.

Similarly, the data driver DDRV uses the second sound data voltage ⓑ to be output during the second frame Frame2 as shown in FIG. 5 (I), and the second sound as shown in FIG. 5 (II). In addition to the data voltage (4), a second positive data voltage (3) is inverted. Then, as shown in FIG. 5 (II), the data voltage is output so that the second positive data voltage ③ and the second negative data voltage ④ are divided into the third period P3 and the fourth period P4. The order is different. Here, the second positive data voltage ③ has a positive voltage at a lower level than the first positive data voltage ① based on the common voltage Vcom, and the second negative data voltage ④ is the common voltage. A negative voltage of a low level is compared to the first negative data voltage ② based on Vcom.

That is, the data inverting unit 156 and the data selecting unit 157 of the data driving unit DVV have the first positive data voltage ⓐ and the second negative data voltage ⓑ whose output are scheduled to be the first positive data. The additional generated voltage is written in order of the voltage (①), the first negative data voltage (②), the second positive data voltage (③), and the second negative data voltage (④). Correct the data voltage to be adjusted.

6 illustrates another example of the data voltage output from the data driver DDRV. As shown in FIG. 6 (II), the data driver DDRV uses the first positive data voltage ⓐ that is scheduled to be output during the first frame Frame1 as shown in FIG. 6 (I). In addition to ①), a first negative data voltage ② is generated. Then, as shown in FIG. 6 (II), the data voltage is output so that the first positive data voltage ① and the first negative data voltage ② are divided into the first period P1 and the fourth period P4. The order is different. Here, the first positive data voltage ① has a high level of positive voltage based on the common voltage Vcom, and the first negative data voltage ② has a high level of negative voltage based on the common voltage Vcom. Has a voltage.

Similarly, the data driver DDRV uses the second sound data voltage ⓑ to be output during the second frame Frame2 as shown in FIG. 6 (I), and the second sound as shown in FIG. 6 (II). In addition to the data voltage (4), a second positive data voltage (3) is inverted. As shown in FIG. 6 (II), the data voltage is output so that the second negative data voltage ④ and the second positive data voltage ③ are divided into the second period P2 and the third period P3. The order is different. Here, the second positive data voltage ③ has a positive voltage at a lower level than the first positive data voltage ① based on the common voltage Vcom, and the second negative data voltage ④ is the common voltage. A negative voltage of a low level is compared to the first negative data voltage ② based on Vcom.

That is, the data inverting unit 156 and the data selecting unit 157 of the data driving unit DVV have the first positive data voltage ⓐ and the second negative data voltage ⓑ whose output are scheduled to be the first positive data. In addition to writing the voltage (①), the second negative data voltage (④), the second positive data voltage (③), and the first negative data voltage (②) in order, the output voltage is written. Correct the data voltage to be adjusted.

FIG. 7 is a view showing a liquid crystal display device driven by a frame inversion method, FIG. 8 is a view showing a liquid crystal display device driven by a dot inversion method, and FIG. 9 is a view showing a liquid crystal display device driven by a line inversion method. The figure shown.

As shown in FIGS. 7 to 9, the liquid crystal display device is driven in various inversion schemes to avoid the problem caused by the induction of the direct current (DC) component. The embodiment of the present invention can be applied to various methods such as the column inversion method as well as the frame inversion method, the dot inversion method and the line inversion method as shown in FIGS. .

Hereinafter, a driving method of a liquid crystal display device according to an exemplary embodiment of the present invention will be described.

10 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention. The driving method of the liquid crystal display device according to the exemplary embodiment of the present invention will be described with reference to FIGS. 1 to 10 to help understand the description.

First, a gate signal is supplied through a gate line connected to a sub pixel (S110).

Next, the first negative data voltage ⓐ and the second negative data voltage ⓑ are respectively inverted through the data line connected to the subpixel, thereby inverting the first negative data voltage ② and the second positive data voltage. A data voltage ③ is further generated (S120).

Next, the output order of the first positive data voltage (①), the first negative data voltage (②), the second positive data voltage (③), and the second negative data voltage (④) are changed to the subpixels. The data voltage is supplied through the connected data line (S130).

Next, an image is displayed based on the gate signal and the data voltage (S140).

On the other hand, in the data voltage supplying step S130, the first positive data voltage ①, the first negative data voltage ②, the second positive data voltage ③ and the second negative data voltage ④ The output order is randomly output for each of at least one frame. At this time, the first positive data voltage ① has a higher level than the second positive data voltage ③ and the second negative data voltage ④ has a lower level than the first negative data voltage ②.

In the data voltage supplying step S130, the first positive data voltage ① is output in the first period P1, the first negative data voltage ② is output in the second period P2, and the third period ( The second positive data voltage ③ may be output to P3), and the second negative data voltage ④ may be output to the fourth period P4.

Further, in the data voltage supplying step S130, the first positive data voltage ① is output in the first period P1, the second negative data voltage ④ is output in the second period P2, and the third The second positive data voltage ③ may be output in the period P3 and the first negative data voltage ② may be output in the fourth period.

In the above description, in order to prevent bias of the data voltage based on the common voltage Vcom, the data voltage is ①-> ②-> ③-> ④ or ①-> ④-> ③-> ②. Two examples of output have been described. However, if the predetermined data voltage is the same condition as ⓐ and ⓑ, the data voltage may be output in the order of ④-> ③-> ②-> ① or ②-> ③-> ④-> ①.

On the other hand, at the voltage set at which the output is intended, the luminance is determined to be (luminance in section ⓐ + luminance in section ⓑ) / 2. Therefore, ⓐ = ① = ②, ⓑ = ③ = ④ If there is a relationship between voltage levels (sum of luminance in sections ① to ④) / 4 = (sum of luminance in sections ⓐ to ⓑ) / 2, the output is scheduled The luminance of the voltage of the output set to be the same as the luminance of the corrected voltage output becomes the same. 5 and 6, ⓐ, ⓑ, ①, ②, ③ and ④ each represent a change in voltage of one sub-pixel in one frame period.

As described above, when the data driver outputs the data voltage, the data driver randomly varies the output of the data voltage for at least one frame so that the level of the positive state and the negative state does not deviate to either side, but the data voltage is symmetrical. Or symmetrical with time difference.

In the form as described above, when the output order and the voltage level of the data voltage are changed, it is possible to prevent the data voltage from being biased toward either the positive state or the negative state. As a result, the liquid crystal may escape from the problem caused by the induction of the direct current (DC) component, and the liquid crystal panel may improve the afterimage generation problem due to the induction of the direct voltage of the liquid crystal even if the liquid crystal panel is maintained for a long time.

As described above, embodiments of the present invention prevent a phenomenon in which the data voltage is biased in either a positive state or a negative state, so that an afterimage occurrence problem due to the induced voltage induced by the liquid crystal panel may be improved even if the liquid crystal panel maintains a specific screen for a long time. There is an effect of providing the device and its driving method. In addition, the embodiment of the present invention prevents a phenomenon in which the data voltage is biased toward either the positive state or the negative state, thereby improving the afterimage at all grayscale levels. In addition, according to the embodiment of the present invention, the set margin may be secured by inverting the set value corresponding to the target gamma to generate a voltage capable of improving the afterimage.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

TCN: Timing Control PWR: Power Supply
VcomG: Common Voltage Drive DDRV: Data Drive
SDRV: Gate driver PNL: LCD panel
BLU: Backlight Unit 151: Shift Register
152: Data register 153: first latch
154: second latch 155: conversion unit
156: data inversion unit 157: data selection unit

Claims (10)

A liquid crystal panel including sub pixels;
A gate driver supplying a gate signal through a gate line connected to the subpixel; And
Generate a data voltage including the first negative data voltage and the second positive data voltage by inverting the first positive data voltage and the second negative data voltage through the data line connected to the subpixel, respectively. ,
And a data driver for outputting the first positive data voltage, the first negative data voltage, the second positive data voltage, and the second negative data voltage in different order. The method of claim 1,
The data driver
A data panel further generating a data voltage including a first negative data voltage and a second positive data voltage by inverting the first positive data voltage and the second negative data voltage respectively scheduled to be output through the data line; All in all,
And a data selector for changing the output order of the first positive data voltage, the first negative data voltage, the second positive data voltage, and the second negative data voltage output from the data inverting unit. Liquid crystal display device. The method of claim 1,
The data driver
The output order of the first positive data voltage, the first negative data voltage, the second positive data voltage and the second negative data voltage is randomly changed for each N (N is an integer of 1 or more) frames. Liquid crystal display characterized in that. The method of claim 1,
The first positive data voltage has a higher level than the second positive data voltage,
And the data voltage of the second sound has a lower level than the data voltage of the first sound. The method of claim 1,
The data driver
Outputting the first positive data voltage in a first period and outputting the first negative data voltage in a second period and having a lower level than the first positive data voltage in a third period And output a data voltage of the second sound having a lower level than the data voltage of the first sound in a fourth period. The method of claim 1,
The data driver
Outputting the first positive data voltage in a first period and outputting the second negative data voltage in a second period and having a lower level than the first positive data voltage in a third period And outputs the data voltage of the first sound having a higher level than the data voltage of the second sound in a fourth period. Supplying a gate signal through a gate line connected to the sub pixel;
Generating a first negative data voltage and a second positive data voltage by inverting a first positive data voltage and a second negative data voltage respectively scheduled to be output through a data line connected to the subpixel; And
The data voltage is supplied through the data lines connected to the subpixels by changing the output order of the first positive data voltage, the first negative data voltage, the second positive data voltage, and the second negative data voltage. Method of driving a liquid crystal display device comprising the step of. The method of claim 7, wherein
The data voltage supply step
The output order of the first positive data voltage, the first negative data voltage, the second positive data voltage and the second negative data voltage is randomly changed for each N (N is an integer of 1 or more) frames. and,
And wherein the first positive data voltage has a higher level than the second positive data voltage and the second negative data voltage has a lower level than the first negative data voltage. The method of claim 7, wherein
The data voltage supply step
Outputting the first positive data voltage in a first period and outputting the first negative data voltage in a second period and having a voltage level lower than the first positive data voltage in a third period And outputting a data voltage at the second negative data voltage having a voltage level lower than that of the first negative data voltage in a fourth period. The method of claim 7, wherein
The data voltage supply step
Outputting the first positive data voltage in a first period and outputting the second negative data voltage in a second period and having a lower level than the first positive data voltage in a third period And outputting the first negative data voltage having a higher level than the second negative data voltage in the fourth period.

Images