KR20130033680A - Method for manufacturing of printed circuit board - Google Patents
Method for manufacturing of printed circuit board Download PDFInfo
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- KR20130033680A KR20130033680A KR20110097498A KR20110097498A KR20130033680A KR 20130033680 A KR20130033680 A KR 20130033680A KR 20110097498 A KR20110097498 A KR 20110097498A KR 20110097498 A KR20110097498 A KR 20110097498A KR 20130033680 A KR20130033680 A KR 20130033680A
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- insulating layer
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- carrier member
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Abstract
Description
The present invention relates to a method of manufacturing a printed circuit board.
In general, a printed circuit board is wired on one or both sides of a board made of various thermosetting synthetic resins with copper foil, and then an IC or an electronic component is disposed and fixed on the board and coated with an insulator by implementing electrical wiring therebetween.
In recent years, there has been a rapid increase in the demand for high performance and light weight shortening of electronic components in the development of the electronic industry, and accordingly, printed circuit boards on which these electronic components are mounted are also required to have high density wiring and thinning.
In particular, a coreless substrate that is capable of reducing the thickness of the entire printed circuit board by reducing the thickness of the printed circuit board and thus shortening the signal processing time has been attracting attention in order to cope with thinning of the printed circuit board.
In order to manufacture the above-mentioned coreless board | substrate, a thin board | substrate, an odd layer board | substrate, etc., the board | substrate is manufactured using the carrier member of various forms.
On the other hand, a method of manufacturing a printed circuit board using a carrier member according to the prior art is disclosed in Patent No. 3811680 (Japanese Patent).
However, in the substrate manufacturing process using the carrier member according to the prior art, the substrate is manufactured through a process of laminating a plurality of insulating layers and circuit layers on the carrier member and heat-compressing the substrate. There is a problem that warpage occurs.
The present invention is to solve the above-mentioned problems of the prior art, an aspect of the present invention is to provide a method for manufacturing a printed circuit board for manufacturing a printed circuit board with a minimized warpage (warpage) generation.
In addition, another aspect of the present invention is to provide a method for manufacturing a printed circuit board for manufacturing a substrate in which the chip mounting process stability is secured.
According to one or more exemplary embodiments, a method of manufacturing a printed circuit board may include preparing a carrier member made of an insulating material having metal foils formed on one or both surfaces thereof, forming a first insulating layer on the carrier member, and Forming a first metal layer on the insulating layer, disposing a pressing plate on the first metal layer, and heat-pressing the carrier member, the first insulating layer, and the first metal layer using the pressing plate. And forming a first circuit layer by patterning the first metal layer, wherein a coefficient of thermal expansion (CTE) of the carrier member is lower than a coefficient of thermal expansion (CTE) of the pressing plate.
Here, the metal foil may be made of a first metal foil and a second metal foil formed on the first metal foil.
The apparatus may further include a release layer formed between the first metal foil and the second metal foil.
In addition, the first metal foil and the second metal foil may be made of copper (Cu).
In addition, the first metal layer may be a copper foil.
In addition, the pressing plate may be made of stainless steel.
In addition, forming the first circuit layer by patterning the first metal layer may include forming an etching resist on the first metal layer, disposing a patterned mask on the etching resist, and exposing and developing processes. The method may include exposing the first metal layer by removing the etching resist of the patterned portion using a photolithography method including a step of removing the exposed first metal layer.
In addition, after the forming of the first circuit layer, forming a second insulating layer on the first insulating layer, forming a second metal layer on the second insulating layer, and the second metal layer Arranging a pressing plate on the substrate; heat pressing the first insulating layer, the second insulating layer, and the second metal layer using the pressing plate; and separating the carrier member from the first insulating layer. It may include.
The method may further include forming a second circuit layer by patterning the second metal layer after heat pressing the first insulating layer, the second insulating layer, and the second metal layer and a plurality of insulating layers on the second insulating layer. And forming a plurality of circuit layers.
The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.
Prior to that, terms and words used in the present specification and claims should not be construed in a conventional and dictionary sense, and the inventor may properly define the concept of the term in order to best explain its invention It should be construed as meaning and concept consistent with the technical idea of the present invention.
The present invention has an effect of controlling the degree of cure shrinkage of the insulating layer formed on the carrier member by manufacturing a printed circuit board using a carrier member and a pressure plate having different thermal expansion coefficients.
In addition, the present invention, as described above, by controlling the degree of cure shrinkage (cure shrinkage) of the insulating layer formed on the carrier member, there is an effect that can minimize the occurrence of warpage (warpage) of the final printed circuit board .
In addition, the present invention, as described above, by producing a printed circuit board with a minimized warpage (warpage) generation, there is an effect that can be improved after the stability of the chip mounting process.
1 to 7 are cross-sectional views sequentially illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention.
The objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and embodiments associated with the accompanying drawings. In the present specification, in adding reference numerals to the components of each drawing, it should be noted that the same components as much as possible even if displayed on different drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In this specification, the terms first, second, etc. are used to distinguish one element from another, and the element is not limited by the terms.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1 to 7 are process cross-sectional views sequentially illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention.
First, referring to FIG. 1, a
In the present embodiment, a resin insulating material may be used as the
The resin insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin impregnated with a reinforcing material such as glass fiber or an inorganic filler, for example, a prepreg, and also a thermosetting resin and / or Or a photocurable resin may be used, but is not particularly limited thereto.
In the present embodiment, as shown in FIG. 1, all of the metal foils 103 may be formed on the upper and lower surfaces of the
In the present embodiment, the metal foil 103 may include the
Here, the
In addition, the
In addition, although not shown in FIG. 1, the
Here, the release layer (not shown) is for controlling the adhesion between the
In this case, when a metal is used as the release layer (not shown), the release layer (not shown) may use a different kind of metal from the
In addition, the adhesive material such as the polymer material may include a material selected from the group consisting of fluorine-based, silicon-based, polyethylene terephthalate, polymethylpentene, and combinations thereof, but is not particularly limited thereto.
In addition, in this embodiment, the coefficient of thermal expansion (hereinafter, referred to as CTE) of the
This will be described later in detail in the heat compression process step.
Next, referring to FIG. 2, the first
Here, the first
In addition, the
Next, referring to FIG. 3, the
That is, as shown in FIG. 3, after the
In this embodiment, the
In this process, when the
In general, the
At this time, since the thickness of the
Accordingly, a portion of the insulating layer compressed on the
At this time, the larger the coefficient of thermal expansion (CTE) of the
Therefore, in the present exemplary embodiment, the thermal expansion coefficient CTE of the
That is, if the size of the expansion that is expanded when applying heat by lowering the coefficient of thermal expansion (CTE) of the
In this case, the coefficient of thermal expansion (CTE) of the
In general, the
In the present embodiment, the
For example, in the present embodiment, the thermal expansion coefficient CTE of the
CTE of carrier member
As shown in the table, when the coefficient of thermal expansion (CTE) of the
As such, when the
At this time, in the present experiment, when the coefficient of thermal expansion (CTE) of the
Next, referring to FIG. 4, the
In this case, the forming of the
First, an etching resist (not shown) is formed on the
In this case, the etching resist (not shown) may be a dry film (DF), but is not particularly limited thereto.
Next, a patterned mask (not shown) is disposed on the etching resist (not shown), and then the etching resist (not shown) of the patterned portion is removed by a photolithography method including an exposure and development process. One
Next, the exposed
In this case, removing the exposed
Next, referring to FIG. 5, a second insulating
Here, the second insulating
In addition, the
Next, referring to FIG. 6, the
Next, referring to FIG. 7, the
At this time, as described above, the metal foil 103 of the
Thereafter, an outermost layer circuit (not shown) may be formed on the separated
Since the method of forming the outermost layer circuit (not shown) and the solder resist layer (not shown) are well known techniques, a detailed description thereof will be omitted.
In addition, the first insulating
Although the present invention has been described in detail through specific embodiments of the present invention, this is for describing the present invention in detail and the method of manufacturing the printed circuit board according to the present invention is not limited thereto. It is obvious that modifications and improvements are possible by those skilled in the art.
It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
100: carrier member 101: insulating material
103:
103b: second metal foil 110: first insulating layer
120: first metal layer 125: first circuit layer
130: second insulating layer 140: second metal layer
200
Claims (9)
Forming a first insulating layer on the carrier member;
Forming a first metal layer on the first insulating layer;
Disposing a pressure plate on the first metal layer;
Heating and compressing the carrier member, the first insulating layer, and the first metal layer using the pressing plate; And
Patterning the first metal layer to form a first circuit layer
And a coefficient of thermal expansion (CTE) of the carrier member lower than a coefficient of thermal expansion (CTE) of the pressing plate.
The metal foil is a manufacturing method of a printed circuit board consisting of a first metal foil and a second metal foil formed on the first metal foil.
The method of manufacturing a printed circuit board further comprising a release layer formed between the first metal foil and the second metal foil.
The first metal foil and the second metal foil is a manufacturing method of a printed circuit board made of copper (Cu).
The first metal layer is a copper foil (Cu foil) manufacturing method of a printed circuit board.
The pressing plate is a manufacturing method of a printed circuit board made of stainless steel (stainless steel).
Patterning the first metal layer to form a first circuit layer,
Forming an etching resist on the first metal layer;
Disposing a patterned mask on the etch resist;
Exposing the first metal layer by removing the etch resist of the patterned portion using a photolithography process including an exposure and development process; And
Removing the exposed first metal layer
And a step of forming the printed circuit board.
After forming the first circuit layer,
Forming a second insulating layer on the first insulating layer;
Forming a second metal layer on the second insulating layer;
Disposing a pressure plate on the second metal layer;
Thermally compressing the first insulating layer, the second insulating layer, and the second metal layer by using the pressing plate; And
Separating the carrier member and the first insulating layer
Further comprising the steps of:
After the step of thermally compressing the first insulating layer, the second insulating layer and the second metal layer,
Patterning the second metal layer to form a second circuit layer; And
Forming a plurality of insulating layers and a plurality of circuit layers on the second insulating layer
Further comprising the steps of:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR20110097498A KR20130033680A (en) | 2011-09-27 | 2011-09-27 | Method for manufacturing of printed circuit board |
Applications Claiming Priority (1)
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KR20110097498A KR20130033680A (en) | 2011-09-27 | 2011-09-27 | Method for manufacturing of printed circuit board |
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KR20130033680A true KR20130033680A (en) | 2013-04-04 |
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KR20110097498A KR20130033680A (en) | 2011-09-27 | 2011-09-27 | Method for manufacturing of printed circuit board |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113923871A (en) * | 2021-09-26 | 2022-01-11 | 东莞康源电子有限公司 | Edge sealing design and manufacturing method of novel coreless substrate bearing layer |
-
2011
- 2011-09-27 KR KR20110097498A patent/KR20130033680A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113923871A (en) * | 2021-09-26 | 2022-01-11 | 东莞康源电子有限公司 | Edge sealing design and manufacturing method of novel coreless substrate bearing layer |
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