KR20130033237A - Gate in panel type liqiud crystal panel - Google Patents

Abstract

PURPOSE: A GIP type LCD panel is provided to prevent an error process by increasing the depth of the focused margin. CONSTITUTION: A second activation layer(223) is arranged in the overlapped region of a second source electrode(225a) and a second drain electrode(227a). The second source electrode and the second drain electrode are in parallel to a first source electrode and a first drain electrode for a thin film transistor.

Description

GIP type liquid crystal display panel {Gate In Panel type Liqiud Crystal Panel}

Embodiments of the present invention relate to a liquid crystal display panel, and more particularly, to a liquid crystal display panel that can improve the process yield in manufacturing a liquid crystal display panel.

LCDs have advantages of small size, thinness, and low power consumption, and are used in notebook PCs, office automation devices, and audio / video devices. In particular, an active matrix liquid crystal display device using a thin film transistor (hereinafter referred to as "TFT") as a switch element has been spotlighted as being suitable for displaying dynamic images.

On the other hand, the liquid crystal display device includes a liquid crystal display panel, a driving circuit unit for applying a voltage for driving the liquid crystal layer, and a backlight unit for scanning light to the liquid crystal display panel.

Here, the liquid crystal display panel is formed by crossing a plurality of voltage wires, and a thin film transistor (TFT) is formed at the intersections thereof to switch voltages applied to the liquid crystal layer according to voltages applied from the plurality of voltage wires. An image can be expressed.

Hereinafter, the planar structure of the liquid crystal display panel will be described in more detail.

1 is a schematic view of a liquid crystal display panel of the prior art.

As illustrated, the liquid crystal display panel may include a display unit 10, a gate driver 20, a data driver 30, and a timing controller 40.

The liquid crystal panel 10 is formed by crossing a plurality of gate lines GL and data lines DL, which define a pixel region, and a liquid crystal capacitor Clc for each pixel region defined by two lines GL and DL. ), A storage capacitor (Cst), and a thin film transistor (TFT) for driving the liquid crystal capacitor.

When the driving signal is input from the gate line GL, the thin film transistor TFT is turned on to supply the image signal of the data line DL to the liquid crystal capacitor Clc, and the driving signal is input. If not, it is turned off to maintain the image signal charged in the liquid crystal capacitor Clc until the next frame.

The storage capacitor Cst may be further provided as a storage capacitor for stably maintaining the charged image signal until the next image signal is applied.

The liquid crystal capacitor Clc displays an image by adjusting the light transmittance by adjusting an arrangement state according to an image signal charged by the on-off operation of the thin film transistor TFT.

The timing controller 40 generates a control signal for driving the gate and data drivers 20 and 30 using an external signal.

The gate driver 20 turns on the thin film transistor TFT by receiving a control signal from the timing controller 40 and sequentially supplying a driving signal of the thin film transistor TFT to the gate line GL.

The data driver 30 receives a control signal and an image signal from the timing controller 40 and generates a plurality of data signals for one horizontal line in synchronization with a drive signal of a thin film transistor TFT applied to the gate line GL. Supply to the line DL.

Accordingly, the image signal may be properly transmitted and the screen quality of the display unit 10 may be determined according to how accurately the thin film transistor TFT is switched.

If so, the pattern shape of the thin film transistor TFT is described.

2 is a plan view illustrating a pattern shape of a thin film transistor of a display unit and a gate driver of a liquid crystal display panel according to the related art.

In the liquid crystal display panel, both the gate driver 20 and the data driver 30 are mounted on the upper surface of the substrate.

The thin film transistor has a structure in which a gate electrode, an activation layer, a source electrode, and a drain electrode are sequentially stacked, and a channel through which electrons can move in the activation layer is formed by a voltage signal of the gate electrode. The voltage signal may be transferred between the drain electrodes.

First, the thin film transistor of the display unit 10 will be described.

The source electrode 15a is formed to protrude in a direction parallel to the long side direction of the display unit 10 on one side of the data line DL. In this case, the two protrusions have a shape having a space therebetween, and can be referred to simply as a U-shape. The drain electrode 15b may be inserted into the space of the source electrode 15a. The activation layer 13 is formed below the source electrode 15a and the drain electrode 15b, and a gate electrode is formed below the active layer 13.

Next, the thin film transistor of the gate driver 20 will be described.

The thin film transistor of the gate driver 20 is formed such that the source electrode 25 and the drain electrode 27 have a space between the plurality of protrusions and the protrusions at the top of the activation layer 23, respectively, which are fingered together. It has a shape. In this case, the direction in which the protrusions of the source electrode 25 and the drain electrode 27 are formed is a direction perpendicular to the forming direction of the source electrode 15a and the drain electrode 15b of the display unit 10.

In this case, A and B of the two transistors represent a channel length and greatly affect the characteristics of the transistor.

Meanwhile, an exposure process is performed to form the transistors, and the degree of exposure of the photoresist applied in the exposure process varies depending on the patterned direction due to the characteristics of the exposure process. However, the etching process that proceeds afterwards has a different degree of pattern formation even with slight changes of the previous process. As a result, precise exposure is required in the exposure process, resulting in a lack of depth of focus (DOF) margin.

Depth of focus (DOF) margin is the allowable range in which the mask can be moved on the vertical axis of the substrate in order to form a pattern of the same critical dimension (CD) on the substrate.

When the depth of focus margin is not secured, the channel pattern of the thin film transistor of the display unit and the gate driver may not be uniformly formed. That is, the lengths of A and B in FIG. 2 may be different. In this case, the uniformity of the on / off current may be degraded. In addition, a defect may occur in which a short occurs in a channel due to an error in pattern formation.

Therefore, in order to solve the above problems, embodiments of the present invention have an object to reduce process defects by making the channel forming directions of the transistors of the display unit and the gate driver the same. Other objects and features of the present invention will be described in the following detailed description and claims.

In order to achieve the above object of the present invention, a liquid crystal display panel according to an embodiment of the present invention, the first substrate is divided into a non-display unit including a display unit and a gate driver; A plurality of data lines and a plurality of gate lines formed on the display unit of the first substrate and crossing each other to define a plurality of pixels; A second substrate facing the first substrate; A liquid crystal layer interposed between the first substrate and the second substrate; A first thin film transistor formed at each pixel of the display unit and including a first source electrode having a concave-convex shape protruding in one direction from the data line and a first drain electrode inserted into the concave-convex shape; ; And a second source electrode and a second drain electrode formed in a concave-convex shape in the gate driver, wherein the concave-convex shapes of the second source electrode and the second drain electrode face each other so that the groove and the protrusion are engaged with each other. And a second thin film transistor, wherein the direction toward which the protrusions of the uneven shape of the first transistor and the second transistor face each other is parallel.

Preferably, the direction toward which the protrusions of the concave-convex shape face is characterized in that the direction is horizontal or perpendicular to the gate line.

The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode may be formed by an exposure process using a slit mask.

In addition, a data driving TCP including a data driving unit may be included on the other side of the first substrate on which the gate driving unit is not configured.

In addition, the pattern formed on the same layer including the second source electrode and the second drain electrode electrode of the second thin film transistor has a tree shape including a plurality of branches on both sides of one center line. It is characterized in that it has a shape in which concave-convex shapes face each other in the tree shape.

The plurality of branches may protrude perpendicularly to the center line and the protruding direction may be horizontal to the gate line.

In addition, the concave-convex shape and the tree shape are characterized in that the branch is formed in the form of a fingering inserted into the groove of the concave-convex shape.

The liquid crystal display panel according to at least one embodiment of the present invention configured as described above,

Increasing the depth of focus margin reduces process defects and improves process yield.

In addition, it is possible to increase the uniformity of the on / off current has the effect of stabilizing the quality.

In addition, since the horizontal size of the gate driver is reduced in comparison with the related art, a compact liquid crystal display panel can be manufactured.

1 is a schematic view of a liquid crystal display panel of the prior art.
2 is a plan view illustrating a pattern shape of a thin film transistor of a display unit and a gate driver of a liquid crystal display panel according to the related art.
3 is a schematic diagram of a liquid crystal display panel according to an exemplary embodiment of the present invention.
4 is a plan view of one pixel of a liquid crystal display panel according to an exemplary embodiment of the present invention.
5 is a plan view of a second thin film transistor of a gate driver according to an exemplary embodiment of the present invention.
6A through 6E are cross-sectional views illustrating a method of forming a thin film transistor according to an embodiment of the present invention, in a process sequence.
7A and 7B are graphs showing a relationship between a focal length and a halftone range for the prior art 2 and an embodiment of the present invention.
8 is a plan view illustrating some thin film transistors of a gate driver according to the related art and an exemplary embodiment of the present invention.

Hereinafter, a liquid crystal display panel according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the present specification, the same or similar components are assigned the same or similar reference numerals for different configurations, and the description thereof is replaced with the first description.

As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise.

3 is a schematic diagram of a liquid crystal display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display panel 100 according to the exemplary embodiment of the present invention is divided into a display unit 110 and a non-display unit 105. And a data driver 130 and a gate driver 120 for driving the plurality of gate lines GL and data lines DL arranged on the display unit 110. The gate driver 120 and the data driver 130 are provided. ) May be disposed inside or outside the liquid crystal display panel 100, and a timing controller 140 and a driving voltage generation circuit (not shown).

Here, the data driver 130 is formed by attaching a tape driving package (Tape Carrier Package) 135 manufactured in a package type to the liquid crystal display panel 100, and the gate driver 120 is formed on one surface of the non-display unit 105. It may be a GIP (Gate In Panel) structure formed by patterning directly. At this time, the other side of the data driving TCP 135 is formed by attaching to the PCB substrate for receiving a signal.

Although not shown in the drawing, the liquid crystal display panel 100 defines a display unit 110 and a non-display unit 105 on a first substrate and faces a second substrate (not shown). ) And a liquid crystal layer (not shown) interposed therebetween to correspond to the display unit 110.

The display unit 110 may include a plurality of image signal lines GL and DL and a plurality of unit pixels arranged in a matrix form.

Here, the image signal lines GL and DL include a plurality of gate lines GL that transfer gate voltages and data lines DL that transfer data voltages. The gate lines GL extend in the row direction and are substantially parallel to each other, and the data lines DL extend in the column direction and are substantially parallel to each other. Therefore, the liquid crystal cell includes a plurality of liquid crystal cells arranged in a matrix by the intersection structure of the data line DL and the gate line GL.

Each unit pixel includes a thin film transistor TFT connected to the image signal lines GL and DL, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. The storage capacitor Cst may be omitted as necessary.

The liquid crystal capacitor Clc has a pixel electrode of the first substrate and a common electrode of the second substrate as two terminals, and the liquid crystal layer between the two electrodes functions as a dielectric. The storage capacitor Cst is formed by overlapping a separate signal line (not shown) and a pixel electrode provided on the first substrate, and a predetermined voltage such as a common voltage Vcom is applied to the separate signal line.

The gate driver 120 is connected to the gate line GL of the liquid crystal display panel 100 so that a gate voltage formed by a combination of a gate on voltage Von and a gate off voltage Voff from the outside is applied to the gate line GL. Is authorized.

The data driver 130 is connected to the data line DL of the liquid crystal display panel 100, generates a plurality of gray voltages, selects the generated gray voltages, and applies the generated gray voltages to the unit pixels as data voltages. It consists of a circuit.

The timing controller 140 generates control signals for controlling operations of the gate driver 120 and the data driver 130, and provides the corresponding control signals to the gate driver 120 and the data driver 130.

Although not shown in the drawing, the driving voltage generation circuit generates a plurality of driving voltages.

Hereinafter, the display operation of the liquid crystal display will be described in more detail.

The timing controller 140 receives a signal for controlling the liquid crystal display panel 100 from the outside. The timing controller 140 generates a gate control signal, a data control signal, and the like based on the provided control signal, processes the gate control signal according to the operating conditions of the liquid crystal display panel 100, and then processes the gate control signal in the gate driver 120. The data signal is provided to the data driver 130.

The gate driver 120 turns on the thin film transistor TFT connected to the gate line GL by applying a gate-on voltage Von to the gate line GL according to the gate signal from the timing controller 140.

While the gate-on voltage Von is applied to one gate line GL and a row of TFTs connected thereto is turned on, the data driver 130 transfers each data voltage to the corresponding data line DL. Supply. The data voltage supplied to the data line DL is applied to the corresponding unit pixel through the turned-on thin film transistor TFT.

The liquid crystal molecules change their arrangement according to the change in the electric field generated by the pixel electrode and the common electrode, thereby changing the polarization of light passing through the liquid crystal layer. This change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the first substrate and the second substrate.

In this way, an image can be displayed for one frame and the next frame begins after one frame ends. In addition, the motion of the object can be expressed as an image in successive frames.

Herein, the shape of the thin film transistor TFT in the display unit 110 will be described in detail by looking at a plan view of a pixel serving as a unit for displaying the image.

4 is a plan view of one pixel of a liquid crystal display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the gate lines GL are arranged in a first direction, and the data lines DL are arranged in a second direction crossing the first direction.

A first thin film transistor TFT1 is formed in an area where the gate line GL and the data line DL cross each other.

The first thin film transistor TFT1 includes a first gate electrode 111, a first activation layer 113, a first source electrode 115a, and a first drain electrode 115b.

The first gate electrode 111 is branched from the gate line GL to protrude in the direction of the data line DL, and the first activation layer 113 is formed above the first gate electrode 111. And a pattern is formed below the first source electrode and the first drain electrode 115a and 115b, and the first source electrode 115a is branched from the data line DL to protrude. The drain electrode 115b is spaced apart from the first source electrode 115a at a predetermined interval.

In addition, the pixel electrode 116 is connected to the first drain electrode 115b. For this purpose, the insulating film formed on the first source electrode 115a and the first drain electrode 115b is disposed on the first drain electrode 115b. A contact hole 117 is provided to expose 115b.

Meanwhile, a storage capacitor 118 is formed on one surface of the pixel electrode 116 to maintain a voltage received by the gate line GL and the data line DL. The storage capacitor 118 is electrically connected to the pixel electrode 116 through an upper contact hole 119.

The first source electrode 115a may be formed in a concave-convex shape or a U shape including two protrusions and a groove between the protrusions. In this case, the first drain electrode 115b may have a shape in which a straight protrusion is inserted into the first source electrode 115a. The protrusion and the first drain electrode 115b of the first source electrode 115a may be formed in a direction parallel to the gate line GL.

Hereinafter, the shape of the second thin film transistor of the gate driver formed in the non-display portion will be described in detail.

5 is a plan view of a second thin film transistor of a gate driver according to an exemplary embodiment of the present invention.

The second thin film transistor TFT2 includes a second gate electrode (not shown), a second activation layer 223, a second source electrode 225a, and a second drain electrode 227a.

The second source electrode 225a may include a plurality of protrusions. The second source electrode 225a may be connected to a bridge 225b that connects the plurality of protrusions to one from one side. Alternatively, it can be seen that the second source electrode 225a has a shape in which a plurality of irregularities having protrusions and grooves are arranged in parallel.

The second drain electrode 227a may include a plurality of protrusions, and the protrusions of the second drain electrode 227a may be inserted into spaced spaces between the protrusions of the second source electrode 225a. Can be. The second drain electrode may have a shape that protrudes vertically from the center line 227b formed at the center thereof.

Meanwhile, the positions of the second source electrode 225a and the second drain electrode 227a may be changed.

The second activation layer 223 may be disposed in a predetermined region overlapping the second source electrode 225a and the second drain electrode 227a.

In this case, one giant thin film transistor may be defined based on a region where the second activation layer 223 is formed. In the figure, it can be seen that four thin film transistors are arranged symmetrically with respect to the center line 227b of the second drain electrode 227a.

When the entire shape of the gate driver is viewed in a plan view, a tree shape in which branches are extended from the center line to both sides of the gate driver may be a shape in which a plurality of concavo-convex shapes are fingered to face each side of the tree shape. have.

Meanwhile, the second source electrode 225a and the second drain electrode 227a may be formed horizontally from side to side. The formation direction may be a direction parallel to the formation direction of the gate line, assuming a plan view in which the second thin film transistor TFT2 is formed on the liquid crystal display panel. Therefore, it may be parallel to the formation direction of the first source electrode and the first drain electrode of the first thin film transistor.

Accordingly, the pattern formation uniformity of the exposure and etching processes may be improved by making the pattern formation directions of the source and drain electrodes of the first and second thin film transistors the same. As a result, it is possible to increase the margin range in the exposure process for forming the same critical dimension (CD), thereby increasing the depth of focus (DOF) margin range. When the margin range of the process is improved, a defect in which a short occurs between the source electrode and the drain electrode can be reduced, so that the process yield can be improved.

In addition, the uniformity of channel formation in the active layer of the thin film transistor is also increased by improving the pattern formation uniformity, thereby improving the uniformity of the on / off current and stabilizing the quality.

Hereinafter, a method of forming a thin film transistor according to an embodiment of the present invention by a slit exposure process will be described.

6A through 6E are cross-sectional views illustrating a method of forming a thin film transistor according to an embodiment of the present invention, in a process sequence.

Although the thin film transistor shown in the figure is shown only for the first thin film transistor, the process described below may be applied to the formation of the second thin film transistor.

Referring to FIG. 6A, aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), molybdenum (Mo), titanium (Ti), copper (Cu), and the like may be formed on a first substrate. One or more selected metals of the conductive metal group are deposited to form a first gate electrode 111 and a gate wiring (not shown), and a gate insulating layer 112 is formed thereon. In this case, the gate insulating layer 112 may be an inorganic insulating material or an organic insulating material.

Next, a pure amorphous silicon layer (a-Si: H, 113) and an amorphous silicon layer (n + or p + a-Si: H) containing impurities are formed on the entire surface of the first substrate 101 on which the gate insulating layer 112 is formed. , 114 and the conductive metal layer 115 are sequentially stacked.

The metal layer 115 is formed by depositing one or more materials selected from the aforementioned conductive metal groups.

6B, a photoresist is applied on the entire surface of the first substrate 101 on which the conductive metal layer 115 is formed.

Next, the slit mask M including the transmissive part M3, the blocking part M2, and the transflective part M1 is positioned on the spaced upper portion of the first substrate 101.

In detail, the blocking portions M2 are positioned at both sides of the pure amorphous silicon layer 113 in the center of the transflective portion M1, and then in the region where the data line (not shown) is to be formed. The blocking part (not shown) is to be located, and the transmission part is located in other areas.

In this case, the transflective portion M1 of the slit mask M forms a slit to diffract the transmitted light to weaken the intensity so that the photoresist PR is partially exposed from the surface. do.

The slit exposure process can form a finer pattern by controlling the diffraction amount of light by adjusting the number and arrangement interval of the slits, unlike the prior art that the exposure process using a halftone material. Therefore, even if the height of the vertical axis of the mask is changed, it is possible to form a uniform pattern according to the number and arrangement interval of the slit, it is possible to increase the depth of focus (DOF) margin more than the prior art.

Next, a process of exposing the lower photoresist PR by irradiating light to the upper portion of the mask M and developing the exposed portion are performed.

In this case, as shown in FIG. 6C, the portion corresponding to the first gate electrode 111 is patterned at a low height in the channel formation region. In the exposed area, all of the photoresist PR is removed, and only the unexposed portion of the photoresist PR has an original thickness.

In this case, the thickness of the photoresist PR over the channel formation region is called a half-tone range (HR), and serves as a reference for measuring the accuracy of the exposure process.

Next, referring to FIG. 6D, a process of removing the exposed conductive metal layer 115, the impurity amorphous silicon layer 114 and the pure amorphous silicon layer 113 below is performed.

In this case, the conductive metal layer 115 may be separately wet-etched and removed, and the impurities and the pure amorphous silicon layers 114 and 113 may be removed by a dry etching process. In addition, as long as the conductive metal layer 115 is a metal capable of dry etching, all of the layers 113, 114, and 115 may be simultaneously etched. The upper pot resist PR of the channel formation region may be removed by an ashing process after the etching process.

When the etching process is completed, an ohmic contact including a patterned first source, a first drain electrode 115, a first activation layer 113 composed of pure amorphous silicon layer 113, and an impurity amorphous silicon layer 114. An ohmic contact layer 114 is formed, and an upper portion of the channel forming region of the first activation layer 113 is exposed.

6E, the protective film 200 is formed by removing the photoresist PR and depositing an inorganic insulating material or an organic insulating material on the entire surface of the first substrate 101.

Here, using the table, how much the depth of focus (DOF) margin increases when the liquid crystal display panel according to the exemplary embodiment of the present invention is manufactured by using the slit exposure process, is prepared.

division
(First evaluation)
Mask form TFT threshold minimum Display TFT Pattern Formation Direction Gate driver TFT pattern formation direction Depth of Focus (DOF) Margin
Prior Art 1 Halftone mask
(Using semi-permeable material) 5.5μm
More than
level
Perpendicular
25 μm Prior Art 2 Slit mask 4.5 ~
4.8μm level Perpendicular 30 μm One embodiment of the present invention Slit mask 4.5 ~
4.8μm level level 40 μm

division
(Second evaluation)
Mask form TFT threshold minimum Display TFT Pattern Formation Direction Gate driver TFT pattern formation direction Depth of Focus (DOF) Margin Prior Art 2 Slit mask 4.5 ~
4.8μm level Perpendicular 50 μm One embodiment of the present invention Slit mask 4.5 ~
4.8μm level level 60 μm

In Tables 1 and 2, the minimum threshold value of the TFT channel refers to the minimum threshold value of the active layer that can be exposed between the source electrode and the drain electrode in the thin film transistor. In addition, the TFT pattern formation direction refers to a direction in which protrusions and protrusions of an uneven shape look in each thin film transistor, and horizontal and vertical lines are based on gate lines.

And since Table 1 and Table 2 were evaluated for the process under different conditions, respectively, the depth of focus margin of the prior art and the embodiment of the present invention was measured differently.

First, compare the prior art 1 and the prior art 2 of Table 1. When using the halftone mask and the slit mask in Table 1, the difference in the depth of focus (DOF) margin occurs by 5 μm. It can be seen that only the slit exposure process provides a greater depth of focus (DOF) margin than the conventional halftone mask process using a semi-transparent material.

Next, Table 1 compares the prior art 2 and one embodiment of the present invention. Referring to Table 1, an embodiment of the present invention has a depth of focus (DOF) margin of 10 μm higher than that of the prior art. In addition, it has a depth of focus (DOF) margin of 15 μm or higher compared to the prior art 1.

And when comparing Table 1 and Table 2, even if the measurement of the depth of focus (DOF) margin of the embodiment of the present invention is different, the depth of focus (DOF) margin than the prior art 2 has a uniformly larger value by 10μm Can be.

Therefore, the depth of focus (DOF) margin can be increased by making the thin film transistor channel forming direction parallel to the display unit and the gate driver.

Therefore, the DOF margin can be improved through the slit exposure process and the transistor pattern direction matching of the gate driver and the display unit.

Wherein Table 2 is analyzed in more detail through a graph.

7A and 7B are graphs showing the relationship between the focal length and the halftone range for the prior art 2 and the embodiment of the present invention, respectively.

The halftone range refers to the thickness of the photoresist on the channel formation region shown in Fig. 6C, and the focal length refers to the focal length between the mask and the lens emitting light. 7A and 7B, it can be seen that a plurality of parabolas are distributed, which is because a plurality of experiments are performed to show a plurality of results.

Based on the Grafton specific product specification, it was assumed that the halftone range should be 4000 kHz or less in order to form the same critical pattern on the first substrate. That is, if the photoresist thickness of 4000 kPa or less can be formed by the exposure process, the same critical value pattern can be formed in the subsequent etching process.

In comparison with the drawings, in Fig. 7A, the focal length range of 4000 m or less for all parabolas is approximately 50 m. This is the depth of focus margin of the prior art 2.

In addition, in FIG. 7B, the focal length range satisfies 4000 μs or less for all parabolas is about 60 μm. This is the depth of focus (DOF) margin of one embodiment of the present invention.

In addition, the parabola of FIG. 7B is more smoothly formed on the left and right axes than the parabola of FIG. 7A, and more parabola having a wider depth of focus for 4000 보다 than FIG. 7A.

Accordingly, it can be seen that one embodiment of the present invention provides a larger depth of focus (DOF) margin than that of the related art.

On the other hand, an embodiment of the present invention can reduce the width of the gate driver compared to the prior art bar will be described in more detail.

8 is a plan view illustrating some thin film transistors of a gate driver according to the related art and an exemplary embodiment of the present invention.

The thin film transistor shown in FIG. 8 corresponds to the horizontal width of the gate driver.

Here, the channel length and channel width of the thin film transistor have a great influence on the characteristics of the thin film transistor. The channel length refers to an interval between the source electrode and the drain electrode, and the channel width corresponds to the spaced interval between the thin film transistors. Refers to a zigzag-shaped path to form.

8, an embodiment of the present invention provides a gate driver having a horizontal width d smaller than that of the related art.

This is because the channel width of the prior art and the channel width of the embodiment of the present invention are the same.

Accordingly, an embodiment of the present invention can provide a liquid crystal display panel having a reduced horizontal size by narrowing the horizontal width of the gate driver.

Until now, in the exemplary embodiment of the present invention, only the thin film transistor pattern forming directions of the gate driver and the display unit are formed in a direction parallel to the gate line, but if the thin film transistors have the same pattern forming direction, they are all perpendicular to the gate line. In any case, the present invention may be included as one embodiment of the present invention.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Therefore, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also within the scope of the present invention.

100: liquid crystal display panel 105: non-display portion
110: display unit 120: gate driver
130: data driver 135: TCP
140: timing control DL: data line
GL: Gate Line TFT: Thin Film Transistor
113: first activation layer 223: second activation layer
115a: First source electrode 225a, 225b: Second source electrode
115b: First drain electrode 227a, 227b: Second drain electrode

Claims (7)

A first substrate divided into a non-display unit including a display unit and a gate driver;
A plurality of data lines and a plurality of gate lines formed on the display unit of the first substrate and crossing each other to define a plurality of pixels;
A second substrate facing the first substrate;
A liquid crystal layer interposed between the first substrate and the second substrate;
A first thin film transistor formed at each pixel of the display unit and including a first source electrode having a concave-convex shape protruding in one direction from the data line and a first drain electrode inserted into the concave-convex shape; ; And
And a second source electrode and a second drain electrode formed in an uneven shape in the gate driving part, and the uneven shapes of the second source electrode and the second drain electrode face each other so that the groove and the protrusion are engaged with each other. It includes; a second thin film transistor,
The liquid crystal display panel according to claim 1, wherein the direction toward which the uneven protrusions of the first transistor and the second transistor face each other is parallel. The method of claim 1,
And the direction toward which the protrusions and protrusions of the concave-convex shape face is horizontal or perpendicular to the gate line. The method of claim 1,
And the first thin film transistor and the second thin film transistor are formed by an exposure process using a slit mask. The method of claim 1,
And a data driving TCP including a data driver on the other side of the first substrate on which the gate driver is not configured. The method of claim 1,
The pattern formed on the same layer including the second source electrode and the second drain electrode of the second thin film transistor may be formed in a tree shape including a plurality of branches on both sides of one center line. A liquid crystal display panel having a shape in which concave-convex shapes face each other in a tree shape. The method of claim 5, wherein
And the plurality of branches protrude perpendicularly to the center line and the protruding direction is parallel to the gate line. The method according to claim 6,
Wherein the uneven shape and the tree shape are formed in a fingering shape in which the branch is inserted into a groove of the uneven shape.

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