KR20080043446A - Thin film transistor substrate and method of fabricating the same - Google Patents

Abstract

A thin film transistor substrate and a method of manufacturing the same are provided to make the area between a drain electrode and a gate electrode uniform so as to prevent a parasitic capacitance variation. A thin film transistor includes a gate electrode(3) having a first hole(19), a gate insulating layer insulating the gate electrode, an active layer(11) superposed on the gate electrode having the gate insulating layer interposed between the gate electrode and the active layer, a source electrode(5) electrically connected to a data line(7), and a drain electrode(9) opposite to the source electrode. The active layer has a second hole(25) corresponding to the first hole of the gate electrode. The source electrode is formed apart from the second hole. One end of the drain electrode is formed in the second hole.

Description

Thin Film Transistor Substrate and Manufacturing Method Thereof {THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME}

1 is a view showing a conventional thin film transistor.

2 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention.

3 is a cross-sectional view illustrating a cross section taken along line II ′ of the thin film transistor substrate illustrated in FIG. 2.

4A through 4E are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, for each mask process.

<Description of the symbols for the main parts of the drawings>

1: gate line 3: gate electrode

5: source electrode 7: data line

9: drain electrode 11: active layer

13: first gate insulating film 15: pixel electrode

17: contact hole 19: first hole

21: shield 25: the second hole

30 substrate 33 second gate insulating film

35: ohmic contact layer 43: gate insulating film

The present invention relates to a thin film transistor substrate and a method for manufacturing the same, and more particularly, to a thin film transistor substrate and a method for manufacturing the same that can minimize image quality defects.

A liquid crystal display (LCD) displays an image by allowing liquid crystal cells (Clcs) arranged in a matrix on a liquid crystal panel to adjust light transmittance according to video signals, respectively.

The liquid crystal cell Clc is formed such that a pixel electrode connected to the thin film transistor TFT and a common electrode formed on the upper substrate face each other with a liquid crystal interposed therebetween. The liquid crystal molecules having dielectric anisotropy are rotated according to the voltage charged in the liquid crystal cell Clc, thereby controlling grayscale.

The thin film transistor includes an active layer forming a gate electrode and a channel as part of a gate line, a source electrode and a drain electrode as a part of a data line, a gate insulating layer, and the like, and through a data line according to a scan signal transmitted through the gate line. A switching element that transfers or blocks a transmitted image signal to a pixel electrode.

In general, in the case of the thin film transistor, due to the process margin of the photolithography process, the overlap between the gate electrode and the drain electrode constituting the thin film transistor is inevitable. The gate electrode and the drain electrode form a parasitic capacitor with a gate insulating film interposed therebetween. Therefore, due to a process error such as an alignment error of a photo mask when forming the drain electrode, a change in capacitance of the parasitic capacitor formed by overlapping the gate electrode and the drain electrode occurs. In order to reduce the capacitance change of the parasitic capacitor, a structure in which the drain electrode 110 between the source electrode 140 passes through the gate electrode 130 formed in the gate line 100 is used, as shown in FIG. 1. Therefore, since the tip portion of the drain electrode generated by passing the error of the mask process through the gate electrode 120 is within the error range, there is no change in capacitance of the parasitic capacitor. However, since the structure is thin because there is no active layer 130 at the stepped portions of the gate electrode 120 and the drain electrode 110, the voltage of the electrode wiring is concentrated when driving the thin film transistor, which causes local degradation of the gate insulating film. Has the disadvantage of happening quickly. These factors act collectively, resulting in a markedly high reliability-related image quality defect, such as color defect.

Accordingly, an object of the present invention is to provide a thin film transistor which minimizes the number of gate step portions where the source electrode and the drain electrode overlap with the gate electrode and does not have a variation in capacitance of the parasitic capacitor.

According to an aspect of the present invention, a gate electrode having a first hole and a gate insulating film insulating the gate electrode on the gate electrode and the gate insulating film are overlapped with the gate electrode, A thin film including an active layer having a correspondingly formed second hole, a source electrode electrically connected to a data line, a source electrode spaced apart from the second hole, and a drain electrode facing one side of the source electrode and having one end disposed in the second hole; Provide a transistor.

In addition, the source electrode may be formed in a 'U' shape.

In order to solve another technical problem, a gate line and a data line intersecting each other and being electrically connected to the gate line and insulating the gate electrode on the gate electrode and the gate electrode having a first hole are formed. An active layer having a second hole formed to overlap the gate electrode with a gate insulating layer and the gate insulating layer interposed therebetween, and a source electrode electrically connected to the data line and spaced apart from the second hole. And a thin film transistor substrate formed by partially overlapping a tip of a drain electrode formed to face the source electrode and an interior of the first and second holes.

The gate insulating film may include a first gate insulating film formed on the gate electrode and the substrate and a second gate insulating film formed on the first gate insulating film.

In addition, the first gate insulating film and the second insulating film are preferably formed by discontinuous deposition of SiNx or SiOx.

The present invention also provides a method for forming a gate line and a data line on a substrate, forming a gate electrode protruding from the gate line, and forming a gate insulating film on the gate line and the gate electrode. Forming an active layer and an ohmic contact layer on the gate insulating layer by overlapping with the gate electrode, a source electrode electrically connected to the data line on the ohmic contact layer, and having a 'U' shape; Forming a thin film transistor including forming a drain electrode formed in a straight line inside the electrode; forming a protective film having a gate insulating film and a contact hole exposing the drain electrode on the thin film transistor; Electrically open with drain electrode It provides a method for manufacturing a thin film transistor substrate comprising the step of forming a pixel electrode to be connected.

And forming a first hole in the gate electrode in the forming of the gate electrode.

The method may include forming a second hole in the active layer in the forming of the active layer.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along a line II ′ of the thin film transistor substrate of FIG. 1.

2 and 3, the thin film transistor substrate according to the present invention may be electrically connected to the gate line 1 and the data line 7 and the gate line 1, which cross each other to define a pixel area. A gate electrode 3 having one hole 19 formed therein, a gate insulating film 43 for insulating the gate electrode 3 on the gate electrode 3, and the gate electrode 3 with the gate insulating film 43 interposed therebetween. ) And an active layer 11 having a second hole 25 formed corresponding to the first hole 19, electrically connected to the data line 7, and spaced apart from the second hole 25. The formed source electrode 5 includes a drain electrode 9 formed at one side of the second hole 25 facing the source electrode 5.

Specifically, the thin film transistor TFT is formed of a transparent insulating material such as glass or plastic. The gate line 1 and the data line 7 intersect the substrate 30 with the gate insulating film 43 interposed therebetween.

The gate line 1 is formed of a single metal or an alloy of an opaque metal, for example, gold, silver, copper, aluminum, molybdenum, chromium or the like, or a single layer or two or more layers on the substrate 30. The gate line 1 supplies the gate on voltage and gate off voltage from the gate driving circuit (not shown) to the gate electrode 3 of the thin film transistor TFT.

The data line 7 is formed on the gate insulating film 43 in a single layer or more than a single layer of an opaque metal such as gold, silver, copper, aluminum, molybdenum, or a single metal or an alloy thereof. The data line 7 supplies the pixel data voltage supplied from the data driving circuit (not shown) to the thin film transistor TFT whenever the gate-on voltage is supplied to the gate line 1.

The thin film transistor TFT is turned on by the gate-on voltage supplied from the gate line 1 to supply the pixel data voltage supplied from the data line 7 to the pixel electrode 15. The thin film transistor TFT includes a gate electrode 3 having a first hole 19 formed therebetween, a gate insulating film 43 that insulates the gate electrode 3 on the gate electrode 3, and a gate insulating film 43 therebetween. An active layer 11 having a second hole 25 formed to correspond to the first hole 19 and electrically connected to the data line 7, and overlapping the gate electrode 3. A source electrode 5 formed spaced apart from the 25 and a source electrode 5 facing the source electrode 5 includes a drain electrode 9 formed at one end of the second hole 25.

The gate electrode 3 protrudes from the gate line 1 and is in electrical contact with the gate line 1. The first hole 19 is formed in the gate electrode 3.

The gate insulating film 43 includes a first gate insulating film 13 and a second gate insulating film 33.

The first gate insulating layer 13 is stacked on the substrate 30 and the gate electrode 3 to form an interface with the gate electrode 3. The first gate insulating film 13 is made of a material having good insulation other than oxide, such as SiNx or SiOx.

The second gate insulating film 33 is formed on the first gate insulating film 13 and forms an interface with both the first gate insulating film 13 and the active layer 11. The second gate insulating film 33 is also formed of SiNx and SiOx. The gate insulating film 43 is formed by discontinuous deposition on the entire region of the substrate 30 on which the gate line 1 and the gate electrode 3 are formed as the inorganic insulating film. The gate insulating layer 43 prevents the gate line 1 and the gate electrode 3 from being directly electrically connected to other signal lines or electrodes.

The active layer 11 overlaps with the gate electrode 3 and is formed in an island shape on the gate insulating layer 43. The second hole 25 is formed in the active layer 11 at a position corresponding to the first hole 19. On the other hand, an active layer 11 is further formed between the gate line 1 and the data line 7 at the overlapping portion of the gate line 1 and the data line 7. The active layer 11 is formed of amorphous silicon (a-Si) and forms a channel of the thin film transistor TFT. An ohmic contact layer 35 is further provided between the active layer 11, the source electrode 5, and the drain electrode 9, for ohmic contact, which is separated on both sides of the gate electrode 3. The ohmic contact layer 35 is formed of amorphous silicon (n + a-Si) doped with impurities. The ohmic contact layer 35 forms an interface with the active layer 11 and has the same shape as the active layer 11.

The source electrode 5 overlaps the active layer 11 and is formed in a 'U' shape on the ohmic contact layer 35. The source electrode 5 is in electrical contact with the data line 7 to supply the pixel data voltage supplied from the data line 7 to the drain electrode 9. This source electrode 5 is formed on the same plane with the same metal as the data line 7.

The drain electrode 9 overlaps the active layer 11 and is formed in a linear shape on the ohmic contact layer 35, and is formed to face the inside of the 'U'-shaped source electrode 5. In addition, it is formed inside the second hole 25 and extends to the contact hole 17 of the pixel electrode 15. This drain electrode 9 is formed on the same plane with the same metal as the data line 7 and the source electrode 5.

The pixel electrode 15 is formed on the passivation layer 21 covering the thin film transistor TFT and is electrically connected to the drain electrode 9 through a contact hole 17 penetrating the passivation layer 21. Here, the inorganic insulating material such as SiNx, SiOx, or the like as the gate insulating film 43 may be used for the protective film 21, or an organic insulating material may be used. The contact hole 17 is preferably formed in the drain electrode surface in such a size as to expose the drain electrode 9. In particular, when an organic insulating material is used as the passivation layer 21, it is possible to prevent a step from occurring in the pixel electrode 15 formed in the pixel region. The pixel electrode 15 is formed of a transparent conductive metal such as indium tin oxide (ITO) or indium zinc oxide (IZO).

4A through 4E are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, for each mask process.

4A to 4E illustrate the five mask processes, respectively. However, the thin film transistor substrate according to the embodiment of the present invention may be manufactured by three or four mask processes.

4A is a cross-sectional view illustrating a first mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, a first conductive pattern including a gate line 1 and a gate electrode 3 is formed on a substrate through a first mask process.

Specifically, the first conductive layer is formed on the substrate 30 through a deposition method such as sputtering. Here, the first conductive layer is formed of a metal material such as gold, silver, copper, aluminum, chromium, molybdenum or the like or a metal material made of an alloy thereof as a single layer or formed in two or more layers. Subsequently, a first conductive pattern including the first hole 19, the gate line 1, and the gate electrode 3 is formed by patterning the first conductive layer by a photolithography process and an etching process using the first mask.

4B is a cross-sectional view illustrating a second mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 4B, the second hole 25, the gate insulating layer 43, the active layer 11, and the ohmic contact layer 35 are formed on the substrate 30 on which the first conductive pattern is formed through the second mask process. do.

Specifically, the first and second gate insulating layers 13 and 33 are double deposited on the substrate 30 on which the gate line 1 and the gate electrode 3 are formed, and the amorphous silicon layer and the amorphous silicon layer doped with impurities are plasma. Deposition is carried out sequentially through a deposition method such as Plasma Enhanced Chemical Vopor Deposotion (hereinafter referred to as "PECVD") or Chemical Vopor Deposiotion (CVD). Subsequently, the second silicon layer 25, the active layer 11, and the ohmic contact layer 35 are formed by patterning the amorphous silicon layer and the amorphous silicon layer doped with impurities using a photolithography process and an etching process using a second mask. At this time, an inorganic insulating material such as SiNx or SiOx is used as the gate insulating film 43.

4C is a cross-sectional view illustrating a third mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 4C, the data line 7, the source electrode 5, and the drain electrode 9 are formed on the gate insulating layer 43 on which the active layer 11 and the ohmic contact layer 35 are formed through a third mask process. A second conductive pattern is formed.

Specifically, the data line 7 is formed to cross the gate line 1 perpendicularly, and the source electrode 5 is formed in a 'U' shape on the ohmic contact layer 35 on which the active layer 11 is formed. The second conductive pattern is formed by forming a second conductive layer through a deposition method such as sputtering, and then patterning the second conductive layer by photolithography and etching using a third mask process. Here, a slit mask or a semi-transmissive mask is used for the region forming the channel portion of the third mask. Accordingly, the source electrode 5 and the drain electrode 9 may be finely formed to form a thin film transistor TFT having a small size. As the second conductive layer, a metal or an alloy such as gold, silver, copper, aluminum, molybdenum, chromium, or the like is formed in a single layer or a multi-layer structure composed of a combination thereof.

4D is a cross-sectional view illustrating a fourth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 4D, the second conductive pattern is formed through the fourth mask process to form the passivation layer 21 having the contact hole 17 on the gate insulating layer 43.

Specifically, the passivation layer 21 is formed on the substrate on which the second conductive pattern is formed by a deposition method such as PECVD or CVD, and passes through the passivation layer 21 by a photolithography process and an etching process using a fourth mask. The contact hole 17 exposing) is formed. An inorganic insulating material such as the gate insulating film 43 is used as the passivation layer 21, or an organic insulating material having no step difference is used.

4E is a cross-sectional view illustrating a fifth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 4E, the pixel electrode 15 is formed on the passivation layer through a fifth mask process.

Specifically, the pixel electrode 15 is formed by patterning the transparent conductive layer on the protective film through a deposition method such as sputtering. Then, the transparent conductive layer is patterned by a photolithography process and an etching process using a fifth mask. In this case, the pixel electrode 15 is connected to the drain electrode 9 of the thin film transistor TFT through the contact hole 17. As the transparent conductive layer, a transparent conductive material such as indium tin oxide (TO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or the like is used.

Meanwhile, the manufacturing method of the thin film transistor substrate according to the embodiment of the present invention may be formed by a four mask process. That is, the second mask process and the third mask process may be manufactured using one mask.

In detail, a gate insulating layer 30, an amorphous silicon layer, an amorphous silicon layer doped with impurities, and a second conductive layer are formed on the substrate 30 on which the first conductive pattern is formed. Next, an impurity doped amorphous portion of a portion in which a channel region between the data line 7, the source electrode 5, and the drain electrode 9 is to be formed is formed through the photolithography process and the etching process using the mask. Etch the silicon layer. At this time, the amorphous silicon layer and the impurity doped amorphous silicon layer of the remaining region where the signal line is not formed are etched. Thereafter, the passivation layer 21 and the pixel electrode 15 are formed.

As described above, the thin film transistor substrate and the method of manufacturing the same according to the present invention can form a structure to prevent the parasitic capacitor capacitance variation because there is no change in the area between the drain electrode and the gate electrode.

In addition, by minimizing the number of gate stepped portions where the source electrode and the drain electrode overlap, the deterioration of the gate insulating layer is reduced to prevent color defects.

In the detailed description of the invention described above with reference to the preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge of the present invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the spirit and scope of the art.

Claims (10)

A gate electrode having a first hole formed therein; A gate insulating film insulating the gate electrode on the gate electrode; An active layer overlapping the gate electrode with the gate insulating layer interposed therebetween and having a second hole formed to correspond to the first hole; A source electrode electrically connected to a data line and spaced apart from the second hole; And a drain electrode facing one of the source electrodes and having one end thereof formed in the second hole. The method of claim 1, The source electrode is a thin film transistor, characterized in that formed in the 'U' shape. A gate line and a data line crossing each other to define a pixel area; A gate electrode electrically connected to the gate line and having a first hole formed therein; A gate insulating film insulating the gate electrode on the gate electrode; An active layer overlapping the gate electrode with the gate insulating layer interposed therebetween and having a second hole formed to correspond to the first hole; A source electrode electrically connected to the data line and spaced apart from the second hole; The thin film transistor substrate of claim 1, wherein a tip of the drain electrode formed to face the source electrode and the inside of the first and second holes partially overlap each other. The method of claim 3, wherein The source electrode is a thin film transistor substrate, characterized in that formed in the 'U' shape. The method of claim 4, wherein And a active layer formed on an overlapping portion of the gate line and the data line. The method of claim 5, wherein The gate insulating film A first gate insulating layer formed on the gate electrode and the substrate; And And a second gate insulating film formed on the first gate insulating film. The method of claim 6, The thin film transistor substrate of claim 1, wherein the first gate insulating film and the second gate insulating film are formed by discontinuous deposition of SiNx or SiOx. Forming a gate line and a data line over the substrate; Forming a gate electrode protruding from the gate line; Forming a gate insulating film on the gate line and the gate electrode; Overlapping the gate electrode to form an active layer and an ohmic contact layer on the gate insulating layer; Forming a thin film transistor on the ohmic contact layer, the source electrode being electrically connected to the data line and having a 'U' shape, and a drain electrode having a linear shape inside the source electrode; Forming a protective film having a contact hole exposing the drain electrode on the gate insulating film and the thin film transistor; And Forming a pixel electrode electrically connected to the drain electrode on the passivation layer. The method of claim 8, In the forming of the gate electrode Forming a first hole in the gate electrode; The method of claim 8, In the forming of the active layer Forming a second hole in the active layer;

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