KR20130030039A - Semiconductor package - Google Patents

Semiconductor package Download PDF

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Publication number
KR20130030039A
KR20130030039A KR1020110093543A KR20110093543A KR20130030039A KR 20130030039 A KR20130030039 A KR 20130030039A KR 1020110093543 A KR1020110093543 A KR 1020110093543A KR 20110093543 A KR20110093543 A KR 20110093543A KR 20130030039 A KR20130030039 A KR 20130030039A
Authority
KR
South Korea
Prior art keywords
base substrate
semiconductor package
layer
semiconductor chip
connection pad
Prior art date
Application number
KR1020110093543A
Other languages
Korean (ko)
Inventor
이동욱
노승현
Original Assignee
삼성전기주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전기주식회사 filed Critical 삼성전기주식회사
Priority to KR1020110093543A priority Critical patent/KR20130030039A/en
Publication of KR20130030039A publication Critical patent/KR20130030039A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A semiconductor package is provided to improve the structural stability and reliability of a semiconductor package by using an underfill resin layer. CONSTITUTION: An outer circuit layer is formed in a base substrate and includes a connection pad(115) and a circuit pattern(117). A solder resist layer(120) is formed on the base substrate. The solder resist layer has an opening part for exposing a part of the circuit pattern. A semiconductor chip(130) is formed on the base substrate. An underfill resin layer(140) is formed between the base substrate and the semiconductor chip.

Description

Semiconductor Package {Semiconductor package}

The present invention relates to a semiconductor package.

As IT-based electronic products develop, technology development of components is very important. Among the components, the printed circuit board (PCB) is a component that is applied to all electronic products, and its role is becoming more important.

In particular, the recent rapid development of mobile products, and the resulting parts are also rapidly made due to technological changes.

In the case of an application processor that functions as a CPU of a mobile device, a flip-chip bonding technology is used to connect a semiconductor chip and a printed circuit board, and due to high functionality and high density, Miniaturization of printed circuit boards is required.

On the other hand, a semiconductor package according to the prior art is disclosed in Korea Patent Publication No. 2001-0073452.

The semiconductor package according to the related art has a problem in that a distance between the semiconductor chip and the substrate becomes smaller after flip-chip bonding due to the miniaturization of the bump pitch.

As the separation distance between the semiconductor chip and the substrate becomes smaller, voids are formed in the resin layer during the process of forming an under-fill resin layer between the semiconductor chip and the substrate after flip-chip bonding. void) occurs.

As described above, there is a problem in that voids are generated in the underfill resin layer, which can greatly affect the reliability of the semiconductor package.

The present invention is to solve the above-mentioned problems of the prior art, an aspect of the present invention is to facilitate the flow of the underfill liquid injected between the semiconductor chip and the substrate to form a semiconductor package having a void-free underfill resin layer To provide.

In addition, another aspect of the present invention is to provide a semiconductor package having a structure capable of preventing underfill liquid overflow without forming a separate prevention dam.

According to an embodiment of the present invention, a semiconductor package includes a base substrate having an outer circuit layer including a connection pad and a circuit pattern formed on at least one surface of one surface or the other surface, and formed on the base substrate, wherein the connection pad includes the connection pad. A solder resist layer having an opening for exposing a portion of the circuit pattern and a semiconductor chip mounted on the base substrate.

In addition, the semiconductor substrate may further include an under-fill resin layer formed between the base substrate and the semiconductor chip.

Here, the underfill resin may be an epoxy resin, a polyimide system, a polyester system, a polyacrylate system, or a polymer resin mixed therewith.

The surface treatment layer may further include a surface treatment layer formed on the exposed connection pads and the circuit patterns.

Herein, the surface treatment layer may include an electrolytic gold plating layer, an electroless gold plating layer, an organic solderability preservative layer, an electroless tin plating layer, and an electroless silver plating layer. It may be an Immersion Silver Plating layer, an Electroless Nickel and Immersion Gold (ENIG) layer or a Direct Immersion Gold Plating layer.

In addition, the base substrate may include a plurality of insulating layers and a plurality of circuit layers formed between the plurality of insulating layers.

In addition, the connection pad and the circuit pattern may be formed of an electroless plating layer, an electrolytic plating layer, or a combination thereof.

The semiconductor device may further include a sealing member formed to cover the semiconductor chip on the base substrate.

In this case, the sealing member may be an epoxy molded compound.

The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

Prior to this, the terms or words used in this specification and claims are not to be interpreted in a conventional and dictionary sense, and the inventors may appropriately define the concept of terms in order to best explain their invention in the best way possible. It should be interpreted as meaning and concept corresponding to the technical idea of the present invention based on the principle that the present invention.

The present invention forms a solder resist layer having an opening for exposing a part of a circuit pattern, including a connection pad on which a semiconductor chip is mounted, thereby increasing the separation distance between the substrate and the semiconductor chip, thereby injecting underfill. Since the flow of the smooth, there is an effect that can prevent the void (void) is formed in the underfill resin layer.

In addition, the present invention has the effect of improving the structural stability and reliability of the semiconductor package by forming a void-free under-fill resin layer as described above.

In addition, the present invention has an effect of preventing the under-fill liquid injected between the substrate and the semiconductor chip from flowing over the substrate by the stepped portions on both side surfaces of the opening formed in the solder resist layer.

1 is a cross-sectional view illustrating a structure of a semiconductor package according to an embodiment of the present invention.
2 is a view showing a flow state of an under-fill liquid injected between a substrate and a semiconductor chip in a semiconductor package according to an embodiment of the present invention.
3 is a plan view illustrating a state where a solder resist layer is formed on a printed circuit board of a semiconductor package according to an exemplary embodiment of the present disclosure.

The objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and embodiments associated with the accompanying drawings. In the present specification, in adding reference numerals to the components of each drawing, it should be noted that the same components as much as possible even if displayed on different drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In this specification, the terms first, second, etc. are used to distinguish one element from another, and the element is not limited by the terms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a structure of a semiconductor package according to an embodiment of the present invention, and FIG. 2 is a flow of an under-fill liquid injected between a substrate and a semiconductor chip in a semiconductor package according to an embodiment of the present invention. 3 is a plan view illustrating a state in which a solder resist layer is formed on a printed circuit board of a semiconductor package according to an exemplary embodiment of the present disclosure.

Although the drawings omit schematically and omit other detailed components of the semiconductor package except for the features of the embodiments, those skilled in the art are not particularly limited and fully recognize that the present invention can be applied to all semiconductor package structures known in the art. You can do it.

Referring to FIG. 1, a semiconductor package 100 according to an embodiment of the present invention includes a base substrate 110, a solder resist layer 120 formed on the base substrate 110, and a semiconductor chip 130.

The base substrate 110 may be a printed circuit board as a circuit board on which one or more circuit patterns including the connection pads 115 are formed on the insulating layer.

In the present embodiment, the base substrate 110 may include a plurality of insulating layers and a plurality of circuit layers formed between the plurality of insulating layers.

For example, in FIG. 1, the base substrate 110 is illustrated as a four-layer substrate, but may be a single layer substrate composed of one layer or a multilayer substrate having five or more layers.

A resin insulating layer may be used as the insulating layer.

As the resin insulating layer, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin impregnated with a reinforcing material such as glass fiber or an inorganic filler, for example, prepreg may be used. In addition, a thermosetting resin and / or a photocurable resin may be used, but is not particularly limited thereto.

A solder bump may be formed on the connection pad 115 as an external connection terminal through a subsequent process, and the semiconductor chip or an external component may be electrically connected to the inner layer circuit through the formed solder bump.

In the present embodiment, a circuit including the connection pad 115 and the circuit pattern 117 can be applied without limitation as long as it is used as a conductive metal for circuits in the circuit board field, and copper is typically used in a printed circuit board. .

In addition, in the present embodiment, the circuit may further include a via 119 for connecting the circuit pattern 117 of each layer.

In addition, in the present embodiment, the circuit may be formed of an electrolytic plating layer, an electroless plating layer, or a combination thereof.

Here, the method of forming the electrolytic plating layer, the electroless plating layer is already known in the art, so the detailed description thereof will be omitted.

The solder resist layer 120 functions as a protective layer that protects the outermost layer circuit and is formed for electrical insulation. In general, the solder resist layer 120 includes solder resists having openings (not shown) for exposing connection pads of the outermost layer of the substrate. Layers can be formed.

That is, in the related art, after the solder resist layer 120 is formed on the outermost layer of the base substrate 110, the connection pad 115 corresponding to the portion where the semiconductor chip is to be mounted or the connection pad corresponding to the portion to be connected to the external device is provided. An opening for exposing only 115 is formed.

However, in the present embodiment, as shown in FIGS. 1 to 3, the opening 125 exposing up to the adjacent circuit pattern 117 including the connection pad 115 formed on the outermost layer of the base substrate 110 is exposed. A solder resist layer 120 is formed.

That is, not only the connection pad 115 formed on the outermost layer of the base substrate 110 to be connected to the semiconductor chip 130 or an external device, but also a circuit pattern 117 to be covered and protected by the solder resist layer 120. The opening 125 is formed to be larger than the conventional one so as to expose a portion of the opening to the outside.

In this case, a surface treatment layer (not shown) may be further formed on the exposed connection pad 115 and the circuit pattern 117 to prevent oxidation and contamination before subsequent processes.

The surface treatment layer (not shown) is not particularly limited as long as it is known in the art, for example, electrolytic nickel and gold plating, ENIG (Electroless Nickel Immersion Gold), ENAG (Electroless Nickel Autocatalytic Gold), It may be formed through at least one of ENEPIG (Electroless Nickel Electroless Palladium Inmmersion Gold) method, ENPIG (Electroless Nickel Immersion Palladium Immersion Gold) method, Electroless Tin Plating method, OSP (Organic Solderability Preservative) method. .

In this case, except for the connection pad 115, the general circuit patterns 117 exposed to the outside may be underfill formed between the base substrate 110 and the semiconductor chip 130 by a subsequent process as shown in FIG. 1. under-fill) may be protected from the outside by the resin layer 140.

3 is a plan view of the base substrate 110 of the semiconductor package according to the present embodiment as viewed from above.

Referring to FIG. 3, a C4 region, which is a mounting region of the semiconductor chip 130, is formed on the base substrate 110, and a connection pad 115 is formed in the C4 region to be bonded to bumps (not shown) of the semiconductor chip 130. It is.

In addition, a circuit pattern 117 is formed adjacent to the C4 region, which is the mounting region of the semiconductor chip 130.

In the present exemplary embodiment, not only the connection pad 115 to which bumps (not shown) of the semiconductor chip 130 are bonded to the solder resist layer 120, but also the circuit pattern 117 formed adjacent to the connection pad 115 is exposed. The opening 125 may be formed.

As such, the solder resist layer 120 having the openings 125 exposing not only the connection pad 115 but also the circuit pattern 117 formed adjacent to the connection pad 115 is formed to form the semiconductor chip 130 and the base substrate. The area of the solder resist layer 120 formed between the 110 may be reduced.

Accordingly, after the semiconductor chip 130 is mounted through a subsequent process as shown in FIG. 2, the separation distance between the mounted semiconductor chip 130 and the base substrate 110 is greater than when the solder resist layer 120 exists therebetween. Everything can increase enough.

Therefore, as shown in FIG. 2, when the liquid under-fill resin is injected in the direction of the arrow between the base substrate 110 and the semiconductor chip 130, the semiconductor chip 130 and the base substrate, which are sufficiently increased, are increased. Due to the separation distance between the 110 it is possible to keep the flow rate in the opposite direction to the injection direction of the under-fill resin.

That is, it is possible to smoothly flow the under-fill resin in the opposite direction in which the liquid under-fill resin is injected.

As such, by smoothing the flow of the under-fill resin, it is possible to prevent the generation of voids in the under-fill resin filled between the base substrate 110 and the semiconductor chip 130. Can be.

1 and 3, in the present exemplary embodiment, the opening 125 formed to expose not only the connection pad 115 but also the circuit pattern 117 formed adjacent to the connection pad 115 has a semiconductor chip 130. The dam may be located outside the C4 region, which is a mounting region, to prevent under-fill liquid injected between the base substrate 110 and the semiconductor chip 130.

That is, as shown in Figure 1, the liquid under-fill resin injected between the semiconductor chip 130 and the base substrate 110 by both sides of the opening 125 of the solder resist layer 120 It is possible to prevent the phenomenon flowing over the base substrate 110.

Here, the underfill resin may be an epoxy resin, a polyimide, a polyester, a polyacrylate, or a polymer resin mixed therewith, but is not particularly limited thereto.

In addition, the semiconductor chip 130 is mounted on the base substrate 110 as shown in FIG. 1, and further includes a sealing member (not shown) formed on the base substrate 110 to cover the mounted semiconductor chip 130. can do.

Here, the sealing member (not shown) may be an epoxy molded compound (EMC), but is not particularly limited thereto.

Although the present invention has been described in detail through specific embodiments of the present invention, this is for describing the present invention in detail and the semiconductor package according to the present invention is not limited thereto. It is apparent that the modification and improvement are possible by the ruler.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

100 semiconductor package 110 base substrate
115: connection pad 117: circuit pattern
119: via 120: solder resist layer
125: opening 130: semiconductor chip
140: under-fill resin layer

Claims (9)

A base substrate having an outer circuit layer including a connection pad and a circuit pattern on at least one of one or the other surface thereof;
A solder resist layer formed on the base substrate, the solder resist layer including the connection pad to expose a portion of the circuit pattern; And
A semiconductor chip mounted on the base substrate
≪ / RTI > The method according to claim 1,
The semiconductor package further comprises an under-fill resin layer formed between the base substrate and the semiconductor chip. The method according to claim 2,
The underfill resin is an epoxy-based, polyimide-based, polyester-based, polyacrylate-based or a semiconductor resin mixture of these. The method according to claim 1,
The semiconductor package further comprises a surface treatment layer formed on the exposed connection pad and the circuit pattern. The method of claim 4,
The surface treatment layer is electrolytic nickel and gold plating method, electroless nickel nickel immersion gold (ENIG) method, electroless nickel nickel autocatalytic gold (ENAG) method, electroless nickel nickel electroless palladium inmmersion gold (ENEPIG), electroless nickel nickel immersion palladium immersion gold (ENPIG) A semiconductor package formed by at least one of a method, an electroless tin plating method, and an organic solderability preservative method. The method according to claim 1,
The base substrate includes:
A plurality of insulating layers; And
A plurality of circuit layers formed between the plurality of insulating layers
≪ / RTI > The method according to claim 1,
The connection pad and the circuit pattern is a semiconductor package consisting of an electroless plating layer, an electrolytic plating layer or a combination thereof. The method according to claim 1,
And a sealing member formed to cover the semiconductor chip on the base substrate. The method according to claim 8,
The sealing member is an epoxy packaged compound (Epoxy Molded Compound) semiconductor package.
KR1020110093543A 2011-09-16 2011-09-16 Semiconductor package KR20130030039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110093543A KR20130030039A (en) 2011-09-16 2011-09-16 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110093543A KR20130030039A (en) 2011-09-16 2011-09-16 Semiconductor package

Publications (1)

Publication Number Publication Date
KR20130030039A true KR20130030039A (en) 2013-03-26

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KR1020110093543A KR20130030039A (en) 2011-09-16 2011-09-16 Semiconductor package

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150090504A (en) * 2014-01-29 2015-08-06 삼성전기주식회사 Package substrate
US11315863B2 (en) 2019-10-22 2022-04-26 Samsung Electronics Co., Ltd. Package substrate and method of manufacturing the package substrate, and semiconductor package including the package substrate and method of manufacturing the semiconductor package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150090504A (en) * 2014-01-29 2015-08-06 삼성전기주식회사 Package substrate
US11315863B2 (en) 2019-10-22 2022-04-26 Samsung Electronics Co., Ltd. Package substrate and method of manufacturing the package substrate, and semiconductor package including the package substrate and method of manufacturing the semiconductor package
US11823995B2 (en) 2019-10-22 2023-11-21 Samsung Electronics Co., Ltd. Package substrate, and semiconductor package including the package substrate

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