KR20130028352A - Semiconductor package - Google Patents

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Publication number
KR20130028352A
KR20130028352A KR1020110091844A KR20110091844A KR20130028352A KR 20130028352 A KR20130028352 A KR 20130028352A KR 1020110091844 A KR1020110091844 A KR 1020110091844A KR 20110091844 A KR20110091844 A KR 20110091844A KR 20130028352 A KR20130028352 A KR 20130028352A
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South Korea
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semiconductor chip
pcb
pin
lead frame
semiconductor
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KR1020110091844A
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Korean (ko)
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박병규
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박병규
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Priority to KR1020110091844A priority Critical patent/KR20130028352A/en
Priority to PCT/KR2012/007202 priority patent/WO2013036057A1/en
Publication of KR20130028352A publication Critical patent/KR20130028352A/en

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Abstract

PURPOSE: A semiconductor package having a stack structure and a package method thereof are provided to simplify a line structure by using a PCB pattern structure. CONSTITUTION: A semiconductor package includes a pin and a semiconductor chip(102). The pin is electrically connected to a lead frame(100) or other pin. A PCB(104) is formed in the upper part of a semiconductor chip. The PCB includes a metal pattern. [Reference numerals] (100) Lower PCB/lead frame(100); (102) First semiconductor chip; (104) First PCB; (106) Insulation layer; (108) Second semiconductor chip

Description

반도체 패키지 및 반도체 패키지 방법{Semiconductor Package}Semiconductor package and semiconductor package method {Semiconductor Package}

본 발명은 반도체 패키지 및 반도체 패키지 방법에 관한 것으로, 더욱 상세하게는 반도체 칩 상단에 별도의 PCB를 적층하여 배선 연결에 사용되는 와이어의 길이를 감소시키는 동시에 양산성을 증대시키는 방안에 관한 것이다.
The present invention relates to a semiconductor package and a method for packaging a semiconductor package, and more particularly, to a method for increasing mass productivity while reducing a length of a wire used for wiring connection by stacking a separate PCB on a semiconductor chip.

통상적으로, 스택 패키지(Stack Package, 적층 패키지)는 복수의 반도체 칩을 적층한 패키지로서, 단순화된 공정에 의해 패키지의 제조 단가를 낮출 수 있고, 대량 생산이 가능하다.In general, a stack package (stack package) is a package in which a plurality of semiconductor chips are stacked, and the manufacturing cost of the package can be reduced by a simplified process, and mass production is possible.

적층 패키지의 한 예로 관통 실리콘 비아(Through Silicon Via : TSV)를 이용한 구조가 제안된 바 있고, 관통 실리콘 비아를 이용한 적층 패키지는 웨이퍼 단계에서 각각의 반도체 칩 내에 수직방향으로 관통 실리콘 비아를 형성한 후, 이 관통 실리콘 비아를 매개로 상부와 하부 반도체 칩들간의 물리적 및 전기적 연결이 이루어지도록 한 구조이다. As an example of a stacked package, a structure using a through silicon via (TSV) has been proposed. The stacked package using a through silicon via forms a through silicon via in a vertical direction in each semiconductor chip at a wafer stage. In addition, the structure is such that physical and electrical connections between the upper and lower semiconductor chips are made through the through silicon vias.

한편, 적층 패키지는 상부 및 하부 반도체 칩 간을 단순히 연결만 시켜서는 밀도를 향상시킨 적층 패키지로서의 올바른 메모리 동작을 구현할 수 없기 때문에, 각 반도체 칩을 적층시, 상부 및 하부 반도체 칩을 각각의 반도체 칩이 갖는 상이한 신호 별로 각각 구분될 수 있도록 각각의 반도체 칩 내에 재배선층(Redistribution Layer : RDL)을 형성하고, 재배선층을 각 반도체 칩에 형성된 관통 실리콘 비아 및 그에 맞는 전극 단자와 연결되도록 하여, 반도체 칩을 구분하고 있다.On the other hand, since the stack package cannot implement correct memory operation as a stack package having a higher density by simply connecting the upper and lower semiconductor chips, when the semiconductor chips are stacked, the upper and lower semiconductor chips may be separated from each other. A redistribution layer (RDL) is formed in each semiconductor chip so as to be distinguished for each of the different signals, and the redistribution layer is connected to the through silicon vias formed in each semiconductor chip and the corresponding electrode terminals. It is distinguished.

종래 UBM(Under Bump Metal) 형성시 이용된 시드층이 솔더 범프에 가해지는 스트레스에 의해 반도체 다이로부터 분리되는 것을 방지함으로써 신뢰성을 확보할 수 있는 반도체 패키지 및 그 제조 방법에 대해서는 한국공개번호 제2009-0089578호에 나타나 있다.For a semiconductor package and a method of manufacturing the same, the seed layer used to form the under bump metal (UBM) can be secured by preventing the seed layer from being separated from the semiconductor die due to the stress applied to the solder bumps. 0089578.

그러나 전술한 바와 같은 종래의 적층 패키지에서, 각각의 반도체 칩 내에 서로 상이한 재배선층을 형성하여 각 반도체 칩의 신호를 구별하는 방법은 각 반도체 칩 별로 재배선층을 형성하기 위한 별도의 패터닝(Patterning) 공정을 수행해야 하며, 패터닝을 위한 마스크를 별도로 형성해야 한다.However, in the conventional stacking package as described above, a method of distinguishing signals of each semiconductor chip by forming different redistribution layers in each semiconductor chip is a separate patterning process for forming a redistribution layer for each semiconductor chip. And a mask for patterning must be formed separately.

더욱이, 공정 수행에 있어서도 반도체 칩들이 적층되는 스택 위치에 따라 마스크의 위치를 바꿔가면서 패터닝 공정을 수행해야 하므로 양산성 저하 및 비용이 증가하게 된다.
Furthermore, in performing the process, the patterning process must be performed while changing the position of the mask according to the stack position where the semiconductor chips are stacked, thereby decreasing mass productivity and increasing cost.

본 발명이 해결하려는 과제는 양산성 저하와 비용 증가를 방지할 수 있는 스택 구조를 갖는 반도체 패키지 및 반도체 패키지 제조 공정을 제안함에 있다.SUMMARY OF THE INVENTION An object of the present invention is to propose a semiconductor package and a semiconductor package manufacturing process having a stack structure capable of preventing mass loss and increased cost.

본 발명이 해결하려는 다른 과제는 RDL 공정을 이용하여 패드(PAD)를 본딩하는 과정에서 발생하는 취약점을 해결할 수 있는 방안을 제안함에 있다.
Another problem to be solved by the present invention is to propose a method that can solve the vulnerability that occurs during the bonding pad (PAD) using the RDL process.

이를 위해 본 발명의 반도체 패키지는 다른 반도체 칩의 핀 또는 리드 프레임과 전기적으로 연결되는 핀을 구성하고 있는 반도체 칩과 상기 반도체 칩 상단에 형성되며, 상기 다른 반도체 칩의 핀 또는 리드 프레임과 상기 반도체 칩의 핀의 위치에 따라 구별되는 금속 물질로 형성되는 패턴을 갖는 PCB를 포함한다.To this end, the semiconductor package of the present invention is formed on the semiconductor chip and the semiconductor chip constituting the pin electrically connected to the pin or lead frame of the other semiconductor chip, the pin or lead frame and the semiconductor chip of the other semiconductor chip It includes a PCB having a pattern formed of a metallic material that is distinguished according to the position of the pin.

이를 위해 본 발명의 반도체 패키지 방법은 다른 반도체 칩의 핀 또는 리드 프레임과 전기적으로 연결되는 핀을 구성하고 있는 반도체 칩을 형성하는 단계, 형성된 상기 반도체 칩의 상단에 상기 다른 반도체 칩의 핀 또는 리드 프레임과 상기 반도체 칩의 핀의 위치에 따라 구별되는 금속 물질로 형성되는 패턴을 갖는 PCB를 형성하는 단계를 포함한다.
To this end, the semiconductor package method of the present invention comprises the steps of forming a semiconductor chip constituting a pin electrically connected to the pin or lead frame of another semiconductor chip, the pin or lead frame of the other semiconductor chip on top of the formed semiconductor chip And forming a PCB having a pattern formed of a metal material distinguished according to a position of a pin of the semiconductor chip.

본 발명에 따른 PCB를 이용한 반도체 패키지 방식은 종래 방식에 비해 높은 양산성과 비용 감소를 가진다는 장점이 있다. 즉, 본 발명은 PCB의 패턴 구조를 이용하여 칩과 칩의 핀을 연결하거나, 칩과 리드 프레임을 연결함으로써 배선에 사용되는 와이어의 길이의 감소와 배선 구조를 간단히 함으로써 높은 양산성과 비용 감소를 가지게 된다.
The semiconductor package method using the PCB according to the present invention has an advantage of having high mass production and cost reduction compared to the conventional method. In other words, the present invention uses a pattern structure of the PCB to connect the chip and the pin of the chip, or by connecting the chip and the lead frame to reduce the length of the wire used for wiring and simplify the wiring structure to have high productivity and cost reduction do.

도 1은 본 발명의 일실시 예에 따른 적층 구조를 갖는 반도체 패키지를 도시하고 있다.
도 2는 본 발명의 다른 실시 예에 따른 적층 구조를 갖는 반도체 패키지를 도시하고 있다.
도 3은 본 발명의 일실시 예에 따른 PCB를 이용한 칩과 칩의 연결 구조 또는 칩과 리드 프레임과의 연결 구조를 도시하고 있다. 1 illustrates a semiconductor package having a stacked structure according to an embodiment of the present invention.
2 illustrates a semiconductor package having a stacked structure according to another embodiment of the present invention.
3 illustrates a connection structure between a chip and a chip or a connection structure between a chip and a lead frame using a PCB according to an embodiment of the present invention.

전술한, 그리고 추가적인 본 발명의 양상들은 첨부된 도면을 참조하여 설명되는 바람직한 실시 예들을 통하여 더욱 명백해질 것이다. 이하에서는 본 발명의 이러한 실시 예를 통해 당업자가 용이하게 이해하고 재현할 수 있도록 상세히 설명하기로 한다.The foregoing and further aspects of the present invention will become more apparent through the preferred embodiments described with reference to the accompanying drawings. Hereinafter will be described in detail to enable those skilled in the art to easily understand and reproduce through this embodiment of the present invention.

도 1은 본 발명의 일실시 예에 따른 적층 구조를 갖는 반도체 패키지를 도시하고 있다. 이하 도 1을 이용하여 본 발명의 일실시 예에 따른 적층 구조를 갖는 반도체 패키지의 구성에 대해 상세하게 알아보기로 한다.1 illustrates a semiconductor package having a stacked structure according to an embodiment of the present invention. Hereinafter, a configuration of a semiconductor package having a stacked structure according to an embodiment of the present invention will be described in detail with reference to FIG. 1.

도 1에 의하면, 반도체 패키지는 하단으로부터 리드 프레임(Lead Frame; L/F), 제1 반도체 칩, 제1 PCB, 절연층, 제2 반도체 칩을 순서대로 적층한다. 물론 상술한 구성 이외에 다른 구성이 더 포함될 수 있음은 자명하다. 즉, 제 2PCB의 상단에 제2 절연층, 제 2절연층의 상단에 제3 반도체 칩을 순서대로 적층할 수 있다. 즉, 본 발명의 반도체 패키지는 복수의 반도체 칩과 PCB를 순서대로 반복하여 적층할 수 있다.Referring to FIG. 1, the semiconductor package sequentially stacks a lead frame (L / F), a first semiconductor chip, a first PCB, an insulating layer, and a second semiconductor chip from the bottom thereof. It goes without saying that other configurations other than the above-described configuration may be further included. That is, the second semiconductor layer may be stacked on top of the second PCB, and the third semiconductor chip may be sequentially stacked on the top of the second insulating layer. That is, in the semiconductor package of the present invention, a plurality of semiconductor chips and PCBs may be repeatedly stacked in order.

본 발명과 관련하여 리드 프레임(100)의 상단에 제1 반도체 칩(102)을 적층한다.In connection with the present invention, the first semiconductor chip 102 is stacked on the lead frame 100.

도 1은 하단에 리드 프레임이 형성되는 것으로 도시되어 있으나, 이에 한정되는 것은 아니다. 하단에 리드 프레임 대신 하단 PCB가 형성될 수 있다. 즉, 리더 프레임 상단에 반도체 칩이 적층되거나, 하단 PCB 상단에 반도체 칩이 적층될 수 있다. 1 shows that the lead frame is formed at the bottom, but is not limited thereto. The bottom PCB may be formed at the bottom instead of the lead frame. That is, the semiconductor chip may be stacked on top of the leader frame or the semiconductor chip may be stacked on top of the lower PCB.

제1 반도체 칩(102)의 상단에는 제1 PCB(104)를 적층한다. 본 발명과 관련하여 반도체 칩의 상단에는 PCB를 적층한다, 즉 기존 반도체 패키지는 복수의 반도체 칩들을 적층하고, 각 반도체 칩들과 리드 프레임을 배선으로 연결하거나, 적층되어 있는 반도체 칩들을 배선으로 상호 연결함으로써 배선 구조가 복잡하고, 배선 길이가 늘어난다는 단점이 있었다. 하지만, 본 발명은 제1 반도체 칩(102)의 상단에 제1 PCB(104)를 적층하며, 적층되는 제1 PCB(104)는 제1 반도체 칩(102)과 리드 프레임(100), 또는 제1 PCB(104)의 상단에 적층되는 제2 반도체 칩(108)을 고려하여 적합한 패턴을 갖는 제1 PCB(104)를 적층할 수 있다. 즉, 제1 반도체 칩(102)과 리드 프레임(100)의 배선 관계를 고려하여 제1 PCB(104)의 패턴을 형성하거나, 제1 반도체 칩(102)과 제2 반도체 칩(108)의 배선 관계를 고려하여 제1 PCB의 패턴을 형성할 수 있다.The first PCB 104 is stacked on the top of the first semiconductor chip 102. According to the present invention, a PCB is stacked on top of a semiconductor chip, that is, a conventional semiconductor package stacks a plurality of semiconductor chips, connects each semiconductor chip and a lead frame by wiring, or interconnects the stacked semiconductor chips by wiring. This has the disadvantage that the wiring structure is complicated and the wiring length is increased. However, according to the present invention, the first PCB 104 is stacked on top of the first semiconductor chip 102, and the stacked first PCB 104 includes the first semiconductor chip 102 and the lead frame 100, or the first semiconductor chip 102. In consideration of the second semiconductor chip 108 stacked on the top of the first PCB 104, the first PCB 104 having a suitable pattern may be stacked. That is, the pattern of the first PCB 104 is formed in consideration of the wiring relationship between the first semiconductor chip 102 and the lead frame 100, or the wiring of the first semiconductor chip 102 and the second semiconductor chip 108 is performed. In consideration of the relationship, the pattern of the first PCB may be formed.

제1 PCB(104)의 상단에는 절연층(106)이 적층된다. 절연층(106)은 실리콘 또는 에폭시 등으로 구성된다. 도 1은 제1 PCB(104)의 상단에 절연층이 적층되는 것으로 도시하고 있으나, 이에 한정되는 것은 아니다. 제1 PCB가 절연층의 역할을 수행하는 경우에는 제1 PCB(104)의 상단에는 절연층(106)을 적층하지 않을 수 있다.An insulating layer 106 is stacked on top of the first PCB 104. The insulating layer 106 is made of silicon, epoxy, or the like. 1 illustrates that an insulating layer is stacked on top of the first PCB 104, but is not limited thereto. When the first PCB serves as the insulating layer, the insulating layer 106 may not be stacked on the top of the first PCB 104.

절연층(106)의 상단에는 제2 반도체 칩(108)이 적층된다.The second semiconductor chip 108 is stacked on top of the insulating layer 106.

이와 같이 함으로써 적층되는 반도체 칩 상호 간에 발생했던 복잡한 배선 문제를 효과적으로 해결할 수 있게 된다.By doing this, it is possible to effectively solve the complicated wiring problem occurring between the stacked semiconductor chips.

도 2는 본 발명의 일실시 예에 따른 반도체 패키지를 도시하고 있다. 이하 도 2를 이용하여 본 발명의 일실시 예에 따른 반도체 패키지에 대해 상세하게 알아보기로 한다.2 illustrates a semiconductor package according to an embodiment of the present invention. Hereinafter, a semiconductor package according to an embodiment of the present invention will be described in detail with reference to FIG. 2.

도 2(a)는 리드 프레임(L/F)(200)과 제1 반도체 칩(202)을 포함하고 있는 반도체 패키지를 도시하고 있다. 도 2(a)와 같이 형성되는 있는 반도체 패키지에 리드 프레임(200)과 연결이 요구되는 제2 반도체 칩(206)을 적층하는 경우에 대해 알아보기로 한다.2A illustrates a semiconductor package including a lead frame (L / F) 200 and a first semiconductor chip 202. A case in which the second semiconductor chip 206 required to be connected to the lead frame 200 is stacked on the semiconductor package formed as shown in FIG. 2A will be described.

도 2(a)는 종래 리드 프레임(L/F)(200)과 제1 반도체 칩(202)을 포함하고 있는 반도체 패키지에 리드 프레임과 배선 연결이 요구되는 제2 반도체 칩(206)을 적층하는 경우를 도시하고 있다. 도 2(a)에 의하면, 제2 반도체 칩(206)과 리드 프레임(200)을 직접 와이어를 이용하여 배선 작업을 수행하고 있다. 이와 같이 제2 반도체 칩(206)과 리드 프레임(200)을 직접 와이어를 이용하여 배선 작업을 수행함으로써 배선의 연결 구조가 복잡해지며, 배선 길이 역시 늘어난다는 단점을 가지게 된다. 또한, 도 2(a)에 도시되어 있는 바와 같이 제1 반도체 칩(202)과 제2 반도체 칩(206)이 전기적으로 분리되기 위해 제1 반도체 칩(202)과 제2 반도체 칩(206) 사이에 절연층(204)을 형성한다. 절연층(204)으로 인해 반도체 패키지에 사용되는 와이어의 길이가 길어지게 되고, 이로 인해 양산성이 떨어지며, 제조 단가가 올라가는 문제점이 있다.FIG. 2 (a) illustrates a method of stacking a second semiconductor chip 206 requiring wiring connection with a lead frame in a semiconductor package including a conventional lead frame (L / F) 200 and a first semiconductor chip 202. The case is illustrated. Referring to FIG. 2 (a), the second semiconductor chip 206 and the lead frame 200 are directly wired using wires. As described above, the wiring structure of the wiring is complicated by directly wiring the second semiconductor chip 206 and the lead frame 200, and the wiring length is also increased. In addition, as shown in FIG. 2A, the first semiconductor chip 202 and the second semiconductor chip 206 are electrically separated from each other so as to be electrically separated from each other. An insulating layer 204 is formed on the substrate. Due to the insulating layer 204, the length of the wire used in the semiconductor package is long, which leads to a problem in that it is inferior in mass productivity and the manufacturing cost increases.

본 발명은 이러한 문제점을 해결하기 위해 도 2(b)에 도시되어 있는 바와 같이 제1 반도체 칩(202)의 상단에 PCB(208)를 적층하고, 적층된 PCB(208)의 상단에 제2 반도체 칩(206)을 적층한다. 즉, 배선 연결이 요구되는 제2 반도체 칩(206)의 핀과 리드 프레임(200)의 핀을 연결하는 배선 길이를 최소로 하는 형태로 PCB(208)의 패턴을 형성한다. 이와 같이 형성된 PCB(208)의 패턴을 이용하여 제2 반도체 칩(206)의 핀과 PCB(208)의 핑거를 연결하며, PCB(208)의 핑거와 리드 프레임(200)의 핀을 연결함으로써 배선 연결 구조를 간단히 할 수 있으며, 연결 길이 역시 줄일 수 있게 된다.To solve this problem, the present invention stacks the PCB 208 on top of the first semiconductor chip 202 and the second semiconductor on top of the stacked PCB 208, as shown in FIG. The chips 206 are stacked. That is, the pattern of the PCB 208 is formed in such a way that the wiring length connecting the pins of the second semiconductor chip 206 and the pins of the lead frame 200 to which the wiring connection is required is minimized. The pins of the second semiconductor chip 206 and the fingers of the PCB 208 are connected by using the pattern of the PCB 208 formed as above, and the wires are connected by connecting the fingers of the PCB 208 and the pins of the lead frame 200. The connection structure can be simplified and the connection length can be reduced.

물론 리더 프레임(하단 PCB)의 핀과 제1 반도체 칩의 핀 사이에 배선이 요구되는 경우에도 동일하게 특정 패턴이 형성되어 있는 별도의 PCB를 이용하여 용이하게 배선 작업을 수행할 수 있게 된다. 또한 제1 반도체 칩(202)과 제2 반도체 칩(206)사이에 적층되는 PCB(208)가 절연층 기능도 동시에 수행하는 경우에는 별도의 절연층을 형성하지 않음으로써 용이하게 배선 작업을 수행할 수 있게 된다.Of course, even when wiring is required between the pins of the leader frame (lower PCB) and the pins of the first semiconductor chip, the wiring operation can be easily performed by using a separate PCB having the same specific pattern. In addition, when the PCB 208 stacked between the first semiconductor chip 202 and the second semiconductor chip 206 also performs an insulating layer function, wiring is easily performed by not forming a separate insulating layer. It becomes possible.

도 3은 본 발명의 일실시 예에 따른 PCB를 이용한 반도체 칩과 반도체 칩의 연결 구조 또는 반도체 칩과 리드 프레임과의 연결 구조를 도시하고 있다. 특히 도 3(a)은 종래 반도체 칩과 반도체 칩의 연결 구조 또는 반도체 칩과 리드 프레임의 연결 구조를 도시하고 있으며, 도 3(b)은 본 발명에 따른 PCB를 이용한 반도체 칩과 반도체 칩의 연결 구조 또는 반도체 칩과 리드 프레임의 연결 구조를 도시하고 있다.3 illustrates a connection structure of a semiconductor chip and a semiconductor chip or a connection structure of a semiconductor chip and a lead frame using a PCB according to an embodiment of the present invention. In particular, FIG. 3 (a) shows a connection structure of a conventional semiconductor chip and a semiconductor chip or a connection structure of a semiconductor chip and a lead frame, and FIG. 3 (b) shows a connection between a semiconductor chip and a semiconductor chip using a PCB according to the present invention. The structure or connection structure of the semiconductor chip and the lead frame is shown.

도 3(a)에 의하면, 리더 프레임의 핀과 제1 반도체 칩의 핀을 연결하기 위해서는 직접 와이어를 이용하여 리더 프레임의 핀과 제1 반도체 칩의 핀을 연결한다. 이와 같은 와이어를 이용하여 리더 프레임의 핀과 제1 반도체 칩의 핀을 연결하는 경우 배선 작업에 사용되는 와이어의 길이가 증가하고 배선 구조가 복잡해진다는 단점이 있다.According to FIG. 3A, in order to connect the pins of the leader frame and the pins of the first semiconductor chip, the pins of the leader frame and the pins of the first semiconductor chip are directly connected using wires. When the pins of the leader frame and the pins of the first semiconductor chip are connected using the wires, the length of the wires used for the wiring work increases and the wiring structure becomes complicated.

이에 비해 도 3(b)은 PCB를 이용하여 리더 프레임의 핀과 제1 반도체 칩의 핀을 연결하는 구조를 도시하고 있다. 특히 도 3(b)는 연결해야 하는 리더 프레임의 핀과 제1 반도체 칩의 핀이 서로 반대방향에 위치하는 경우를 도시하고 있다. 본 발명에 따른 PCB는 리더 프레임의 핀과 제1 반도체 칩의 핀을 연결하기 위해 패턴을 형성한다. 즉, 제1 반도체 칩의 핀과 인접되어 있는 제1지점과 리더 프레임의 핀과 인접되어 있는 제2 지점 사이를 금속 재질을 이용하여 패턴을 형성한다. 패턴이 형성되어 있는 PCB의 제1 지점과 제1 반도체 칩의 핀을 연결하고, 제2 지점과 리더 프레임의 핀을 와이어를 이용하여 연결한다. 이와 같은 와이어를 이용하여 제1 지점과 제1 반도체 칩의 핀을 연결하고, 제2 지점과 리더 프레임의 핀을 연결하는 경우, 배선 작업에 사용되는 와이어의 길이가 감소되고 배선 구조 역시 단순해진다.도 3(b)는 하단에 리더 프레임이 형성되는 있는 것으로 설명하였으나, 이에 한정되는 것은 아니다. 상술한 바와 같이 하단에 리더 프레임 대신 PCB가 형성되는 경우에도 동일하게 적용할 수 있으며, 제1 반도체 칩의 핀과 제2 반도체 칩의 핀을 연결하는 경우에도 동일하게 적용할 수 있다. In contrast, FIG. 3B illustrates a structure in which a pin of the leader frame and a pin of the first semiconductor chip are connected by using a PCB. In particular, FIG. 3B illustrates a case in which the pins of the leader frame to be connected and the pins of the first semiconductor chip are located in opposite directions. PCB according to the present invention forms a pattern for connecting the pin of the leader frame and the pin of the first semiconductor chip. That is, a pattern is formed using a metal material between a first point adjacent to the pin of the first semiconductor chip and a second point adjacent to the pin of the leader frame. The first point of the PCB on which the pattern is formed is connected to the pins of the first semiconductor chip, and the second point and the pin of the leader frame are connected using a wire. When the first point and the pin of the first semiconductor chip are connected using the wire, and the second point and the pin of the leader frame are connected, the length of the wire used for the wiring work is reduced and the wiring structure is simplified. 3 (b) has been described as having a leader frame formed at the bottom thereof, but is not limited thereto. As described above, the same applies to the case in which the PCB is formed instead of the leader frame. The same applies to the case in which the pins of the first semiconductor chip and the pins of the second semiconductor chip are connected.

본 발명은 도면에 도시된 일실시 예를 참고로 설명되었으나, 이는 예시적인 것에 불과하며, 본 기술 분야의 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 것이다.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention .

100: 리드 프레임 102: 제1 반도체 칩
104: 제1 PCB 106: 절연층
108: 제2 반도체 칩 110: 제2 PCB100: lead frame 102: first semiconductor chip
104: first PCB 106: insulating layer
108: second semiconductor chip 110: second PCB

Claims (6)

다른 반도체 칩의 핀 또는 리드 프레임과 전기적으로 연결되는 핀을 구성하고 있는 반도체 칩;
상기 반도체 칩 상단에 형성되며, 상기 다른 반도체 칩의 핀 또는 리드 프레임과 상기 반도체 칩의 핀의 위치에 따라 구별되는 금속 물질로 형성되는 패턴을 갖는 PCB를 포함함을 특징으로 하는 반도체 패키지.
A semiconductor chip constituting a pin electrically connected to a pin or lead frame of another semiconductor chip;
And a PCB formed on top of the semiconductor chip, the PCB having a pattern formed of a metal material distinguished according to a location of a pin or lead frame of the other semiconductor chip and a pin of the semiconductor chip.
제 1항에 있어서, 상기 PCB의 패턴은,
상기 다른 반도체 칩의 핀 또는 리드 프레임의 위치를 고려하여 PCB상에서 제1 지점을 결정하고, 상기 반도체 칩의 핀의 위치를 고려하여 상기 PCB상에서 제2 지점을 결정하며, 결정된 제1 지점과 제2 지점을 상기 금속 물질로 연결함을 특징으로 하는 반도체 패키지.
The method of claim 1, wherein the pattern of the PCB,
A first point is determined on the PCB in consideration of the position of the pin or lead frame of the other semiconductor chip, and a second point is determined on the PCB in consideration of the position of the pin of the semiconductor chip. And a point connecting said points with said metallic material.
제 2항에 있어서, 상기 반도체 패키지는,
제1 반도체 칩;
상기 제1 반도체 칩의 상단에 적층되는 제1 PCB;
상기 제1 PCB의 상단에 적층되는 절연층;
상기 절연층의 상단에 형성되는 제2 반도체 칩을 포함함을 특징으로 하는 반도체 패키지.
The method of claim 2, wherein the semiconductor package,
A first semiconductor chip;
A first PCB stacked on top of the first semiconductor chip;
An insulating layer stacked on top of the first PCB;
And a second semiconductor chip formed on top of the insulating layer.
제 2항에 있어서, 상기 반도체 패키지는,
리드 프레임 또는 하단 PCB;
상기 리드 프레임 또는 하단 PCB의 상단에 적층되는 제1 반도체 칩;
상기 제1 반도체 칩의 상단에 적층되는 제1 PCB;
상기 제1 PCB의 상단에 형성되는 제2 반도체 칩을 포함함을 특징으로 하는 반도체 패키지.
The method of claim 2, wherein the semiconductor package,
Lead frame or bottom PCB;
A first semiconductor chip stacked on top of the lead frame or the bottom PCB;
A first PCB stacked on top of the first semiconductor chip;
And a second semiconductor chip formed on an upper end of the first PCB.
제 2항에 있어서, 상기 반도체 패키지는,
리드 프레임 또는 하단 PCB;
상기 리드 프레임 또는 하단 PCB의 상단에 적층되는 제1 반도체 칩;
상기 제1 반도체 칩의 상단에 적층되는 제1 PCB를 포함함을 특징으로 하는 반도체 패키지.
The method of claim 2, wherein the semiconductor package,
Lead frame or bottom PCB;
A first semiconductor chip stacked on top of the lead frame or the bottom PCB;
And a first PCB stacked on top of the first semiconductor chip.
다른 반도체 칩의 핀 또는 리드 프레임과 전기적으로 연결되는 핀을 구성하고 있는 반도체 칩을 형성하는 단계;
형성된 상기 반도체 칩의 상단에 상기 다른 반도체 칩의 핀 또는 리드 프레임과 상기 반도체 칩의 핀의 위치에 따라 구별되는 금속 물질로 형성되는 패턴을 갖는 PCB를 형성하는 단계를 포함함을 특징으로 하는 반도체 패키지 방법.Forming a semiconductor chip constituting a pin electrically connected to a pin or lead frame of another semiconductor chip;
Forming a PCB having a pattern formed on a top of the formed semiconductor chip with a metal material which is distinguished according to the pin or lead frame of the other semiconductor chip and the position of the pin of the semiconductor chip. Way.
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