KR20130023766A - Method for fabricating semiconductor device using single-side-contact - Google Patents

Method for fabricating semiconductor device using single-side-contact Download PDF

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Publication number
KR20130023766A
KR20130023766A KR1020110086760A KR20110086760A KR20130023766A KR 20130023766 A KR20130023766 A KR 20130023766A KR 1020110086760 A KR1020110086760 A KR 1020110086760A KR 20110086760 A KR20110086760 A KR 20110086760A KR 20130023766 A KR20130023766 A KR 20130023766A
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South Korea
Prior art keywords
sacrificial
film
forming
etching
layer
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KR1020110086760A
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Korean (ko)
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이해정
김은미
고경보
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에스케이하이닉스 주식회사
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Publication of KR20130023766A publication Critical patent/KR20130023766A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
    • H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66045—Field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device using a single side contact is provided to prevent not-open and secure a sufficient selectivity ratio with a peripheral structure in a single side contact process. CONSTITUTION: A plurality of pillars(24) separated by a trench(23) is formed by etching a substrate(21). A first liner film pattern(25A) covering the sidewall and the trench of the pillar is formed. A second sacrificial layer is formed on the first liner film pattern. A spin-on carbon film(31) is formed on the second sacrificial layer. An antireflection layer(32) is formed on the spin-on carbon film. A photosensitive pattern(33) is formed on the antireflection layer. A single side contact structure(34) is formed by etching a second sacrificial layer.

Description

Method of manufacturing semiconductor device using single side contact {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING SINGLE―SIDE―CONTACT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a single side contact.

As the design rule of the semiconductor device decreases, the cell size decreases, thereby increasing the process difficulty in the 8F 2 or 6F 2 (F is a minimun feature) cell structure. In addition, the short channel margin characteristic is degraded due to the reduction of the gate length.

In order to solve this problem, a method of three-dimensionally processing a semiconductor substrate and thereby three-dimensionally forming a transistor has been proposed. For example, a vertical transistor having a pillar extending in a direction perpendicular to the surface of a semiconductor substrate is used as a channel. Vertical transistors can reduce the footprint and contribute to a reduction in cell size. In addition, the vertical transistor can realize a 4F 2 cell structure by forming the gate and the channel in the vertical direction.

When a vertical transistor using a pillar is used as a cell transistor of a memory device, one side (eg, a source) of a junction that becomes a source or a drain is a bitline. ), And the other side of the junction (eg, drain) is connected to a capacitor. In general, since the capacitor is disposed above the cell transistor, the capacitor is connected to the upper part of the pillar and the bit line is connected to the lower part of the pillar.

A portion of the sidewall of either pillar must be exposed to connect the bitline and one side junction. This is called a SSC (Single-Side-Contact) process or an OSC (One-Side-Contact) OSC process. Hereinafter, it is abbreviated as "singleside contact process." The source formed inside the pillar is exposed by the single side contact process, and the buried bit line is electrically connected to the exposed source.

1A to 1C are diagrams for describing a single side contact process according to the prior art.

As shown in FIG. 1A, a plurality of pillars 14 separated by a plurality of trenches 13 are formed on the substrate 11. The hard mask film 12 is formed on the pillar 14. An insulating film is coated on both sidewalls of the pillars 14, the surface of the trench 13 between the pillars 14, and the sidewalls of the hard mask film 12. The insulating film includes a liner oxide film 15A and a liner nitride film 15B.

A plug 16 partially filling the trench 13 is formed on the liner film, and a sacrificial spacer 17 is formed on the sidewall of the liner film above the plug 16.

A sacrificial oxide film 18 is formed between the pillars 14 on which the sacrificial spacers 17 are formed.

As shown in FIG. 1B, the sacrificial oxide layer 18 is etched using the contact mask 19 for single side contact. In this case, the etching of the sacrificial oxide layer 18 may use dry etching.

As shown in FIG. 1C, after the sacrificial spacer 17 of one sidewall is removed, a portion of the liner oxide layer 15A is removed to form an open portion 20 exposing a portion of one sidewall of the pillar 14. . Thereafter, the sacrificial oxide film 18 and the sacrificial spacers 17 are removed.

However, in the conventional technique, when etching the sacrificial oxide film 18, the conventional etching technique is very difficult to etch so that not open occurs while securing a selectivity with the liner nitride film 15B of 10: 1 or more. .

Therefore, when the sacrificial oxide layer 18 is etched, the hard mask layer 12, the liner oxide layer 15A, and the liner nitride layer 15B are lost (see reference numeral 100). For this reason, since the asymmetry of the hard mask film 12 occurs after the open portion 20 is formed, there is a limit to high integration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing a sick open while sufficiently securing a selection ratio with a peripheral structure during a single side contact process.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a plurality of pillars separated by a trench by etching the substrate; Forming a liner layer covering the sidewalls and the trench of the pillar; Forming a first sacrificial layer gap-filling the trench on the liner layer; Recessing the first sacrificial layer; Forming a second sacrificial film on the entire surface including the recessed first sacrificial film; Forming a single side contact mask on the second sacrificial layer; Etching the second sacrificial layer to form a single side structure; Etching the first sacrificial layer under the single side structure to form a recessed single side structure; And forming an open portion to etch a portion of the liner layer to open a portion of one sidewall of the body.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of etching the substrate to form a plurality of pillars separated by a trench; Forming a liner layer covering the sidewalls and the trench of the pillar; Forming a plug partially filling the trench on the liner layer; Forming a first sacrificial layer gap-filling the trench on the plug; Recessing the first sacrificial layer; Forming a second sacrificial film on the entire surface including the recessed first sacrificial film; Forming a single side contact mask containing carbon on the second sacrificial layer; Etching the second sacrificial layer to form a single side structure; Etching the first sacrificial layer under the single side structure to form a recessed single side structure; And forming an open portion to etch a portion of the liner layer to open a portion of one sidewall of the body.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of etching the substrate to form a plurality of pillars separated by a trench; Forming a liner layer covering the sidewalls and the trench of the pillar; Forming a sacrificial oxide film gap-filling the trench on the liner film; Recessing the sacrificial oxide film; Forming a sacrificial polysilicon film on the entire surface including the recessed sacrificial oxide film; Forming a single side contact mask on the sacrificial polysilicon layer; Etching the sacrificial polysilicon layer to form a single side structure; Etching the sacrificial oxide layer under the single side structure to form a recessed single side structure; And forming an open portion to etch a portion of the liner layer to open a portion of one sidewall of the body.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of etching the substrate to form a plurality of pillars separated by a trench; Forming a liner layer covering the sidewalls and the trench of the pillar; Forming a sacrificial oxide film gap-filling the trench on the liner film; Recessing the sacrificial oxide film; Forming a sacrificial polysilicon film on the entire surface including the recessed sacrificial oxide film; Forming a single side contact mask on the sacrificial polysilicon layer; Etching the sacrificial polysilicon layer to form a single side structure; Etching the sacrificial oxide layer under the single side structure to form a recessed single side structure; Etching a portion of the liner layer to form an open portion for opening a portion of one sidewall of the body; And forming a buried bit line connected to the body through the open part.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of etching the substrate to form a plurality of pillars separated by a trench; Forming a liner layer covering the sidewalls and the trench of the pillar; Forming a plug partially filling the trench on the liner layer; Forming a sacrificial oxide film gap-filling the trench on the plug; Recessing the sacrificial oxide film; Forming a sacrificial polysilicon film on the entire surface including the recessed sacrificial oxide film; Forming a single side contact mask on the sacrificial polysilicon layer; Etching the sacrificial polysilicon layer to form a single side structure; Etching the sacrificial oxide layer under the single side structure to form a recessed single side structure; Etching a portion of the liner film adjacent the upper portion of the plug to form an open portion for opening a portion of one sidewall of the body; And forming a buried bit line connected to the body through the open part on the plug.

According to the present invention, when the single side contact structure is formed, a sacrificial oxide film is wet-etched in a predetermined amount, and then additionally a sacrificial polysilicon film is deposited on the upper part, and then selectively dry-etched to secure the selectivity for the oxide film and the nitride film. It is possible to prevent the high integration of the device can be achieved.

1A to 1C are diagrams for describing a single side contact process according to the prior art.
2A through 2K are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2A through 2K are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, a hard mask film 22 is formed on the semiconductor substrate 21. The semiconductor substrate 21 includes a silicon-containing substrate, for example, a silicon substrate and a silicon germanium substrate. The hard mask film 22 includes a nitride film. In addition, the hard mask film 22 may have a multilayer structure including an oxide film and a nitride film. For example, the hard mask layer 22 may be stacked in the order of the hard mask nitride layer (HM Nitride) and the hard mask oxide layer (HM Oxide). In addition, the hard mask layer 22 may be laminated in the order of a hard mask nitride film, a hard mask oxide film, a hard mask silicon oxynitride film (HM SiON), and a hard mask carbon film (HM Carbon). In the case of including the hard mask nitride layer, a pad oxide layer may be further formed between the substrate 21 and the hard mask layer 22. The hard mask film 22 is formed using a photosensitive film pattern (not shown).

Next, a trench etch process is performed using the hard mask layer 22 as an etch barrier. For example, the pillars 24 are formed by etching the substrate 21 by a predetermined depth using the hard mask layer 22 as an etch barrier. The pillars 24 are separated from each other by the trenches 23. The pillar 24 includes an active region where a transistor is formed. The pillars 24 are in the form of lines with two side walls. Trench etching processes include anisotropic etch. When the substrate 21 is a silicon substrate, the anisotropic etching may include plasma dry etching using Cl 2 or HBr gas alone, or using a mixture of these gases. The plurality of pillars 24 are separated by the trench 23 described above, and the pillars 24 are formed to extend in the vertical direction on the substrate 21. The pillar 24 is a line pillar extending in the first direction.

The first liner film 25 is formed as an insulating film. The first liner film 25 includes an oxide film such as a silicon oxide film.

A conductive film 26 is formed on the first liner film 25 to gap fill the trenches 23 between the pillars 24. The conductive layer 26 includes undoped polysilicon or amorphous silicon. The conductive film 26 becomes a plug.

As shown in FIG. 2B, the conductive film 26 is planarized until the surface of the hard mask film 22 is exposed. Planarization of the conductive film 26 includes a chemical mechanical polishing (CMP) process. The etch-back process is performed continuously. After such an etch back process, a preliminary plug 26A for providing the first recess R1 is formed. In the chemical mechanical polishing process, the first liner layer 25 on the hard mask layer 24 may be polished. As a result, a first liner film pattern 25A covering both sidewalls of the hard mask film 22 and the trench 23 is formed. The first liner film pattern 25A also covers the bottom of the trench 23.

Subsequently, the first liner layer pattern 25A is slimmed by using wet etching. At this time, by adjusting the wet etching time, the first liner film pattern 25A may remain on the sidewall of the pillar 24 with a predetermined thickness.

As shown in Fig. 2C, a second liner film 27 is formed as an insulating film on the entire surface including the preliminary plug 26A. The second liner film 27 includes a nitride film such as a silicon nitride film. The second liner film 27 is formed to have the same thickness as the slimmed thickness of the first liner film pattern 25A.

As shown in FIG. 2D, the second liner layer 27 is selectively etched. As a result, the second liner film pattern 27A is formed in the slimming area of the first liner film pattern 25A. An etch back process may be applied to form the second liner film pattern 27A, whereby the second liner film pattern 27A becomes a spacer.

Subsequently, the preliminary plug 26A is recessed with a predetermined depth using the second liner film pattern 27A as an etch barrier. As a result, a second recess R2 exposing a part of the surface of the first liner film pattern 25A is formed. The preliminary plug forming the second recess R2 becomes the plug 26B. If plug 26B comprises polysilicon, it is recessed using an etch back process.

As shown in FIG. 2E, a metal nitride film is conformally formed on the entire surface including the second recess R2. Thereafter, the spacer etching is performed to form the sacrificial spacer 28. The sacrificial spacers 28 are formed on both sidewalls of the body 24. The sacrificial spacer 28 includes a titanium nitride film TiN.

Subsequently, the second recess R2 on which the sacrificial spacer 28 is formed is gap-filled to form a first sacrificial layer pattern 29 having a recessed surface. The first sacrificial film pattern 29 includes an oxide film. The first sacrificial layer pattern 29 includes a spin on dielectric (SOD). In order to form the first sacrificial layer pattern 29, an oxide layer is formed on the entire surface to gap-fill the second recess. Subsequently, as the wet etching is performed after the planarization, the recessed first sacrificial layer pattern 29 is formed. Wet etching may proceed with a solution containing dilute hydrofluoric acid. The amount of etching during the wet etching to form the first sacrificial layer pattern 29 is adjusted to expose the upper portion of the sacrificial spacer 28.

Both side walls of the hard mask layer 22 protrude from the recessed first sacrificial layer pattern 29. The laminated structure of the pillars 24 and the hard mask film 22 is called a body structure. Accordingly, the body structure is separated by the plurality of trenches 23, and is formed by the first liner film pattern 25A, the second liner film pattern 27A, the sacrificial spacer 28 and the first sacrificial film pattern 29. Insulated.

As shown in FIG. 2F, the second sacrificial layer 30 is formed on the entire surface including the first sacrificial layer pattern 29. The second sacrificial film 30 includes polysilicon. The second sacrificial layer 30 is formed to have a thickness to fill the upper portion of the recessed first sacrificial layer pattern 29. The second sacrificial film 30 may be planarized using CMP to facilitate the subsequent photolithography process.

Subsequently, after forming spin-on carbon (SOC) 31 as a hard mask film on the second sacrificial film 30, an anti-reflection film 32 is formed on the spin-on carbon film 31. The antireflection film 32 includes SiON.

The photosensitive film pattern 33 is formed on the anti-reflection film 32. The photoresist pattern 33 is also referred to as a single side contact mask or an OSC mask. One side of the photoresist pattern 33 is aligned between the pillars 24, and the other side of the photoresist pattern 33 is aligned on the top of the pillars 24. That is, the upper portion of the pillars 24 overlaps with the photoresist pattern 33, and a portion of the pillars 24 overlaps with each other.

As shown in FIG. 2G, the anti-reflection film 32 and the spin-on carbon film 31 are sequentially etched using the photoresist pattern 33 as an etch barrier. Subsequently, the second sacrificial film 30 is selectively etched using the spin-on carbon film 31 as an etching barrier. As a result, the second sacrificial film pattern 30A is formed, and the single side structure 34 is formed to partially expose the upper surface of the first sacrificial film pattern 29 by the second sacrificial film pattern 30A.

Here, the second sacrificial layer pattern 30A is etched by dry etching, and is etched by using plasma including HBr during dry etching. This can maximize the selectivity of the oxide film and the nitride film. For example, by etching using a plasma containing HBr, etching can be etched so as to ensure that the selectivity of the oxide film and the nitride film is 10: 1 or more, while the sick open does not occur.

As described above, the hard mask layer 22, the first liner layer pattern 25A, and the second liner layer pattern 27A are formed by using dry etching, particularly, plasma containing HBr when etching the second sacrificial layer pattern 30A. Consumption does not occur.

Meanwhile, the photoresist pattern 33 and the anti-reflection film 32 may be removed before etching the second sacrificial layer 30. As a result, the spin-on carbon film 31 becomes an etch barrier.

As shown in FIG. 2H, the spin-on carbon film 31 is removed.

Next, any one of the sacrificial spacers 28 is removed using the second sacrificial film pattern 30A as an etch barrier. As a result, a single-sided structure 34A is formed between the first sacrificial film pattern 29 and the second liner film pattern 27A. The sacrificial spacers 28 are removed using wet etching. Accordingly, one sacrificial spacer 28A remains. Wet etching uses a solution mixed with sulfuric acid and hydrogen peroxide.

By removing the sacrificial spacers, the first liner film pattern 25A and the first sacrificial film pattern 29 are exposed.

As shown in FIG. 2I, wet etching is performed to expose a portion of the lower sidewall of the pillar 24.

Wet etching uses hydrofluoric acid (HF), BOE (Buffered Oxide Etchant). By using wet etching, the first sacrificial film pattern 29 may be selectively etched without damaging the plug 26B, the sacrificial spacer 28A, and the second liner film pattern 27A. Subsequently, a part of the first liner film pattern 25A exposed between the second liner film pattern 27A and the plug 26B is etched. As a result, an open portion 35 exposing a portion of one sidewall of the pillar 24 is formed. The open part 35 becomes a single side contact or an OSC.

As shown in FIG. 2J, the second sacrificial film pattern 30A is removed using a plasma containing fluorine. A part of the plug 26B may be recessed when the second sacrificial film pattern 30A is removed, but this does not affect device characteristics. When the second sacrificial layer pattern 30A is removed, the wet sacrificial layer may be wet etched using a dilute nitric acid solution.

Next, the remaining sacrificial spacers 28A are removed. The sacrificial spacers 28A are removed using a solution in which sulfuric acid and hydrogen peroxide water are mixed.

As shown in FIG. 2K, the buried bit line 36 is formed on the plug 26B to contact the pillar 24 through the opening. A method of forming the buried bit line 36 is as follows. First, a conductive film is formed along the entire structure in which the open part 35 is formed. The conductive film gap gaps between the pillars 24. The conductive film is a material used as the buried bit line 36 and is formed of a low resistance material having a low resistance. For example, the conductive film includes a metal film or a metal nitride film. The conductive film includes a titanium nitride film (TiN). Next, the planarization and etch back processes are sequentially performed on the conductive film. As a result, the conductive film remains only in the trench 23. The planarization proceeds until the surface of the hard mask film 22 is exposed, for example, by applying chemical mechanical polishing (CMP). The conductive film becomes a buried bit line 36 by the etch back process. By forming the buried bit line 36 using a metal film or a metal nitride film, the resistance of the buried bit line 36 can be lowered.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.

21: semiconductor substrate 22: hard mask film
23: trench 24: pillar
25A: first liner film pattern 26B: plug
27A: second liner film pattern 28, 28A: sacrificial spacer
29: first sacrificial film pattern 30A: second sacrificial film pattern
35: open part 36: buried bit line

Claims (5)

Etching the substrate to form a plurality of pillars separated by trenches;
Forming a liner layer covering the sidewalls and the trench of the pillar;
Forming a first sacrificial layer gap-filling the trench on the liner layer;
Recessing the first sacrificial layer;
Forming a second sacrificial film on the entire surface including the recessed first sacrificial film;
Forming a single side contact mask on the second sacrificial layer;
Etching the second sacrificial layer to form a single side structure;
Etching the first sacrificial layer under the single side structure to form a recessed single side structure; And
Etching a portion of the liner layer to form an open portion for opening a portion of one sidewall of the body
≪ / RTI >
Etching the substrate to form a plurality of pillars separated by trenches;
Forming a liner layer covering the sidewalls and the trench of the pillar;
Forming a plug partially filling the trench on the liner layer;
Forming a first sacrificial layer gap-filling the trench on the plug;
Recessing the first sacrificial layer;
Forming a second sacrificial film on the entire surface including the recessed first sacrificial film;
Forming a single side contact mask on the second sacrificial layer;
Etching the second sacrificial layer to form a single side structure;
Etching the first sacrificial layer under the single side structure to form a recessed single side structure; And
Etching a portion of the liner layer to form an open portion for opening a portion of one sidewall of the body
≪ / RTI >
Etching the substrate to form a plurality of pillars separated by trenches;
Forming a liner layer covering the sidewalls and the trench of the pillar;
Forming a sacrificial oxide film gap-filling the trench on the liner film;
Recessing the sacrificial oxide film;
Forming a sacrificial polysilicon film on the entire surface including the recessed sacrificial oxide film;
Forming a single side contact mask on the sacrificial polysilicon layer;
Etching the sacrificial polysilicon layer to form a single side structure;
Etching the sacrificial oxide layer under the single side structure to form a recessed single side structure; And
Etching a portion of the liner layer to form an open portion for opening a portion of one sidewall of the body
≪ / RTI >
Etching the substrate to form a plurality of pillars separated by trenches;
Forming a liner layer covering the sidewalls and the trench of the pillar;
Forming a sacrificial oxide film gap-filling the trench on the liner film;
Recessing the sacrificial oxide film;
Forming a sacrificial polysilicon film on the entire surface including the recessed sacrificial oxide film;
Forming a single side contact mask on the sacrificial polysilicon layer;
Etching the sacrificial polysilicon layer to form a single side structure;
Etching the sacrificial oxide layer under the single side structure to form a recessed single side structure;
Etching a portion of the liner layer to form an open portion for opening a portion of one sidewall of the body; And
Forming a buried bit line connected to the body through the open part;
≪ / RTI > Etching the substrate to form a plurality of pillars separated by trenches;
Forming a liner layer covering the sidewalls and the trench of the pillar;
Forming a plug partially filling the trench on the liner layer;
Forming a sacrificial oxide film gap-filling the trench on the plug;
Recessing the sacrificial oxide film;
Forming a sacrificial polysilicon film on the entire surface including the recessed sacrificial oxide film;
Forming a single side contact mask on the sacrificial polysilicon layer;
Etching the sacrificial polysilicon layer to form a single side structure;
Etching the sacrificial oxide layer under the single side structure to form a recessed single side structure;
Etching a portion of the liner film adjacent the upper portion of the plug to form an open portion for opening a portion of one sidewall of the body; And
Forming a buried bit line connected to the body through the open part on the plug;
≪ / RTI >

KR1020110086760A 2011-08-29 2011-08-29 Method for fabricating semiconductor device using single-side-contact KR20130023766A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269746B2 (en) 2013-11-12 2016-02-23 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269746B2 (en) 2013-11-12 2016-02-23 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same
US9431458B2 (en) 2013-11-12 2016-08-30 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same

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