KR20130019267A - Memory cell string stack with common body and memory array using the same - Google Patents

Abstract

PURPOSE: A memory cell string stack sharing a body and a memory array using the same are provided to reduce an area occupied by a cell by forming a body connection member and a control electrode between the memory cell string stacks. CONSTITUTION: A semiconductor stack has a preset length in a first horizontal direction. Gate insulation layer stacks(7) include charge storage layers(5). A plurality of charge storage layers are separated in the first horizontal direction. A plurality of control electrodes(8a) are formed on each gate insulation layer stack. An isolation insulation layer is filled between the control electrodes and between the gate insulation layer stacks.

Description

Stacking memory cell strings and memory arrays using the same body {MEMORY CELL STRING STACK WITH COMMON BODY AND MEMORY ARRAY USING THE SAME}

The present invention relates to a nonvolatile memory, and more particularly, to a memory cell string stack and a memory array using the same stacked vertically.

Recently, the demand for nonvolatile memory is rapidly increasing in home appliances and portable electronic devices.

In particular, the density of NAND nonvolatile memory is required to increase continuously with the development of IT technology. The degree of integration of the NAND nonvolatile memory is highly dependent on the degree of integration of the cell devices. In recent years, gate lengths of cell devices have been reduced to 50 nm or less, and memory capacities have reached tens of gigabytes. Therefore, the conventional non-volatile memory device having a flat floating channel structure having a conductive floating gate is a problem that the short channel effect is a big problem, and the manufacturing process is also very difficult. The technology having a gate length of 50 nm or less requires expensive equipment or processes and thus increases manufacturing costs. In the future, the gate length must be reduced to improve the density, and there is a need for an alternative to cope with this situation.

In order to increase the density of memory cell devices, a SONOS-based flash memory cell using an insulating storage node such as a nitride film instead of a memory cell having a floating gate has been considered. In addition, nano-floating gate memory (NFGM) cells using nano dots or nano crystals as charge storage nodes have been considered. When a memory cell is implemented by using a charge storage node such as a nitride film or a nano dot in a conventional flat channel structure, the miniaturization characteristic is improved as compared with the case of using a floating gate of conductive polysilicon. However, even when the improved charge storage node is used, the characteristics of the gate length of 40 nm or less are greatly reduced due to the short channel effect, and thus the limit of the reduction is impossible.

SONOS or TANOS (TaN-AlO-SiN-) with an asymmetric source / drain structure in a flat channel structure to suppress short channel effects and reduce threshold voltages caused by reducing the gate length of the cell device to 40 nm or less. Oxide-Si) cell devices have been published by Samsung Electronics (see Non-Patent Document 1). The impurity doped region corresponding to the source / drain is formed on one side of the gate of the cell device, but the impurity doped region for the source / drain is not formed on the other side. This structure suppresses short channel effects by forming a virtual source / drain into an inversion layer formed by fringing electric fields from neighboring control electrodes instead of impurity doping. Although the reduction characteristics are improved compared to SONOS cell devices having flat channels that form both sources / drains by conventional impurity doping, one of the two sources / drains of the cell devices is formed to overlap the control electrode. Short channel effects are still seen at the following channel lengths and ultimately face the miniaturization limitation of flat channel structures.

One way to increase the degree of integration while reducing manufacturing costs is to form cell elements or cell strings vertically. In Patent Document 1, a trench is formed, and a tunneling insulating film, a floating gate, a blocking insulating film, and a control electrode are sequentially formed in the trench to implement the trench. Sources were formed in the semiconductor region near the bottom of the trench, and drains in the semiconductor region near the top of the trench, respectively. In this structure, only one vertical cell element is formed to substantially increase the memory capacity, and due to structural problems, it is impossible to form multiple cell elements vertically.

In a recently published paper (Non-Patent Document 2), in order to solve the problem of Patent Document 1, several cells and two switch elements are disposed vertically. According to this, although the degree of integration can be increased, the write time is rather slow, and in particular, the erase time is slow. In addition, the retention characteristics are poor. In the manufacturing process, an insulating layer is formed for electrical insulation between control layers of various layers stacked vertically. In this case, when forming a via via of a circle to form a string, it is necessary to continue to etch alternately between the control electrode made of polysilicon and the insulating layer made of silicon oxide. It can be difficult and time consuming. In addition, in order to form a tube-shaped body vertically, only the bottom of the via hole may be etched, leaving a gate insulating film or a blocking insulating film formed on the vertical sidewall of the via hole so that the bottom is electrically connected to the semiconductor region. At this time, the insulating film on the sidewall may be damaged, which may result in deterioration of the memory cell characteristics and, in turn, lower the yield. The electrical contact and wiring of the source region formed at the bottom of the via hole from the upper surface of the via hole may require a large mask as well as overcoming a large step. In short, there are many difficulties in terms of fairness.

Therefore, there is a continuing need for the development of a new structure of high-integration / high performance nonvolatile memory device that can solve the problems of the existing published devices.

Patent Document 1: US Patent No. 5,739,567 (Highly compact memory device with nonvolatile vertical transistor memory cell) 1998. 4. 14.

[Non-Patent Document 1] K. T. Park et al., A 64-cell NAND flash memory with asymmetric S / D structure for sub-40 nm technology and beyond, in Technical Digest of Symposium on VLSI Technology, p. 24, 2006 [Non-Patent Document 2] Y. Fukuzumi et al., Optimal integration and characteristics of vertical array devices for ultra-high density, bit-cost scalable flash memory, IEDM Tech. Dig., Pp. 449-452, 2007

The present invention is to solve the problems of the prior art, when forming a cell string stack by vertically stacking a cell string formed with a plurality of memory cell elements in a horizontal first direction with an insulating layer interposed, one side of the stack The purpose of the present invention is to provide a memory cell string stack that shares a body so that a neighboring stack, a predetermined stack, or an entire stack can be erased at the same time as in a planar structure by forming a conductive fence or pillar connecting the bodies of the upper and lower cell strings. have.

In addition, another object is to provide a memory array in which a plurality of vertically stacked memory cell string stacks share a body and are formed in a plurality in a horizontal second direction.

In order to achieve the above object, the memory cell string stack according to the present invention comprises a semiconductor stack formed such that an insulating film and a semiconductor layer are alternately repeatedly stacked on the semiconductor substrate and having a predetermined length in a horizontal first direction; Gate insulating layer stacks including a plurality of charge storage layers spaced apart from each other by a predetermined distance on one side of the semiconductor stack in a first direction; A plurality of control electrodes formed on the gate insulating film stacks; And a separation insulating layer filled between the control electrodes and between the gate insulating layer stacks, wherein a body connection member is further formed on the other side of the semiconductor stack to vertically connect the stacked semiconductor layers. .

In addition, the body connection member is a feature of the memory cell string stack according to the present invention that the fence or pillar shape.

In addition, the body connection member is another feature of the memory cell string stack according to the present invention that is electrically connected to the semiconductor substrate.

The body connection member is another feature of the memory cell string stack according to the present invention that the body connection member is electrically connected to a metal wire formed on the body connection member.

In addition, the semiconductor layer of the semiconductor stack is larger than the insulating film, so that the protruded side surface in which the gate insulating film stacks are formed is another feature of the memory cell string stack according to the present invention.

In addition, the semiconductor layer of the semiconductor stack is another feature of the memory cell string stack according to the present invention that protrudes in a curved structure on the side where the gate insulating film stacks are formed.

Each gate insulating film stack is formed of a tunneling insulating film, the charge storage layer, and a blocking insulating film on a curved structure of the semiconductor layer, and the charge storage layer is a conductive thin film, an insulating film having traps, and nano-sized dots. Is formed of any one of the dispersed insulating films, which is another feature of the memory cell string stack according to the present invention.

Memory cell elements are formed at positions crossing the control electrodes along the first direction of the semiconductor layer, and the memory cell elements are fringing fields from the control electrodes in the semiconductor layer. Another feature of the memory cell string stack according to the present invention is that the memory cell string is connected to each other by an inversion layer or an accumulation layer formed by the memory cell string.

Memory cell elements are formed at positions crossing the control electrodes along the first direction of the semiconductor layer, and the memory cell elements are source / drain as an impurity doping layer in the semiconductor layer between the control electrodes. Is formed to be connected to each other to form a memory cell string, which is another feature of the memory cell string stack according to the present invention.

Meanwhile, in the memory array according to the present invention, a plurality of semiconductor stacks in which insulating films and semiconductor layers are alternately repeatedly stacked on a semiconductor substrate, each having a predetermined length in a horizontal first direction, and spaced apart a predetermined distance in a horizontal second direction ; Gate insulating layer stacks including a plurality of charge storage layers spaced apart at a predetermined distance along the first direction on one side of each semiconductor stack facing each other between the semiconductor stacks; A plurality of control electrodes formed in the spaced spaces between the semiconductor stacks on the gate insulating film stacks; And a separation insulating film filled between the control electrodes and between the gate insulating film stacks, wherein a body connection member is further formed on the other side of each semiconductor stack to vertically connect the stacked semiconductor layers. do.

The body connection member may be formed in a spaced space between the semiconductor stacks between the gate insulating film stacks, the control electrodes, and the separation insulating film, or may be formed together with the insulating film with one or more pillars. It is another feature of the memory array according to the present invention.

The body connecting member may be formed of a semiconductor material doped with the same impurity type as the semiconductor layer and the semiconductor substrate.

In addition, the body connection member is another feature of the memory array according to the present invention that is electrically connected to the semiconductor substrate.

At least one well having a different impurity type from the semiconductor substrate is formed in the semiconductor substrate.

The body connection member may be formed of a semiconductor material having the same impurity type as the semiconductor layer and the respective wells, and at least one body connection member may be electrically connected to each of the wells. .

The body connecting member may be formed of a semiconductor material doped with the same impurity type as the semiconductor layer, and the semiconductor substrate may be doped with a different impurity type from the semiconductor layer.

The body connection member is another feature of the memory array according to the present invention that the body connection member is electrically connected to a metal wire formed on the body connection member.

In addition, an insulating film is further formed between the body connection member and the semiconductor substrate.

The body connection member may be formed by alternately stacking the semiconductor layer with a semiconductor material layer having an etch rate or dielectric constant different from that of the semiconductor layer instead of the insulating layer in each of the semiconductor stacks. do.

The semiconductor layer may be silicon (Si), and the semiconductor material layer having a different etching rate from that of the semiconductor layer may be silicon germanium (SiGe).

By the above configuration, the memory cell string stack according to the present invention is formed on one side of the stack, the memory array by forming a body connecting member for vertically connecting the bodies of the cell strings stacked in three dimensions between the cell stack, respectively As a planar structure, a predetermined stack composed of modules such as a stack unit or a neighboring stack can be erased at once, and the entire stack formed as an array can be erased at the same time, thereby increasing the erase speed even in a 3D stack structure.

In addition, since the body connection member and the control electrode are formed to be shared between the adjacent memory cell string stacks, the area occupied by one cell is greatly reduced.

1 is a plan view of a portion of a memory array using a memory cell string stack according to an embodiment of the present invention, and any of a plurality of cell string stacks formed and stacked in the z-axis direction perpendicular to the xy plane to show an internal structure. It is sectional drawing cut horizontally in the semiconductor layer.
FIG. 2 is a perspective view corresponding to portion C of FIG. 1 and illustrates a memory cell string stack and a memory array structure according to an embodiment of the present invention.
3 and 4 are perspective views corresponding to part B of FIG. 1, which illustrate an example of a memory array structure using a memory cell string stack according to an embodiment of the present invention, and differs only in the configuration of a body connection member. There is this.
FIG. 5 is a structure similar to that of FIG. 2, except that only the impurity type (conductive type) doped into the semiconductor substrate is different.
FIG. 6 is a structure similar to that of FIG. 2, except that there is an insulating film between the body connection member and the semiconductor substrate.
7 to 10 are cross-sectional views taken along the y-direction of FIG. 2 to show respective embodiments of the semiconductor stack and the gate insulating film stack according to the present invention.
FIG. 11 is a layout (top view) illustrating a specific embodiment of a structure, contacts, and wiring of a memory array according to the present invention.
12 is a cross-sectional view taken along the line XX ′ of FIG. 11.
FIG. 13 is a cross-sectional view taken along the line YY ′ of FIG. 11.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a plan view of a portion of a memory array using a memory cell string stack according to an embodiment of the present invention, and any of a plurality of cell string stacks formed and stacked in the z-axis direction perpendicular to the xy plane to show an internal structure. It is sectional drawing cut horizontally in the semiconductor layer.

In FIG. 1, region A represents an area occupied by one memory cell element, and regions B and C each show a part of the structure of an embodiment of a memory array described later, and the portion ' F 'represents the minimum line width for a given technique.

Hereinafter, an embodiment according to the present invention will be largely divided into a memory cell string stack and a memory array.

Regarding Cell String Stacks Example ]

First, in the cell string stack according to an embodiment of the present invention, as shown in FIGS. 1 and 2, the insulating film 2 and the semiconductor layer 3 are alternately repeatedly stacked on the semiconductor substrate 1, and the horizontal first layer is stacked. A semiconductor stack 41 or 42 formed to have a predetermined length in a direction (eg, the x direction); Gate insulating layer stacks 7 including a plurality of charge storage layers 5 vertically spaced apart at a predetermined distance along the first direction (x direction) on one side of the semiconductor stack; A plurality of control electrodes 8a formed on each of the gate insulating layer stacks; And a separation insulating film 9 filled between the control electrodes 8a and between the gate insulating film stacks 7 and stacked on the other side of the semiconductor stack 41 or 42. It is characterized in that the body connecting member 8b for vertically connecting 3) is further formed.

In this case, the semiconductor layer 3 is preferably formed of a single crystal semiconductor material, but may be formed of a polycrystalline or amorphous semiconductor material, and the specific impurities are weakly doped to function as a p-type or n-type semiconductor body.

As shown in FIG. 2, the semiconductor stack 41 or 42 is a plurality of semiconductor layers 3 vertically and repeatedly stacked with an insulating film 2 such as an oxide film interposed on the semiconductor substrate 1. It is formed to have a predetermined length in the horizontal first direction (x direction).

In addition, as shown in FIG. 2, the gate insulating layer stacks 7 are formed on the side surface of the semiconductor stack 41 or 42 at a predetermined distance along the first direction (x direction) and are vertically formed. And a charge storage layer 5, and may be formed from the semiconductor layer 3 as a tunneling insulating film 4 / charge storage layer 5 / blocking insulating film 6.

Here, the charge storage layer 5 may be formed of any one of not only a nitride layer but also a conductive thin film, an insulating film having a trap, and an insulating film in which nano-sized dots are dispersed.

7 to 10 illustrate a shape of the semiconductor stack 41 or 42 and the gate insulating film stack 7 according to the present invention.

In the semiconductor stack 41 or 42 according to the present invention, as shown in FIG. 7, the insulating film 2 and the semiconductor layer 3 may be repeatedly stacked vertically with the same width, but as shown in FIGS. 8 to 10. Each of the semiconductor layers 3 may have a structure protruding on the side where the gate insulating film stacks 7 ′ and 7 ″ are formed by repeatedly stacking the semiconductor layer 3 in a larger width than the insulating film 2 ′.

In addition, in the case where each semiconductor layer has a protruding structure, it is preferable that the semiconductor insulating layer has a curved structure on the side where the gate insulating film stack 7 ″ is formed, as shown in FIG. 10. As described above, when the tunneling insulating film 4 '/ charge storage layer 5' / blocking insulating film 6 'is formed from the curved structure of the semiconductor layer 3', the semiconductor tunneling insulating film 4 "is in contact with the programming. The electric field on the curved surface of the layer 3 'can be concentrated to facilitate charge injection into the charge storage layer 5', and the charge storage layer 5 'can be drilled through the blocking insulating film 6' during erasing. There is an advantage that can effectively prevent the reverse tunneling charge coming into the.

In addition, the gate insulating film stack 7 according to the present invention, as shown in Figs. 2, 7 and 8, the tunneling insulating film 4, 4 '/ charge storage layer 5 on one side of the semiconductor stack 41 or 42 5 ') / blocking insulating films 6 and 6', but as shown in FIGS. 9 and 10, the tunneling insulating film 4 "is formed only on the protruding semiconductor layer 3 with a thermal oxide film and the like. The portion may be formed in a structure in which the charge storage layer 5 '/ blocking insulating film 6' are stacked together.

In addition, the control electrodes 8a are formed on each gate insulating layer stack 7 by using a conductive material (metal or impurity doped semiconductor material), as shown in FIG. 2, and thus the length direction of the semiconductor stack 41 or 42. Each of them is perpendicular to (x direction).

In addition, the isolation insulating layer 9 has a configuration filled vertically between the control electrodes 8a and the gate insulating layer stacks 7 as shown in FIG. 2.

In the embodiment of the present invention, the memory cell elements are formed at positions crossing the control electrodes 8a along the first direction (x direction) of the semiconductor layer 3.

In this case, as shown in FIG. 2, the source 3a / drain 3b is formed as an impurity doping layer in the semiconductor layer 3 between the control electrodes 8a and connected to each other to form a memory cell string. Is achieved.

However, the memory cell elements are formed not by the impurity doped layers 3a and 3b as shown in FIG. 2 but by the fringing field from the control electrodes 8a adjacent to the semiconductor layer 3. A virtual source / drain may be formed of an inversion layer or an accumulation layer, and may be connected to each other to form a memory cell string.

As described above, a plurality of memory cell strings formed along the first direction (x direction) of each semiconductor layer 3 are stacked vertically with the insulating layer 2 interposed therebetween, thereby being referred to as a cell stack (hereinafter, referred to as a “cell stack”). Will form. That is, one semiconductor stack 41 or 42 constitutes one cell stack.

On the other side of the semiconductor stack 41 or 42 (that is, the side where the memory cell is not formed), a body for vertically connecting the plurality of stacked semiconductor layers 3 vertically as shown in FIG. 2. The connecting member 8b is formed.

Here, the body connection member 8b may have a fence shape formed in a first direction (x direction) along an opposite side of the semiconductor stack 41 or 42, as shown in FIG. 2. The pillars (not shown) may be perpendicular to a portion of the side surface of the side in which the memory cells are not formed.

In addition, although the body connecting member 8b may be any conductive material, the body connecting member 8b may be formed of the same material as the control electrodes 8b. This is because the manufacturing process is simplified.

As a specific example, the material of the body connection member 8b may be a semiconductor material that is doped with the same impurity type (p type or n type) as the semiconductor layer 3 and the semiconductor substrate 1 (ie, has the same conductivity type). In this case, the bodies of all the memory cells of the cell stack are shared by each semiconductor layer 3 and the semiconductor substrate 1 of the semiconductor stack 41 or 42 with the same conductive semiconductor (for example, p-type semiconductor). And it is connected to the semiconductor substrate (1).

Here, the semiconductor material constituting the body connecting member 8b may be the same semiconductor material (eg, silicon), but as shown in FIG. 3, two semiconductor material layers 2a and 3 having different etching rates or dielectric constants may be formed. It may also be formed by alternately laminating repeatedly. As shown in FIG. 3, in the semiconductor stack (eg, reference numeral 41), instead of the insulating layer 2, the stacked shape is replaced by a semiconductor material layer 2a having an etch rate or a dielectric constant different from that of the semiconductor layer 3. It may be the same as formed by repeated lamination alternately with the layer (3).

In this case, specific examples of the two semiconductor material layers 2a and 3 having different etching rates may be silicon (Si) and silicon germanium (SiGe).

The embodiment of the material of the body connecting member 8b is not limited to the above examples, but may be anything as long as it can be electrically connected to the upper and lower semiconductor layers 3 and the semiconductor substrate 1 of the semiconductor stack.

Furthermore, the body connecting member 8b may be electrically connected to the upper and lower semiconductor layers 3 of the semiconductor stack, and may not necessarily be electrically connected to the semiconductor substrate 1. This is because the body contact can be made on the body connection member 8b in addition to the semiconductor substrate 1.

Therefore, as shown in FIG. 6, the body connection member 8b may have an insulating film 2b between the semiconductor substrate 1 and an impurity type different from that of the semiconductor substrate 1 as shown in FIG. 5. That is, it may be formed of a semiconductor material having the opposite conductivity type. In the former case, the insulating film 2b is used to insulate the body, and in the latter case, the body connection member 8b and the semiconductor substrate 1 are insulated by the pn junction of the semiconductor.

Although the accompanying drawings illustrate that the cell string is formed along one side of the semiconductor stack (eg, 41), the cell string may also be formed along the opposite side, in which case the body connecting member may have a length of the semiconductor stack. It is formed perpendicular to any one of the cross-section in both directions.

As described above, the body connection member 8b is formed perpendicularly to a portion of the side surface of the semiconductor stack (for example, 41) where no memory cells are formed, thereby electrically connecting the upper and lower semiconductor layers 3 to be formed in the semiconductor stack. By sharing the body of all the memory cells, there is an advantage that can be controlled by a single body contact, it is possible to erase all the cells at the same time.

[Regarding Memory Array Example ]

Next, a memory array using an embodiment of the memory cell string stack will be described.

1 and 2, the insulating film 2 and the semiconductor layer 3 are alternately repeatedly stacked on the semiconductor substrate 1, respectively, and have a predetermined length in the horizontal first direction (for example, the x direction). A plurality of semiconductor stacks 41 and 42 spaced apart by a predetermined distance in a horizontal second direction (eg, y direction); Gate insulating layer stacks including a plurality of charge storage layers 5 formed on the one side of each of the semiconductor stacks 41 and 42 facing each other and spaced apart from each other along the first direction (x direction) and formed in plurality. 7); A plurality of control electrodes (8a) formed in the spaced space between the semiconductor stacks (41, 42) on each gate insulating film stack (7); And a separation insulating film 9 filled between the control electrodes 8a and between the gate insulating film stacks 7 and stacked on the other side of each of the semiconductor stacks 41 and 42. It is characterized in that the body connecting member 8b is further formed which vertically connects the layer 3.

The basic technical concept of the present embodiment is to form a memory array with a plurality of semiconductor stacks 41 and 42 having a predetermined length in a horizontal first direction (x direction) spaced a predetermined distance in a horizontal second direction (y direction). The plurality of gate insulating layers may be disposed between the plurality of semiconductor stacks 41 and 42 in the horizontal second direction (y direction) and once with the isolation insulating layer 9 interposed therebetween in the horizontal first direction (x direction). It is characterized by repeating the structure filled with the stacks 7 and the control electrodes 8a and the other once filled with the body connecting member 8b. It is to implement a memory array capable of controlling all the semiconductor layers 3 stacked in the stacks to a predetermined body contact.

The body connection member 8b is disposed in a spaced space between the gate insulating film stacks 7, the control electrodes 8a, and the isolation insulating film 9 among the plurality of semiconductor stacks 41 and 42. As shown in FIG. 2, it may be filled with the fence shape 8b or filled with one or more pillars (not shown) together with the insulating film. When the body connection member 8b has a columnar shape, two or more semiconductor stacks may be formed at one end of the plurality of semiconductor stacks 41 and 42 in the longitudinal direction.

In addition, the body connection member 8b may be formed of the same material as the control electrodes 8a as shown in FIG. 2. This is preferable because the manufacturing process can be simplified.

In addition, the bodies of all the cells constituting the memory array may be connected to the semiconductor substrate 1 through the body connection member 8b (first embodiment), and the bodies of the memory cells formed in certain semiconductor stacks may be connected. (Second embodiment), only bodies of memory cells formed in each semiconductor stack may be connected (third embodiment).

<First Example >

In order to connect the bodies of all the cells constituting the memory array on the semiconductor substrate 1, the body connecting member 8b may be formed of a conductive material (metal or the like), but the semiconductor layer 3 constituting each semiconductor stack 3 may be formed. ) And the semiconductor substrate 1 may be doped with the same impurity type to form a semiconductor material having the same conductivity type. That is, all of the semiconductor substrate 1, the body connecting member 8b, and the semiconductor layer 3 constituting each semiconductor stack may be formed of the same p-type semiconductor material or n-type semiconductor material.

The semiconductor material having the same conductivity type may be the same kind of semiconductor (eg, silicon), but is composed of two or more semiconductors (eg, silicon and silicon germanium) having different etching rates or dielectric constants, but the same conductivity type. It may be. As a specific example of the latter, the semiconductor substrate 1 and the semiconductor layer 3 constituting each semiconductor stack are all p-type silicon, and the body connecting member 8b has a structure in which p-type silicon germanium and p-type silicon are alternately vertically stacked. It can be formed as.

<2nd Example >

In order to connect only the bodies of memory cells formed in certain semiconductor stacks, as shown in FIGS. 3 and 4, the second conductive type (eg, the opposite) to the semiconductor substrate 1a having the first conductive type (for example, p-type) may be used. at least one well having an n-type, or at least one second well having a first conductivity type (eg, p-type) in each well, and then connecting a plurality of bodies Some of the members 8b1 and 8b2 are formed of a conductive material (metal or the like) or a semiconductor material having the same conductivity type as the semiconductor layer 3 and the well 1b or the second well (not shown), Two or more predetermined body connecting members (eg, 8b1 and 8b2) may be electrically connected to the well 1b or the second well (not shown). Of course, one body connecting member may be electrically connected to each well.

FIG. 4 is similar to FIG. 3, but the body connection members 8b1 'and 8b2' are not formed of a single material, but may be formed by stacking two semiconductors having different etching rates or dielectric constants. Shows. Specifically, the body connection members 8b1 'and 8b2' have the same stacked shape as the semiconductor stacks 41 to 46, but instead of the insulating film 2 of each semiconductor stack, the etch rate or dielectric constant The semiconductor layer 3 may be repeatedly stacked with another semiconductor material layer 2a. If the semiconductor layer 3 is silicon (Si), the semiconductor material layer 2a having an etch rate or a dielectric constant different from that of the semiconductor layer may be silicon germanium (SiGe).

<Third Example >

In order to connect only the bodies of memory cells formed in each semiconductor stack, as shown in FIG. 5, the body connection member 8b is doped with the same impurity type as the semiconductor layer 3, and is formed of a semiconductor material having the same conductivity type, and the semiconductor The substrate 1 is doped with a different impurity type from the semiconductor layer 3 to form an opposite conductivity type, so that a pn junction is formed between the body connection member 8b and the semiconductor substrate 1, and depletion is formed at these interfaces. As a region, each body connecting member 8b may be insulated from the semiconductor substrate 1, or as shown in FIG. 6, a separate insulating film 2b may be further added between the body connecting member 8b and the semiconductor substrate 1. It may be formed and implemented.

Finally, referring to Figs. 11 to 13, the contact and wiring of the memory array according to the above embodiment will be briefly described.

As shown in FIG. 11, each semiconductor layer 3 of each semiconductor stack is spaced apart at a distance in a first direction (eg, the XX ′ direction of FIG. 11 and the x direction of FIG. 2) at one end thereof, and the second direction (for example, , YY 'direction of FIG. 11, and y direction of FIG. 2), are electrically connected to any one of the plurality of bit lines BL, grounded through a selection transistor at the other end, and the control electrodes 8a are Except that formed in one or two second directions close to the lines BL, each of the plurality of word lines WL formed in the second direction is electrically connected to the bit lines BL. At least one of the plurality of bit selection lines BSL 15 and 21 formed in the first direction may be spaced apart from each other by a predetermined distance in the second direction, respectively. Each of the body contact lines 29 is electrically connected to each other.

Here, at both ends of each of the bit lines BL and the semiconductor layers 3 connected to the selection transistors, as shown in FIG. 12, a highly doped connection impurity doping layer 3c may be further formed. Can be.

In FIG. 11, a portion in which each bit line BL is electrically connected to the semiconductor layers 3 stacked on the same layer has a contact mark 14 in a solid line on each bit line BL. A portion of the semiconductor layer 3 connected to the drain 24 of the select transistor and the predetermined wiring 19 under the BL has a contact display 13 as a dotted line on each bit line BL. Unexplained reference numeral 28 denotes a contact connecting the body contact line 29 and the body connecting member 8b.

12 is a cross-sectional view taken along the line XX 'of FIG. 11, and FIG. 13 is a cross-sectional view taken along the line YY ′ of FIG. 11.

1, 1a: semiconductor substrate
1b: well
2, 2b, 26, 27: insulating film
3: semiconductor layer
3a: source of cell
3b: drain of the cell
4, 4 '. 4 ": Tunneling Insulation
5, 5 ': charge storage layer
6, 6 ': blocking insulating film
7, 7 ', 7 "; gate insulating film stack
8a, 8a ', 8a ": control electrode
8b, 8b ', 8b ", 8b1, 8b2: body connecting member
9: Separation insulation film
10: wordline
12, 20: bit line
13: Drain contact between semiconductor layer and select transistor
14: semiconductor layer and bitline contact
15, 21: bit select line
16: Source and Ground Line Contacts of Selected Transistors
17: gate of select transistor
18: Drain and Wiring Contact of Select Transistor
22: source of select transistor
23: gate insulating film of select transistor
24: drain of select transistor
25: insulating film
41, 42, 43, 44, 45, 46: semiconductor stack

Claims (19)

A semiconductor stack on which the insulating film and the semiconductor layer are alternately repeatedly stacked on the semiconductor substrate and formed to have a predetermined length in a horizontal first direction;
Gate insulating layer stacks including a plurality of charge storage layers spaced apart from each other by a predetermined distance on one side of the semiconductor stack in a first direction;
A plurality of control electrodes formed on the gate insulating film stacks; And
A separation insulating film filled between the control electrodes and between the gate insulating film stacks,
And a body connection member for vertically connecting the stacked semiconductor layers on the other side of the semiconductor stack.
The method of claim 1,
And the body connecting member has a fence or column shape.
3. The method according to claim 1 or 2,
And the body connection member is electrically connected to the semiconductor substrate.
3. The method according to claim 1 or 2,
And the body connection member is electrically connected to a metal line formed on the body connection member.
3. The method according to claim 1 or 2,
And the semiconductor layer of the semiconductor stack is larger than the insulating film so as to protrude from a side surface on which the gate insulating film stacks are formed.
The method of claim 5, wherein
And the semiconductor layer of the semiconductor stack protrudes in a curved structure on a side surface on which the gate insulating layer stacks are formed.
The method according to claim 6,
Each gate insulating film stack is formed of a tunneling insulating film / the charge storage layer / blocking insulating film on the curved structure of the semiconductor layer,
The charge storage layer is a memory cell string stack, characterized in that formed of any one of a conductive thin film, an insulating film having a trap, an insulating film in which nano-sized dots are dispersed.
The method of claim 7, wherein
Memory cell elements are formed at positions crossing the control electrodes along the first direction of the semiconductor layer,
The memory cell elements may be connected to each other by an inversion layer or an accumulation layer formed by a fringing field from the control electrodes in the semiconductor layer to form a memory cell string. Memory cell string stack.
The method of claim 7, wherein
Memory cell elements are formed at positions crossing the control electrodes along the first direction of the semiconductor layer,
And the memory cell elements are connected to each other by forming a source / drain in the semiconductor layer between the control electrodes as an impurity doping layer and forming a memory cell string.
A plurality of semiconductor stacks each having an insulating layer and a semiconductor layer repeatedly alternately stacked on the semiconductor substrate, the semiconductor stacks having a predetermined length in a horizontal first direction, spaced a predetermined distance in a horizontal second direction;
Gate insulating layer stacks including a plurality of charge storage layers spaced apart at a predetermined distance along the first direction on one side of each semiconductor stack facing each other between the semiconductor stacks;
A plurality of control electrodes formed in the spaced spaces between the semiconductor stacks on the gate insulating film stacks; And
A separation insulating film filled between the control electrodes and between the gate insulating film stacks,
And a body connection member for vertically connecting the stacked semiconductor layers on the other side of each of the semiconductor stacks.
11. The method of claim 10,
The body connection member may be formed in a space between the semiconductor stacks between the gate insulating film stacks, the control electrodes, and the separation insulating film, in a fence shape, or by filling the insulating film with one or more pillars. Memory array.
The method of claim 10 or 11,
The body connecting member is formed of a semiconductor material doped with the same impurity type as the semiconductor layer and the semiconductor substrate.
The method of claim 10 or 11,
And the body connection member is electrically connected to the semiconductor substrate.
The method of claim 10 or 11,
One or more wells having different impurity types from the semiconductor substrate are formed in the semiconductor substrate,
And the body connection member is formed of a semiconductor material having the same impurity type as the semiconductor layer and each well, and at least one body connection member is electrically connected to each well.
The method of claim 10 or 11,
The body connection member is formed of a semiconductor material doped with the same impurity type as the semiconductor layer,
And the semiconductor substrate is doped with a different impurity type from the semiconductor layer.
The method of claim 10 or 11,
And the body connection member is electrically connected to a metal line formed on the body connection member.
The method of claim 10 or 11,
And an insulating film is formed between the body connection member and the semiconductor substrate.
The method of claim 10 or 11,
The body connection member may be formed by alternately stacking the semiconductor layer with a semiconductor material layer having an etch rate or dielectric constant different from the semiconductor layer instead of the insulating layer in each semiconductor stack.
The method of claim 18,
The semiconductor layer is silicon (Si),
The semiconductor material layer having a different etching rate from the semiconductor layer is silicon germanium (SiGe).

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