KR20130013785A - Wake-up receiver with false wake-up preventions circuit and tranceiver comprising the same - Google Patents

Abstract

PURPOSE: A wake-up receiver including an interference wave removing function and a transceiver including the same are provided to minimize power consumption by not reacting to an interference wave having large power. CONSTITUTION: Two or more edge detectors separately detect a rising edge and a falling edge of a digital signal and the rising edge and the falling edge of one or more delay signals. One or more state machines synchronize the rising edge and the falling edge of the digital signal with the rising edge and the falling edge of the delay signals respectively. The state machines determine whether a state defined by the digital signal and the delay signals is matched with a predefined state.

Description

WAKE-UP RECEIVER WITH FALSE WAKE-UP PREVENTIONS CIRCUIT AND TRANCEIVER COMPRISING THE SAME}

The present invention relates to a wake-up receiver having a jamming function and a transceiver comprising the same.

In the case of a communication system including a battery operated transceiver such as a wireless sensor network, a transceiver including a wake-up receiver is generally used to increase the life of a terminal.

The background technology of the present invention is disclosed in Republic of Korea Patent Publication No. 10-2010-0138076 (2010.12.31).

1 is a block diagram schematically illustrating a configuration of a transceiver having a conventional wake up function.

Referring to FIG. 1, a transceiver 10 having a wake up function includes a wake up receiver 11 and a data transceiver 12.

The wake up receiver 11 detects a wake up signal, and the data transceiver 12 transmits and receives actual data. When the wake-up signal is received at a specific time, the wake-up receiver 11 detects this and wakes up the data transceiver 12. Accordingly, the data transceiver 12 can transmit and receive data.

In this wake-up scheme, methods for minimizing power consumption have been proposed. One of them is to operate the wake up circuit periodically in synchronization with a specific reference frequency. However, the power consumption of the wake-up receiver itself is the most important factor. To reduce the power consumption of the wake-up receiver itself, a passive power detector using a low power Schottky diode or MOSFET is used. However, since the passive power detector has a wide pass band, malfunction may occur when a jamming signal having amplitude modulation exists. Since the malfunction due to the disturbing wave unnecessarily changes the terminal to the operating state, even if the power consumption of the wake-up circuit itself is small, the unnecessary power consumption is increased. This will result in a shortened battery life.

FIG. 2 is a block diagram showing the structure of a wake-up receiver to which a passive power detector is commonly used (Reference: Kolinko, P .; Larson, LE ;, "Passive RF Receiver Design for Wireless Sensor Networks," Microwave Symposium, 2007. IEEE / MTT-S International, vol., No., Pp. 567-570, 3-8 June 2007).

Referring to FIG. 2, the wake-up receiver 20 may include: an RF filter 21 for removing impedance matching and interference signal of an antenna, removing a carrier wave from an amplitude modulated RF signal, detecting a modulated signal, and A baseband filter 23, an amplifier 24, and an analog-to-digital converter (ADC) 25, which remove high frequency components and jamming signals that are not removed from the RF filter 21, are included.

The wake up receiver 20 outputs a signal for waking up the data receiver that actually transmits and receives data.

2 shows a graph showing the signal before input to the RF filter 21 and the output signal of the passive power detector 22 in the time domain and the frequency domain. Referring to this, the passive power detector 22 is amplitude modulated. The modulated signal f _mod is detected by removing a _carrier f from the received RF signal.

Referring to FIG. 2, when looking at the characteristics of the amplitude modulated RF signal, in the time domain, the carrier (f _carrier ) has a characteristic that the amplitude changes according to the amplitude modulated signal (f _mod ), and in the frequency domain, the carrier (f _carrier ) It has a characteristic of having a frequency component that differs by the frequency of the amplitude modulated signal f _mod in relation to frequency. When the amplitude modulated signal f _mod passes through the passive power detector 22, the carrier f _carrier is attenuated, and only the amplitude modulated signal f _mod is detected. In general, the passive power detector 22 detects an amplitude modulated signal f _mod almost independent of a carrier f _carrier .

In such a structure, the narrow band RF filter 21 can be used to effectively prevent the passive power detector 22 having the wide band characteristic from responding to the jamming signal. However, in general, since the RF filter 21 has a very narrow band characteristic as shown in FIG. 3, it is almost impossible to select only the channel signals f _carrier1 and f _mod1 to be received. Therefore, when signals f _mod2 and f _mod3 having amplitude modulation are present near a signal to be actually received, amplitude signals of all signals including signals other than the signal to be received are detected and represented as basebands. In addition, since the RF filter 21 has a power loss, the wakeup sensitivity characteristic may also be deteriorated. On the other hand, since the baseband filter 23 has a lower frequency band than the band of the RF filter 21, it is possible to design a filter of good performance. Therefore, the interference wave signal can be effectively removed. Of course, even if the carrier f (f _carrier ) is different by the baseband filter 23, but the frequency of the modulated signal (f _mod ) is the same, it is impossible to remove the interference wave. However, since much of the modulation signal f _mod is removed except when the frequency is the same, the influence of the jamming signal can be considerably reduced. However, since the baseband filter 23 mostly uses an active filter using an OP amplifier, an increase in power consumption for configuring the OP amplifier is caused. On the other hand, the baseband filter 23 may be implemented as a digital circuit behind the analog-to-digital converter. In this case, a clock generation block for driving the digital circuit is generally required, thereby increasing power consumption and system complexity. Cause.

The object of the present invention is to solve all the problems of the prior art described above.

An object of the present invention is to provide a wake-up receiver that can minimize power consumption and improve lifespan by not responding to a jamming wave having a large power.

Another object of the present invention is to minimize the operating current in the standby mode by configuring the wake-up receiver with digital logic circuits that operate without a reference clock.

On the other hand, another object of the present invention is to configure a wake-up receiver in a simplified configuration.

According to an embodiment of the present invention for achieving the above object, a low pass filter for removing a high frequency component for the converted digital signal of the wake-up signal, the low pass filter, by delaying the digital signal A delay cell for outputting one or more delay signals, a rising edge and a falling edge of the digital signal, two or more edge detectors for detecting the rising edge and the falling edge of the one or more delay signals, respectively, the digital signal detected by the edge detector One or more states that determine whether a state defined by the digital signal and the one or more delay signals matches a predefined state, in synchronization with the rising and falling edges of the one or more delayed signals, and the rising and falling edges of the one or more delayed signals. A wake-up receiver with jamming, comprising a machine, is provided .

The edge detector consists of first to fourth edge detectors, the state machine consists of first to third state machines, and the delay cell delays the digital signal by a first to third delay time, Outputting first to third delay signals, the first edge detector to detect the rising edge and the falling edge of the digital signal, and the second to fourth edge detectors respectively to the first to third delay signals; Detecting a rising edge and a falling edge, the first to third state machines respectively synchronizing to the rising edge and the falling edge of the digital signal, the rising edge and the falling edge of the first to third delay signals, and It may be determined whether the four states defined by the signal and the first to third delay signals coincide with the predefined states.

The first to third delay times may be td, td / 2, and td / 4, respectively, and f = 1 / (2 * td), and f may be a threshold frequency to be blocked.

The state machine may include first to fourth and fourth gates inputted differently from the digital signal, the inverted signal, the delayed signal, and the inverted signal, and an output of the first and fourth AND gates, respectively. A first and fourth D flip-flop, a fifth end gate receiving the output signals of the first to fourth D flip-flops, and generating a final output signal of the state machine, wherein the first to fourth D The flip-flop may use the rising edge of the digital signal, the rising edge of the delay signal, the falling edge of the digital signal, and the falling edge of the delay signal, respectively, as clock signals.

The inverted signal of the digital signal and the delay signal is input to the first AND gate, the digital signal and the delay signal are input to the second AND gate, and the inverted signal of the digital signal is input to the third AND gate. The delay signal may be input, and the inverted signal of the digital signal and the inverted signal of the delay signal may be input to the fourth AND gate.

The delay cell may include a plurality of inverters connected in series and a plurality of capacitors connected between both ends of the inverters.

The edge detector may include a NAND gate and an OR gate configured to receive an edge detection target signal and a delay signal of the edge detection target signal, respectively, and the NAND gate detects a rising edge of the edge detection target signal. The gate may detect a falling edge of the edge detection target signal.

The low pass filter may include a sixth AND gate receiving the output signals of the two or more state machines, an output signal of the digital signal and the sixth AND gate, and the output signal of the sixth AND gate is high. ) May further include a seventh AND gate for outputting the digital signal as it is.

And a high pass filter for removing low frequency components of the converted digital signal of the wake up signal, wherein the high pass filter outputs a high signal in synchronization with the rising edge of the digital signal. And a flip-flop, a counter for counting the number of cycles of the digital signal, and a counter reset unit for receiving the output signal of the D-flip-flop and periodically initializing the counter.

The D flip-flop is synchronously reset to the rising edge of the delay signal, and the counter reset unit is a switch that is turned on when the D-flip flop outputs a high signal, and the switch is turned on. It may include a capacitor that is charged in the (ON) state and starts discharging when the D-flip-flop is reset, and an inverter that inverts a signal across the capacitor and inputs it as an initialization signal of the counter.

The switch is implemented as a transistor, the gate of the transistor is connected to the output terminal of the D-flop flop, the source is connected to the power supply, the drain is connected to one end of the capacitor, one end of the resistor, the input terminal of the inverter The other end of the capacitor and the other end of the resistor may be connected to ground.

According to another embodiment of the present invention, a transceiver including the wake-up receiver is provided.

According to the present invention, since the wake-up receiver does not respond to a jamming wave having a large power, power consumption can be minimized and life can be improved.

In addition, according to the present invention, since the wake-up receiver can be configured with a digital logic circuit operating without a reference clock, the operating current in the standby mode is minimized.

On the other hand, according to the present invention, it is possible to configure the wake-up receiver with a simplified configuration.

1 is a block diagram schematically illustrating a configuration of a transceiver having a conventional wake up function.
2 is a block diagram showing a conventional wake-up receiver structure.
3 is a view for explaining the influence of the jamming signal in the conventional wake-up receiver.
4 is a diagram illustrating a configuration of a wake-up receiver according to an embodiment of the present invention.
5A and 5B are diagrams showing an example of a state diagram used in a low pass filter according to an embodiment of the present invention.
6 is a diagram illustrating an embodiment of a low pass filter according to an embodiment of the present invention.
7A and 7B illustrate an embodiment of a delay cell according to an embodiment of the present invention.
8 illustrates an embodiment of an edge detector according to an embodiment of the present invention.
9 is a view for explaining the output characteristics of the harmonic response of the low pass filter according to an embodiment of the present invention.
10 is a view showing the output characteristics of the low pass filter according to an embodiment of the present invention.
11 illustrates an embodiment of a delay cell according to an embodiment of the present invention.
12A to 12C illustrate frequency response characteristics of a low pass filter according to an embodiment of the present invention.
FIG. 13 illustrates an embodiment of a low pass filter in accordance with an embodiment of the present invention. FIG.
14A is a diagram illustrating an embodiment of a high pass filter according to an embodiment of the present invention.
FIG. 14B is a timing diagram showing signal states of respective parts in the high pass filter shown in FIG. 14A.
15 is a diagram illustrating a response characteristic of a conventional wake-up receiver and a wake-up receiver according to an embodiment of the present invention.

Hereinafter, the entire structure of a wake-up receiver according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a configuration of a wake-up receiver according to an embodiment of the present invention.

As described above, the wake-up receiver is provided in the wake-up transceiver, and the wake-up receiver detects the wake-up signal and performs a function of waking up the data transceiver that actually transmits and receives data.

Referring to FIG. 4, the wake-up receiver 400 of the present invention may include a passive power detector 410, an analog-to-digital converter 420, a low pass filter 430, and a high pass filter 440.

In the wake-up receiver according to an embodiment of the present invention, an RF filter or the like is not applied to the front end of the passive power detector 410, and this filter is not included, and only the antenna impedance matching unit IM is applied. Since the RF filter is generally difficult to implement in a narrow band, the amplitude signal of the interference wave is also generally detected. When the narrow band low pass filter 430 and the high pass filter 440 according to the embodiment of the present invention are applied, Since the RF filter is not used, the detection of the amplitude signal of the jamming wave together can be prevented, and the power loss is also reduced to improve the wakeup sensitivity characteristic. The low pass filter 430 and the high pass filter 440 according to an embodiment of the present invention will be described in detail later.

The passive power detector 410 removes a carrier from a signal received through the antenna and detects a modulated signal.

The analog-to-digital converter 420 converts the output signal of the passive power detector 410 into a digital signal.

4 shows a pattern P1 of a wake up signal received by an antenna and a pattern P2 of a signal passing through the analog-to-digital converter 420. As shown in FIG. P1 may be a signal having several cycles (for example, 15 to 17 cycles), and when the signal passes through the analog-digital converter 420, it may be restored to a digital signal having a square wave shape.

A characteristic part of the present invention is the low pass filter 430, the high pass filter 440.

5A and 5B are diagrams illustrating a state diagram of the low pass filter 430 according to an embodiment of the present invention.

5A and 5B, the low pass filter 430 uses the digital signal clk reconstructed by the wake-up receiver 400 and its delay signal clkdly. The delay signal clkdly can be obtained by passing the digital signal clk through a delay cell having a delay time td. Using these two signals, four signal states can be defined: s1 (10), s2 (11), s3 (01), and s4 (00). The states where the digital signal clk is high are s1 (10) and s2 (11), and the states where the delay signal clkdly is high are s2 (11) and s3 (01). S4 (00) is a state in which both the digital signal clk and the delay signal clkdly are low. The low pass filter 430 of the present invention can selectively pass only the defined wake-up signal by passing if all of the above four states exist in one cycle, or otherwise blocking. FIG. 5A shows a normal state in which the delay time between the digital signal clk and the delay signal clkdly is a normal delay time td, and FIG. 5B shows an example of a state in which the corresponding delay time deviates from the normal delay time td. . In the example shown in FIG. 5B, a state in which twice the frequency of the restored digital signal clk is greater than the inverse of the normal delay time td, that is, half of the period of the digital signal clk is the normal delay time td Shorter than) 5b shows four states s1 (10), s2 (01), s3 (00) and s4 (10), which are defined states s1 (10), s2 (11), s3 (01) and s4 ( 00). The low pass filter 430 according to an embodiment of the present invention, for example, as shown in Figure 5b to block the output to remove the signal. That is, by defining the delay time td of the delay cell, the high frequency signal is removed in such a manner as to block a signal having a frequency higher than half of its inverse.

FIG. 6 is a diagram illustrating one implementation of a logic circuit for state definition in low pass filter 430.

Referring to FIG. 6, a logic circuit for defining a state includes two inverters I1 and I2 which invert the restored digital signal clk and its delay signal clkdly, and an inverted signal of the delay signal clkdly and a digital signal. Inverted and delayed signals clkdly of the first AND gate A1 receiving the signal clk, the second AND gate A2 receiving the digital signal clk, and the delay signal clkdly, and the digital signal clk. ), The third AND gate A3 receiving the input, the fourth AND gate A4 receiving the inverting signal of the digital signal clk and the inverting signal of the delay signal clkdly, and the first to fourth AND gates A1, First to fourth D-flop flops D1, D2, D3, and D4 and first to fourth D-flip flops D1, D2, D3, and D4 respectively receiving the output signals of A2, A3, and A4. And a fifth end gate A5 that receives all of the output signals.

Since the states represented by the digital signal clk and the delay signal clkdly vary with time, it is necessary to store each state using the D-flip flops D1, D2, D3, and D4. As the clock signals of the first D-flip flop D1 and the third D-flip flop D3, a rising edge and a falling edge of the digital signal clk are used. In addition, the rising edge and the falling edge of the delay signal clkdly are used as the clock signals of the second D-flop flop D2 and the fourth D-flop flop D4.

Accordingly, the state s1 is stored in synchronization with the rising edge clk_re of the digital signal clk by the first D-flip flop D1, and the state s2 is delayed by the second D-flip flop D2. stored in synchronization with the rising edge (clkdly_re) of (clkdly), state s3 is stored in synchronization with the falling edge (clk_fe) of the digital signal (clk) by a third D-flip-flop (D3), and state s4 4 D-flip-flop (D4) is stored in synchronization with the falling edge (clkdly_fe) of the delay signal (clkdly).

When the outputs of the first to fourth D-flip flops D1, D2, D3, and D4 are all 1, the output signal ON of the fifth and gate A5 is high, and thus the digital signal clk. ) Is output as an output signal. On the other hand, if any of the outputs of the first to fourth D-flip flops D1, D2, D3, and D4 is not 1, that is, twice the frequency of the digital signal clk is the delay time td of the delay cell. Is greater than the reciprocal of (= 1/2 of the period of the digital signal clk is less than the delay time td), the output signal ON of the fifth and gate A5 is turned low to The signal clk is not output. This serves as a low pass filter, whereby a signal with a frequency higher than 1 / (2 td) is cut off.

The above-described logic circuit of FIG. 6 is just one embodiment, and of course, other logic circuits may be implemented according to a state to be defined.

7A and 7B illustrate an embodiment of a delay cell that outputs a delay signal clkdly by delaying the digital signal clk by a predetermined delay time td. FIG. 7A is a diagram illustrating a unit cell constituting a delay cell, that is, a cell of one stage, and FIG. 7B is a diagram illustrating an entire configuration of a delay cell composed of N cells.

7A and 7B also show the waveform of the digital signal after passing through the delay cell.

Referring to FIG. 7A, the delay cell may include an inverter I and a capacitor C. Referring to FIG.

If the required delay time td is large, the implementation of only one delay cell, as shown in Fig. 7A, will cause excessive delays, preventing the used inverter I from operating at the logic level, and delays being specified. It will not increase above the value.

Therefore, as shown in FIG. 7B, it is preferable to use a delay cell composed of N stages by connecting unit delay cells in multiple stages within the range in which the inverter I can operate at a logic level. That is, it is preferable to use an N-stage delay cell including a plurality of inverters I connected in series and a plurality of capacitors C connected between both ends of each inverter I.

On the other hand, in the logic circuit shown in FIG. 6, the clock signals of the D-flip flops D1, D2, D3, and D4 for storing the state may be generated by the edge detector.

8 illustrates an embodiment of an edge detector according to an embodiment of the present invention.

Referring to FIG. 8, the edge detector may include a delay cell DC that delays the digital signal clk, a NAND gate N that receives the digital signal clk, and a delay signal of the digital signal clk. (OR) gate (O) may be included.

The output signal of the NAND gate N becomes the clock signal as the rising edge clk_re of the digital signal clk, and the output signal of the or gate O is the clock signal of the falling edge clk_fe of the digital signal clk. do.

Referring back to FIG. 6, the four defined states appear repeatedly, and thus are not removed when the frequency of the restored digital signal clk becomes n * (1 / td).

9 is a view for explaining the output characteristics of the harmonic response of the low pass filter 430 according to an embodiment of the present invention.

Referring to FIG. 9, a blocking characteristic is shown for a signal having a frequency f2 higher than 1 / (2 * td). However, a signal with a frequency f4 of 1 / td exhibits four states that coincide with four defined states, so that a state transition becomes equal to a signal with a frequency f0 of 1 / (4 * td). Will occur. That is, these signals have a high frequency but are not blocked. Likewise, signals having a frequency f8 of 2 / td are also not blocked. FIG. 10 illustrates the output characteristics of the low pass filter 430 according to an embodiment of the present invention. For the same reason, the sampling effect as shown in FIG. That is, the pass filter characteristic of the predetermined band is generated starting from the frequency n times 1 / td.

In order to improve this characteristic, the present invention applies a delay time and a delay of td / n to the delay cell described with reference to FIG. 7.

11 is a diagram illustrating a configuration of a delay cell to which a delay is applied according to an embodiment of the present invention.

Referring to FIG. 11, delay cells clkdly, clkdly2, and clkdly4 having delays of 1, 1/2, and 1/4 times the delay time td are respectively included in a delay cell according to an embodiment of the present invention. Delay of td / n can be applied through.

12A to 12C show frequency response characteristics when the first order low pass filter 430 is implemented using digital signals and delay signals, respectively. First, FIG. 12A shows the frequency response of the low pass filter 430 using the digital signal clk and the delay signal clkdly having the delay time td. FIG. 12B shows the digital signal clk and the delay time td / 2. The frequency response characteristic of the low pass filter 430 using the delay signal clkdly2 having the following is shown. FIG. 12C shows the low pass filter 430 using the delay signal clkdly4 having the delay time td / 4 with the digital signal clk. ) Frequency response characteristics. FIG. 12D illustrates the frequency response characteristics of the third order low pass filter 430 in which all of the first order low pass filters 430 of FIGS. 12A to 12C are synthesized. That is, if the states of FIG. 6 are defined using delay signals clkdly, clkdly2, and clkdly4, respectively, the third-order low pass filter 430 as illustrated in FIG. 12D may be implemented. Theoretically, in the case of the third-order low pass filter 430, the pass band is repeatedly present every four times the frequency, but the quadrature frequency may be removed due to the frequency response of the delay cell itself.

FIG. 13 is a diagram illustrating an implementation of a third order low pass filter 430 to which a delay cell is applied according to an embodiment of the present invention.

Referring to FIG. 13, the third-order low pass filter 430 receives a reconstructed digital signal clk, and outputs an N-stage delay cell NDC and a digital signal clk that output delay signals clkdly, clkdly2, and dlkdly4. ) And the first to fourth edge detectors ED1, ED2, ED3, and ED4, the digital signals clk and the respective delay signals clkdly, clkdly2, and clkdly4, which detect edges of the delay signals clkdly, clkdly2, and clkdly4. First and third state machines SM1, SM2, and SM3 that define a state by using the first and gate A1 to receive output signals of the first to third state machines SM1, SM2, and SM3, The second AND gate A2 may receive the output signal of the first AND gate A1 and the digital signal clk to generate a final output signal.

The first edge detector ED1 detects the rising edge clk_re and the falling edge clk_fe of the digital signal clk, and the second edge detector ED2 is delayed by td by the delay cell NDC. The rising edge (clkdly_re) and the falling edge (clkdly_fe) of the signal (clkdly) are detected, and the third edge detector (ED3) is the rising edge of the second delay signal (clkdly2) delayed by td / 2 by the delay cell (NDC). The clkdly2_re and the falling edge clkdly2_fe are detected, and the fourth edge detector ED4 detects the rising edge clkdly4_re and the falling edge of the third delay signal clkdly4 delayed by td / 4 by the delay cell NDC. clkdly4_fe) is detected.

Meanwhile, the first state machine SM1 is detected by the rising edge clk_re, the falling edge clk_fe, and the second edge detector ED2 of the digital signal clk detected by the first edge detector ED1. In synchronization with the rising edge (clkdly_re) and the falling edge (clkdly_fe) of the first delay signal (clkdly), the state defined by the input digital signal (clk) and the first delay signal (clkdly) coincide with the predefined state Judge. In addition, the second state machine SM2 is detected by the rising edge clk_re, the falling edge clk_fe, and the third edge detector ED3 of the digital signal clk detected by the first edge detector ED1. The state defined by the input digital signal clk and the second delay signal clkdly2 coincides with the predefined state in synchronization with the rising edge clkdly2_re and the falling edge clkdly2_fe of the second delay signal clkdly2. Judge. The third state machine SM3 may include the rising edge clk_re, the falling edge clk_fe, and the fourth edge detector ED4 of the digital signal clk detected by the first edge detector ED1. By synchronizing with the rising edge (clkdly4_re) and the falling edge (clkdly4_fe) of the delay signal (clkdly4), it is determined whether the state defined by the input digital signal (clk) and the third delay signal (clkdly4) matches the predefined state. do.

The first to third state machines SM3 may be implemented with logic circuits as shown in FIG. 6. When the state defined based on the currently input digital signal clk and the respective delay signals clkdly, clkdly2, and clkdly4 matches the predefined state, the first to third state machines SM3 are respectively high. ) Outputs a signal. The first state machine SM1 synchronizes the rising edge clk_re and the falling edge clk_fe of the digital signal clk, and the rising edge clkdly_re and the falling edge clkdly_fe of the first delay signal clkdly. A high signal is output when the state defined by the signal clk and the first delay signal clkdly matches the predefined state. The second state machine SM2 synchronizes the rising edge clk_re and the falling edge clk_fe of the digital signal clk, and the rising edge clkdly2_re and the falling edge clkdly2_fe of the second delay signal clkdly2. A high signal is output when the state defined by the signal clk and the second delay signal clkdly2 matches the predefined state. The third state machine SM3 outputs a rising edge of the digital signal clk. A state defined by the digital signal clk and the third delay signal clkdly4 in synchronization with the clk_re and the falling edge clk_fe and the rising edge clkdly4_re and the falling edge clkdly4_fe of the third delay signal clkdly4. If the signal matches a predefined state, a high signal is output.

The pass band is repeatedly formed at every four times the frequency, and thus the formation of the pass band even at an undesired frequency band is prevented by the third order filter including the first to third state machines SM1, SM2, and SM3. Can be.

The first AND gate A1 receives the outputs of the first to third state machines SM1, SM2, and SM3 as inputs, and the outputs of the first to third state machines SM1, SM2, and SM3 are all high. ) Outputs a high signal. The second and gate A2 receives the digital signal clk and the output of the first and gate A1 as inputs, and the digital signal clk when the output of the first and gate A1 is high. To the output signal (clk_out).

Only when the digital signal clk having a frequency smaller than the frequency 1 / (2 * td) defined as the delay cell NDC is input by the low pass filter 430, the input of the digital signal clk_in ) May be output as the output signal clk_out.

Meanwhile, referring back to FIG. 4, the high pass filter 440 according to the exemplary embodiment of the present invention performs a function of removing the low frequency component from the signal from which the high frequency component is removed by the low pass filter 430.

14A is a diagram illustrating an implementation of a high pass filter 440 according to one embodiment of the present invention.

Since the jammer signal may also include low frequency components, a structure is needed to remove it.

Referring to FIG. 14A, a high pass filter 440 according to an embodiment of the present invention includes a D-flip flop 441, a counter reset unit 442, and a counter 443.

The counter 443 receives a signal passing through the low pass filter 430, that is, a signal from which high frequency components have been removed, and finally receives a cycle of a predetermined value (for example, 15 to 17 cycles). The wake-up signal WK_DT is output.

The counter reset unit 442 performs a function of periodically resetting the counter 443. The counter reset unit 442 may include a switch T, a capacitor C, a resistor R, and an inverter I, which may be implemented as a transistor.

The switch T may be implemented with, for example, a P-type transistor. A power terminal may be connected to a source of the switch T implemented as a P-type transistor, an output terminal of the D-flop flop 441 may be connected to a gate, and a capacitor C may be connected between a drain and ground. In addition, a resistor R may be further connected between the drain of the switch T and the ground. Meanwhile, the input terminal of the inverter I is connected to the drain of the switch T, and the output terminal is connected to the load LOAD of the counter 443.

The D flip-flop 441 outputs a high signal in synchronization with the rising edge clk_re of the restored digital signal clk, and when the D flip-flop 441 outputs a high signal. The switch T is turned on to charge the capacitor C. That is, the capacitor C of the counter reset unit 442 is charged in synchronization with the rising edge clk_re of the digital signal clk. On the other hand, the D-flip-flop 441 is reset in synchronization with the rising edge (clkdly_re) of the delayed signal of the digital signal (clk), at which time the switch (T) is off (OFF), charging the capacitor (C) Charge is discharged. The discharge rate is 1 / RC. The discharge signal is input to the load terminal of the counter 443 via the inverter I, thereby periodically initializing the load signal of the counter 443.

FIG. 14B is a timing diagram showing signal states of respective parts in the high pass filter 440 shown in FIG. 14A.

In FIG. 14B, WK_PCR represents charge and discharge states of the capacitor (C). Referring to FIG. 14B, the capacitor C is charged in synchronization with the rising edge clk_re of the restored digital signal clk, and the capacitor is synchronized with the rising edge clkdly_re of the delayed signal of the restored digital signal clk. (C) is discharged. As described above, the discharge rate is 1 / RC, and the time required for discharge may be represented by an R-C time constant (τ = RC). As shown in FIG. 14B, when the voltage across the capacitor C is equal to or greater than a predetermined value (for example, 1/2 of the power supply voltage applied to the source terminal of the switch T), the value is the inverter I. Is inverted to a load terminal of the counter 443 to initialize the counter 443. The counter 443 receives the digital signal clk as an input. If the period of the digital signal clk is longer than the R-C time constant τ = RC, the counter is initialized to limit the output signal. The R-C time constant may be appropriately selected based on the period associated with the number of cycles of the digital signal clk to be passed.

Accordingly, the high pass filter 440 may remove low frequency components from the signal passing through the low pass filter 430.

FIG. 15 illustrates response characteristics when a conventional wake-up receiver and a wake-up receiver according to an embodiment of the present invention are applied to Chinese Dedicated Short Range Communications (DSRC), respectively.

The system applied is a short range communication standard technology in China that uses 14kHz wake-up signal. Therefore, by designing a filter having a band pass characteristic of about 4 ~ 30kHz based on 14kHz to implement the wake-up error caused by the interference wave.

In Figure 15, the horizontal axis represents the amplitude modulation frequency of the jammer, the vertical axis represents the reception sensitivity of the wake-up receiver. In case of the prior art, the highest reception sensitivity is shown in the 14 kHz band, which is a wake-up modulation frequency, and the reception sensitivity gradually decreases (slowly) as the modulation frequency is increased. This is a common characteristic of passive power detectors. In general, the interference wave is often a large power received, according to the prior art, since the terminal reacts to the interference wave with a large power, there are many cases of malfunction. On the other hand, according to the present invention, since the modulation frequency is limited to about 4 to 30 kHz, the possibility of malfunction due to the interference wave is significantly reduced. Therefore, when the present invention is applied to the wake-up receiver, power consumption due to malfunction may be reduced, and the life of the battery operated terminal may be extended.

Although the above description has been made with reference to the embodiments, these are only examples and are not intended to limit the present invention, and those of ordinary skill in the art to which the present invention pertains should not be exemplified above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

400: wake up receiver
410: passive power detector
420: analog-to-digital converter
430 low pass filter
440: high pass filter

Claims (12)

A low pass filter for removing high frequency components on the converted digital signal of the wake up signal,
The low pass filter,
A delay cell delaying the digital signal to output one or more delayed signals;
Two or more edge detectors for detecting a rising edge and a falling edge of the digital signal and a rising edge and the falling edge of the one or more delayed signals, respectively; And
A state defined by the digital signal and the at least one delay signal is defined in synchronization with the rising edge and the falling edge of the digital signal detected by the edge detector and the rising edge and the falling edge of the at least one delay signal. One or more state machines to determine if they match the state
A wake-up receiver having a jamming function, including. The method of claim 1,
The edge detector consists of first to fourth edge detectors, the state machine consists of first to third state machines,
The delay cell delays the digital signal by a first to third delay time, and outputs first to third delay signals,
The first edge detector detects a rising edge and a falling edge of the digital signal, and the second to fourth edge detectors detect the rising edge and the falling edge of the first to third delay signals, respectively,
The first to third state machines are respectively synchronized with the rising edge and the falling edge of the digital signal, the rising edge and the falling edge of the first to third delay signals, and the digital signal and the first to third delay. A wake-up receiver with interference cancellation that determines whether four states defined by a signal match a predefined state. The method of claim 2,
The first to third delay times are td, td / 2, and td / 4, respectively.
a wake-up receiver with interference rejection, where f = 1 / (2 * td) and f is the threshold frequency to be blocked. The method of claim 1,
The state machine,
First to fourth AND gates configured to differently input two signals of the digital signal, the inverted signal, the delay signal, and the inverted signal;
First to fourth D flip-flops receiving the outputs of the first to fourth AND gates, respectively; And
A fifth end gate receiving the output signals of the first to fourth D-flip flops to generate a final output signal of the state machine,
The first to fourth D-flip flops each use a rising wave cancellation function using a rising edge of the digital signal, a rising edge of the delay signal, a falling edge of the digital signal, and a falling edge of the delay signal as clock signals. Having a wake up receiver. 5. The method of claim 4,
The inverted signal of the digital signal and the delay signal is input to the first AND gate,
The digital signal and the delay signal are input to the second AND gate,
The inverted signal and the delay signal of the digital signal are input to the third AND gate,
The fourth AND gate is input to the inverted signal of the digital signal and the inverted signal of the delay signal, the wake-up receiver having a jamming function. The method of claim 1,
The delay cell,
A plurality of inverters connected in series; And
And a plurality of capacitors coupled between each of said inverters. The method of claim 1,
The edge detector includes a NAND gate and an OR gate that receive edge detection target signals and delay signals of the edge detection target signals, respectively,
And the NAND gate detects a rising edge of the edge detection target signal, and the or gate detects a falling edge of the edge detection target signal. 8. The method according to any one of claims 1 to 7,
The low pass filter,
A sixth AND gate configured to receive output signals of the two or more state machines; And
And a seventh AND gate which receives the digital signal and the output signal of the sixth AND gate and outputs the digital signal as it is when the output signal of the sixth AND gate is high. Wake-up receiver with the function. The method of claim 1,
And a high pass filter for removing low frequency components of the converted digital signal of the wake up signal,
The high pass filter,
A D-flip-flop that outputs a high signal in synchronization with the rising edge of the digital signal;
A counter for counting the number of cycles of the digital signal; And
Counter reset unit for receiving the output signal of the D- flip-flop and periodically initializes the counter
A wake-up receiver having a jamming function, including. 10. The method of claim 9,
The D-flip-flop is synchronously reset to the rising edge of the delay signal,
The counter reset unit,
A switch that is turned on when the D-flip-flop outputs a high signal;
A capacitor charged when the switch is in an ON state and starting discharging when the D flip-flop is reset;
And an inverter for inverting a signal across the capacitor and inputting the signal as an initialization signal of the counter. The method of claim 10,
The switch is implemented with a transistor,
An output terminal of the D-flip-flop is connected to a gate of the transistor, a power source is connected to a source, one end of the capacitor, one end of a resistor, and an input end of the inverter are connected to a drain thereof.
And the other end of the capacitor and the other end of the resistor are connected to ground. 12. A transceiver comprising a wake-up receiver according to any one of claims 1-7 or 9-11.

Images