CN102904595A

CN102904595A - Wake-up receiver with interference wave clearing function and tranceiver comprising the same

Info

Publication number: CN102904595A
Application number: CN2011102355601A
Authority: CN
Inventors: 崔贞基; 李康赫; 高桭豪
Original assignee: PI CHIP CORP Ltd
Current assignee: Neo Lab Convergence Inc.
Priority date: 2011-07-29
Filing date: 2011-08-17
Publication date: 2013-01-30
Anticipated expiration: 2031-08-17
Also published as: KR20130013785A; KR101241742B1; CN102904595B

Abstract

The invention relates to a wake-up receiver with an interference wave clearing function and a tranceiver comprising the same. The wake-up receiver with the interference wave clearing function comprises a low-pass filter clearing high-frequency components of converted digital signals of the wake-up signals, wherein the low-pass filter comprises a delay element used for delaying digital signals and outputting more than one delay signals; more than two edge detectors used for respectively detecting a rising edge and a falling edge of the digital signals and a rising edge and a falling edge of the more than one delay signals; and more than one state machine used for synchronizing with the rising edge and the falling edge of the digital signals and the rising edge and the falling edge of the more than one delay signals detected by the edge detectors, and determining whether the states of the digital signals and the more than one delay signals are consistent with a pre-defined state.

Description

Have disturbing wave and remove waking receiver up and comprising that this wakes the transceiver of receiver up of function

Technical field

The present invention relates to have disturbing wave and remove waking receiver up and comprising that this wakes the transceiver of receiver up of function.

Background technology

For adopting such as the communication system by the transceiver of battery operation such as wireless sensor network, normal operation comprises the transceiver of the receiver that wakes (wake-up) mode up, to prolong the life-span of terminal.

Be disclosed in Korea S's publication communique 10-2010-0138076 number (2010.12.31) as background technology of the present invention.

Fig. 1 is for roughly illustrating the block diagram of the structure of the transceiver that possesses common arousal function.

With reference to Fig. 1, the transceiver 10 that possesses arousal function comprises and wakes receiver 11 and data collector 12 up.

Wake receiver 11 up and detect wake-up signal, the actual data of data collector 12 transmitting-receivings.When particular moment receives wake-up signal, wake receiver 11 up this induction is waken up data collector 12.Accordingly, data collector 12 can transceiving data.

For this wake-up mode, multiple method for minimum power consumption has been proposed.One of them mode is periodically moved wake-up circuit with the specific criteria Frequency Synchronization exactly.But, basically the power consumption that wakes receiver itself up is most important factor, and in order to reduce this power consumption that wakes receiver itself up, use power application to consume low Schottky diode or the passive type electric power detector of mos field effect transistor (MOSFET) all the time.But because passive type electric power detector has the characteristic of pass band, therefore when existence has amplitude-modulated disturbing wave signal, can produce misoperation.Because the running status of terminal is unnecessarily changed in the misoperation that this disturbing wave causes, even the power consumption of wake-up circuit itself diminishes, also can increase unnecessary power consumption.This can cause the shortening of battery life.

Fig. 2 is for using the block diagram that wakes receiver architecture up (reference: Kolinko, the P. of normally used passive type electric power detector; Larson, L.E.; , " Passive RF Receiver Design for Wireless Sensor Networks, " Microwave Symposium, 2007.IEEE/MTT-S International, vol., no., pp.567-570,3-8June 2007).

With reference to Fig. 2, wake receiver 20 up and comprise: radio frequency (RF) filter 21 is used for the impedance matching of antenna and removes disturbing wave; Baseband filter 23 from by amplitude-modulated RF signal removal carrier wave, and detects modulation signal, and the disturbing wave of removing high fdrequency component and do not remove at RF filter 21 from detected signal; Amplifier 24; Analog to digital converter (ADC) 25.

Thisly wake the signal that in fact receiver 20 exports the data sink that is used for waking up transceiving data up.

The curve that the output signal that Fig. 2 illustrates the signal that is input into before the RF filter 21 and passive type electric power detector 22 simultaneously shows at time domain and frequency domain, with reference to this figure, passive type circuit detector 22 is removed carrier wave f from amplitude-modulated RF signal _CarrierAnd detect modulation signal f _Mod

With reference to Fig. 2, observe by the characteristic of amplitude-modulated RF signal as can be known, in time domain, have the amplitude of carrier wave according to amplitude-modulated signal f _ModThe characteristic that changes is at frequency domain, with carrier wave f _CarrierFrequency relation be to be and to possess difference and be equivalent to amplitude-modulated signal f _ModThe characteristic of frequency content of frequency.This amplitude-modulated signal f _ModDuring by passive type electric power detector 22, carrier wave f _CarrierBe attenuated, only amplitude-modulated signal f _ModBe detected.In general, passive type electric power detector 22 almost with carrier independent detect amplitude-modulated signal f _Mod

In this structure, can effectively prevent from by the RF filter 21 that uses the arrowband having the passive type electric power detector 22 response disturbing wave signals of broadband character.But as shown in Figure 3, in general, RF filter 21 extremely difficulty possesses narrow-band characteristic, therefore may only select hardly the channel signal f that will receive _Carrier1, f _Mod1Therefore, existence has amplitude-modulated signal f near the actual signal that will receive _Mod2, f _Mod3The time, can detect the amplitude signal of all signals that comprise the signal outside the signal that will receive, and be shown in base band.And, for RF filter 21, owing to have power loss, wake sensitivity up and also may worsen.In contrast, therefore baseband filter 23 can design high performance filter owing to have the lower frequency band of relative RF filter 21.Therefore, can effectively remove disturbing wave.Obviously, carrier wave f _CarrierDifference, and modulation signal f _ModFrequency when identical, even also can't remove disturbing wave by baseband filter 23.But, except modulation signal f _ModThe identical situation of frequency outside, can remove most of interference signal, therefore can reduce the impact of most disturbing wave signal.But for baseband filter 23, most of active filter of using OP (computing) amplifier that uses causes the increase for the power consumption that consists of the OP amplifier.In addition, baseband filter 23 can be in the rear end of analog to digital converter with digital circuit, but needs to be used for driving the clock generating module of digital circuit this moment, therefore causes the complicated of the increase of power consumption and system.

Summary of the invention

The object of the invention is to solve all problems of above-mentioned prior art.

The object of the invention is to, a kind of receiver that wakes up is provided, this wakes receiver up can be to having the disturbing wave response of large electric power, can minimum power consumption, and life-saving.

Another object of the present invention is to, consist of with the Digital Logical Circuits that does not have standard time clock also can move and wake receiver up, thus the running current of minimize standby pattern.

In addition, another purpose of the present invention is, utilizes the structure of simplifying to consist of and wakes receiver up.

For achieving the above object, according to one embodiment of the invention, a kind of receiver that wakes up with function of removing disturbing wave is provided, comprise and remove the low pass filter of high fdrequency component for wake-up signal through the digital signal of conversion, this low pass filter comprises: delay element, to be used for postponing digital signal, export more than one inhibit signal; Plural edge detector is to be used for detecting the respectively rising edge of described digital signal and rising edge and the drop edge of drop edge and described more than one inhibit signal; And more than one state machine, synchronous to be used for rising edge and the drop edge of the rising edge of the described digital signal that detects by described edge detector and drop edge, described more than one inhibit signal, judge the state that defined by described digital signal and described more than one inhibit signal whether with predefined state consistency.

Described edge detector is made of first to fourth edge detector, described state machine becomes to third state mechanism by first, described delay element is with the first to the 3rd time of delayed digital signal, to export the first to the 3rd inhibit signal, described the first edge detector detects rising edge and the drop edge of described digital signal, described the second to the 4th edge detector detects respectively rising edge and the drop edge of described the first to the 3rd inhibit signal, described first to third state machine respectively with rising edge and the drop edge of described digital signal, rising edge and the drop edge of described the first to the 3rd inhibit signal are synchronous, can judge described digital signal and the defined four kinds of states of described the first to the 3rd inhibit signal whether with predefined state consistency.

Be respectively td, td/2, td/4 described the first to the 3rd time of delay, and f=1/ (2*td), f can be the critical frequencies that will block.

Described state machine comprises: first to fourth with the door, two signals in described digital signal and reverse signal, described inhibit signal and the reverse signal are transfused to differently; First to fourth D-trigger; Receive respectively described first to fourth with the door output; The 5th with door, receive the output signal of described first to fourth D-trigger and produce the final output signal of described state machine; Described first to fourth D-trigger can be used as clock signal with the drop edge of the drop edge of the rising edge of the rising edge of described digital signal, described inhibit signal, described digital signal, described inhibit signal respectively.

Can be, described first with door in be transfused to the reverse signal of described digital signal and described inhibit signal, described second with the door in be transfused to described digital signal and described inhibit signal, the described the 3rd with door in be transfused to reverse signal and the described inhibit signal of described digital signal, the described the 4th with door in be transfused to the reverse signal of described digital signal and the reverse signal of described inhibit signal.

Described delay element can comprise a plurality of inverters that are connected in series, and is connected in a plurality of electric capacity between each described inverter two ends.

Described edge detector comprises that the NAND gate of the inhibit signal that receives respectively rim detection echo signal and described rim detection echo signal reaches or door, described NAND gate can detect the rising edge of described rim detection echo signal, and described or door can detect the drop edge of described rim detection echo signal.

Described low pass filter also can comprise: the 6th with door, to be used for receiving the output signal of described plural state machine; The 7th with door, be used for receiving described digital signal and the described the 6th with the output signal of door, when the described the 6th is high level (high) with the output signal of door, directly export described digital signal.

Also comprise high pass filter, remove low frequency component with the digital signal through conversion to described wake-up signal, described high pass filter can comprise: the D-trigger, to be used for exporting synchronously high level (high) signal with the rising edge of described digital signal; Counter is to be used for calculating the period of described digital signal; Counter replacement section is to be used for receiving the output signal of described D-trigger, the periodically described counter of initialization.

The rising edge of described D-trigger and described inhibit signal is reset synchronously, and described counter replacement section can comprise: switch, to be used for when described D-trigger is exported high level signal, being switched on (ON); Capacitor with for being recharged, begins discharge when described D-trigger is reset when described switch is switched on; Inverter is inputted as the initializing signal of described counter to be used for making the signal counter-rotating at described capacitor two ends.

Described switch is realized with transistor, be connected with the lead-out terminal of described D-trigger on the described transistorized grid, be connected with power supply on the source electrode, be connected with an end of described capacitor, an end of resistor, the input of described inverter in the drain electrode, the other end of described capacitor and the other end of described resistor can be connected to ground connection.

According to another embodiment of the present invention, provide and comprise the described transceiver that wakes receiver up.

According to the present invention, owing to wake receiver up and also can not respond for the disturbing wave that possesses large electric power, therefore can minimum power consumption, and improve the life-span.

And, according to the present invention, even if owing to can consist of and wake receiver up not possess Digital Logical Circuits that standard time clock also can move, but the therefore running current of minimize standby pattern.

In addition, according to the present invention, only just can consist of with the structure of simplifying and wake receiver up.

Description of drawings

Fig. 1 is for roughly illustrating the calcspar of the structure of the transceiver that possesses common arousal function;

Fig. 2 illustrates the existing calcspar that wakes receiver architecture up;

Fig. 3 is for being used for illustrating the existing figure that wakes the impact of the disturbing wave on the receiver up;

Fig. 4 is the figure that the structure of waking according to an embodiment of the invention receiver up is shown;

Fig. 5 a and Fig. 5 b are the figure that an example of employed state diagram in the low pass filter according to an embodiment of the invention is shown;

Fig. 6 illustrates the according to an embodiment of the invention figure of a realization example of low pass filter;

Fig. 7 a and Fig. 7 b illustrate the according to an embodiment of the invention figure of a realization example of delay element;

Fig. 8 illustrates the according to an embodiment of the invention figure of a realization example of edge detector;

Fig. 9 illustrates that for being used for low pass filter is for the figure of the output characteristic of high frequency response according to an embodiment of the invention;

Figure 10 illustrates the according to an embodiment of the invention figure of the output characteristic of low pass filter;

Figure 11 illustrates the according to an embodiment of the invention figure of a realization example of delay element;

Figure 12 a to Figure 12 d illustrates the according to an embodiment of the invention frequency response characteristic of low pass filter;

Figure 13 illustrates the according to an embodiment of the invention figure of a realization example of low pass filter;

Figure 14 a illustrates the according to an embodiment of the invention figure of a realization example of high pass filter;

Figure 14 b is the sequential chart that the each several part signal condition in the high pass filter shown in Figure 14 a is shown;

Figure 15 illustrates the existing figure that wakes receiver up and wake according to an embodiment of the invention the response characteristic of receiver up.

The drawing reference numeral explanation:

400: wake receiver up

410: passive type electric power detector

420: analog to digital converter

430: low pass filter

440: high pass filter

Embodiment

Below, describe the overall structure of waking according to the preferred embodiment of the invention receiver up in detail with reference to accompanying drawing.

Fig. 4 is the figure that the structure of waking according to an embodiment of the invention receiver up is shown.

As previously mentioned, wake receiver up and be provided to and wake up in the formula transceiver, wake that receiver is carried out the induction wake-up signal up and the function of waking the data collector of actual transceiving data up.

With reference to Fig. 4, the receiver 400 that wakes up of the present invention can comprise passive type electric power detector 410, analog to digital converter 420, low pass filter 430, high pass filter 440.

Wake up according to an embodiment of the invention in the receiver, at the front end of passive type electric power detector 410 RF filter etc. is not set, the IM of Antenna Impedance Matching section only is set.Because the RF filter is difficult to be embodied as the arrowband usually; therefore usually can detect the amplitude signal of disturbing wave; if and adopt low pass filter 430 and the high pass filter 440 of the arrowband as embodiment of the present invention; then can prevent from detecting simultaneously the amplitude signal of disturbing wave; and the minimizing power loss, therefore can promote and wake sensory characteristic up.To describe in detail in the back for low pass filter 430 and high pass filter 440 according to the embodiment of the invention.

Passive type electric power detector 410 is carried out following function, namely from by removing carrier wave the signal of antenna reception and detecting modulation signal.

Analog to digital converter 420 is carried out the function that the output signal of passive type electric power detector 410 is converted to digital signal.

The pattern P 2 of the pattern P 1 of the wake-up signal by antenna reception and the signal by analog to digital converter 420 is shown among Fig. 4 simultaneously, as shown in Figure 4, wake-up signal pattern P 1 can be (for example to have several circulations, 15～17 circulations) signal, when sort signal passes through analog to digital converter 420, can be restored to the digital signal with square wave.

The characteristic part of tool of the present invention is low pass filter 430, high pass filter 440.

Fig. 5 a and Fig. 5 b are the figure that the according to an embodiment of the invention state diagram of low pass filter 430 (state diagram) is shown.

With reference to Fig. 5 a and Fig. 5 b, low pass filter 430 utilizes by the digital signal clk that wakes receiver 400 recoveries up and the inhibit signal clkdly of this digital signal clk.Inhibit signal clkdly is by making digital signal clk obtain by the delay element with td time of delay.Utilize these two signals can define four signal condition, i.e. s1 (10), s2 (11), s3 (01), s4 (00).Digital signal clk be in high level (high) state be s1 (10), s2 (11), inhibit signal clkdly be in high level state be s2 (11), s3 (01).S4 (00) all is in low level (low) state for digital signal clk and inhibit signal clkdly.When four kinds of above-mentioned in one-period states all existed, low pass filter 430 of the present invention passed through signal, otherwise disabling signal optionally makes defined wake-up signal pass through thus.Be the state of normal delay time td the time of delay that Fig. 5 a illustrates between digital signal clk and the inhibit signal clkdly, and Fig. 5 b illustrates the example that the correlation delay time exceeds the state of normal delay time td.Example shown in Fig. 5 b is, the twice of the frequency of the digital signal clk through restoring is greater than the state of the inverse of normal delay time td, that is, and and 1/2 state less than normal delay time td in the cycle of digital signal clk.Four kinds of state s1 (10) shown in Fig. 5 b, s2 (01), s3 (00), s4 (10), this is for breaking away from the situation as defined state s1 (10), s2 (11), s3 (01), s4 (00).For example in the situation shown in Fig. 5 b, block output according to the low pass filter 430 of one embodiment of the invention and remove coherent signal.That is, by td time of delay of definition delay element, adopt to have greater than time of delay td the mode of signal blocker of 1/2 times frequency of inverse remove high-frequency signal.

Fig. 6 is the figure that is illustrated in a realization example of the logical circuit that is used for definition status in the low pass filter 430.

With reference to Fig. 6, the logical circuit that is used for definition status can comprise: two inverter I1, I2, reverse with the digital signal clk that is used for respectively restoring and the inhibit signal clkdly of this digital signal clk; First with a door A1, to be used for reverse signal and the digital signal clk of receive delay signal clkdly; Second with a door A2, to be used for receiving digital signals clk and inhibit signal clkdly; The 3rd with a door A3, to be used for reverse signal and the inhibit signal clkdly of receiving digital signals clk; The 4th with a door A4, with the reverse signal that is used for receiving digital signals clk and the reverse signal of inhibit signal clkdly; First to fourth D-trigger D1, D2, D3, D4, be used for receiving respectively first to fourth with the output signal of door A1, an A2, A3, A4; The 5th with a door A5, be used for to receive the output signal of first to fourth D-trigger D1, D2, D3, D4.

Owing to the represented state of digital signal clk and inhibit signal clkdly along with the time changes, therefore need to utilize first to fourth D-trigger D1, D2, D3, D4 to store each state.The rising edge (rising edge) of use digital signal clk and drop edge (falling edge) are as the clock signal of a D-trigger D1 and the 3rd D-trigger D3.And the rising edge of use inhibit signal clkdly and drop edge are as the clock signal of the 2nd D-trigger D2 and the 4th D-trigger D4.

Thus, state s1 is stored by the rising edge clk_re of a D-trigger D1 and digital signal clk synchronously, state s2 is stored by the rising signals clkdly_re of the 2nd D-trigger D2 and inhibit signal clkdly synchronously, state s3 is stored by the drop edge clk_fe of the 3rd D-trigger D3 and digital signal clk synchronously, and state s4 is stored by the dropping signal clkdly_fe of the 4th D-trigger D4 and inhibit signal clkdly synchronously.

When the output of first to fourth D-trigger D1, D2, D3, D4 is 1, the 5th with the door A5 output signal ON become high level (high), digital signal clk exports as output signal thus.In contrast, even when only having one to be not 1 in the output of first to fourth D-trigger D1, D2, D3, D4, namely, the twice of the frequency of digital signal clk greater than delay element time of delay td inverse (cycle of=digital signal clk 1/2 less than td time of delay) time, therefore the 5th becomes low level (low) with the output signal ON of door A5, can output digit signals clk.Accordingly, play the effect of low pass filter, according to this filter signal that has greater than the frequency of 1/ (2td) capable of blocking.

The logical circuit of Fig. 6 described above only is a realization example, also can realize by other logical circuit according to the state that will define in advance.

Fig. 7 a and Fig. 7 b illustrate to make digital signal clk postpone scheduled delay td and a figure who realizes example of the delay element of output delay signal clkdly.Fig. 7 a illustrates the unit components that consists of delay element, i.e. the figure of a segment element, and Fig. 7 b is the integrally-built figure that the delay element that is made of the N segment element is shown.

Fig. 7 a and Fig. 7 b illustrate the waveform by the digital signal after the delay element simultaneously.

With reference to Fig. 7 a, delay element can be made of inverter I and capacitor C.

When needed time of delay, td was long, shown in Fig. 7 a, if only use a delay element to realize, then postpone excessively, not only employed inverter I can not move with logic level, postpones also can not increase to more than the particular value.

Therefore, preferably, shown in Fig. 7 b, within the scope that inverter I can move with logic level, connect the cell delay element of multistage, thereby use the delay element that is consisted of by the N section.That is, preferably, use to comprise a plurality of inverter I that are connected in series, the N section delay element that is connected in a plurality of capacitor C between each inverter I two ends.

In addition, in logical circuit shown in Figure 6, be used for D-trigger D1, D2, the D3 of storing state, the clock signal of D4 can be produced by edge detector.

Fig. 8 illustrates an according to an embodiment of the invention realization example of edge detector.

With reference to Fig. 8, edge detector can comprise: delay element DC, to be used for that digital signal clk is postponed; With non-(NAND) door N and or (OR) door O, to be used for the inhibit signal of receiving digital signals and digital signal clk.

The output signal of NAND gate N becomes the clock signal of the rising edge clk_re of digital signal clk, or the output signal of door O becomes the clock signal of the drop edge clk_fe of digital signal clk.

Referring again to Fig. 6, because defined four kinds of states occur repeatedly, if therefore the frequency of the digital signal clk through restoring reaches n* (1/td), then can not be eliminated.

Fig. 9 illustrates that for being used for low pass filter 430 is for the figure of the output characteristic of high frequency response according to an embodiment of the invention.

With reference to Fig. 9, present blocking characteristics for the signal with frequency f 2 higher than 1/ (2*td).But, because therefore the signal of frequency f 4 with 1/td can produce the identical state transition that becomes with the signal of the frequency f 0 with 1/ (4*td) owing to show four kinds of states with defined four kinds of state consistencies.That is, although sort signal has high frequency, can not be blocked.Identical therewith, the signal with frequency f 8 of 2/td can not be blocked yet.Figure 10 represents the according to an embodiment of the invention output characteristic of low pass filter 430, for the foregoing reasons, shows sampling effect as shown in figure 10.That is, the n overtones band from 1/td begins to produce predetermined pass band filter characteristic.

In order to improve this specific character, the present invention has used time of delay in the delay element of reference Fig. 7 explanation, the delay of td/n.

Figure 11 is the figure of the structure of the delay element when representing according to one embodiment of the invention application delay.

With reference to Figure 11, according to an embodiment of the invention in the delay element, inhibit signal clkdly, the clkdly2 of 1 times, 1/2 times, 1/4 times delay by having respectively td time of delay, the delay that clkdly4 uses td/n.

Frequency response characteristic when Figure 12 a and Figure 12 c represent respectively to utilize digital signal and inhibit signal to realize a low pass filter 430.At first Figure 12 a represents to utilize the frequency response characteristic of digital signal clk and the low pass filter 430 of the inhibit signal clkdly with td time of delay, Figure 12 b represents to utilize the frequency response characteristic of digital signal clk and the low pass filter 430 of the inhibit signal clkdly2 with td/2 time of delay, and Figure 12 c represents to utilize the frequency response characteristic of digital signal clk and the low pass filter 430 of the inhibit signal clkdly4 with td/4 time of delay.Figure 12 d represents the frequency response characteristic of No. 3 low pass filters 430 of the low pass filter 430 of composite diagram 12a to Figure 12 c.That is, when utilizing inhibit signal clkdly, clkdly2, clkdly4 respectively to the definition of the state of Fig. 6, can realize No. 3 low pass filters 430 shown in Figure 12 d.In theory, even also there is in per 4 doubling times passband repeatedly in No. 3 low pass filters 430, but according to the frequency response characteristic of delay element itself, also can remove 4 overtones bands.

Figure 13 illustrates the according to an embodiment of the invention figure of the realization example of No. 3 low pass filters 430 of application delay element.

With reference to Figure 13, No. 3 times low pass filter 430 can comprise: N section delay element NDC, to be used for receiving the digital signal through restoring, output delay signal clkdly, clkdly2, clkdly4; First to fourth edge detector ED1, ED2, ED3, ED4 are with the edge for detection of digital signal clk and inhibit signal clkdly, clkdly2, clkdly4; First to third state machine SM1, SM2, SM3, to be used for utilizing digital signal clk and each inhibit signal clkdly, clkdly2, clkdly4 definition status; First with a door A1, be used for to receive the first output signal to third state machine SM1, SM2, SM3; Second with a door A2, be used for to receive first with output signal and the digital signal clk of door A1, produce final output signal.

The first edge detector ED1 detects rising edge clk_re and the drop edge clk_fe of digital signal clk, the second edge detector ED2 detects rising edge clkdly_re and the drop edge clkdly_fe that postpones the first inhibit signal clkdly of td by delay element NDC, the 3rd edge detector ED3 detects rising edge clkdly2_re and the drop edge clkdly2_fe that postpones the second inhibit signal clkdly2 of td/2 by delay element NDC, and the 4th edge detector ED4 detects rising edge clkdly4_re and the drop edge clkdly4_fe that postpones the 3rd inhibit signal clkdly4 of td/4 by delay element NDC.

In addition, rising edge clk_re and the drop edge clk_fe, synchronous by rising edge clkdly_re and the drop edge clkdly_fe of detected the first inhibit signal clkdly of the second edge detector ED2 of the first state machine SM1 and the digital signal clk that detects by the first edge detector ED1, judge the digital signal clk of input and the defined state of the first inhibit signal clkdly whether with predefined state consistency.And, rising edge clk_re and the drop edge clk_fe, synchronous by rising edge clkdly2_re and the drop edge clkdly2_fe of detected the second inhibit signal clkdly2 of the 3rd edge detector ED3 of the second state machine SM2 and the digital signal clk that detects by the first edge detector ED1, judge the digital signal clk of input and the defined state of the second inhibit signal clkdly2 whether with predefined state consistency.Rising edge clk_re and the drop edge clk_fe, synchronous by rising edge clkdly4_re and the drop edge clkdly4_fe of detected the 3rd inhibit signal clkdly4 of the 4th edge detector ED4 of third state machine SM3 and the digital signal clk that detects by the first edge detector ED1, judge the digital signal clk of input and the defined state of the 3rd inhibit signal clkdly4 whether with predefined state consistency.

First to third state machine SM1, SM2, SM3 can realize by logical circuit shown in Figure 6.If based on the digital signal clk of current input and each inhibit signal clkdly, clkdly2, the defined state of clkdly4 and predefined state consistency, first exports respectively high level (high) signal to third state machine SM1, SM2, SM3.Rising edge clkdly_re and the drop edge clkdly_fe of the rising edge clk_re of the first state machine SM1 and digital signal clk and drop edge clk_fe, the first inhibit signal clkdly are synchronous, when digital signal clk and the defined state of the first inhibit signal clkdly and predefined state consistency, output high level (high) signal.Rising edge clkdly2_re and the drop edge clkdly2_fe of the rising edge clk_re of the second state machine SM2 and digital signal clk and drop edge clk_fe, the second inhibit signal clkdly2 are synchronous, when digital signal clk and the defined state of the second inhibit signal clkdly2 and predefined state consistency, output high level (high) signal.Rising edge clkdly4_re and the drop edge clkdly4_fe of the rising edge clk_re of third state machine SM3 and digital signal clk and drop edge clk_fe, the 3rd inhibit signal clkdly4 are synchronous, when digital signal clk and the defined state of the 3rd inhibit signal clkdly4 and predefined state consistency, output high level (high) signal.

Each 4 overtones band forms passband repeatedly, thus unexpected frequency band also form the phenomenon of passband can be so by comprising that first avoids to No. 3 filters of third state machine SM1, SM2, SM3.

First receives the first output to third state machine SM1, SM2, SM3 with door A1, exports high level signal when the first output to third state machine SM1, SM2, SM3 all be high level (high).Second with door A2 receiving digital signals clk and first with the output of door A1, when first is output as high level with A1, digital signal clk is exported as output signal clk_out.

According to this low pass filter 430, when the frequency that only possesses was input into delay element NDC less than the digital signal clk of defined frequency (1/ (2*td)), the input clk_in of correlated digital signals just can export as output signal clk_out.

In addition, referring again to Fig. 4, high pass filter 440 is carried out for the function of removing the signal removal low frequency component of high fdrequency component by low pass filter 430 according to an embodiment of the invention.

Figure 14 a illustrates the according to an embodiment of the invention figure of a realization example of high pass filter 440.

Because the disturbing wave signal also may comprise low frequency component, therefore need to remove the structure of this low frequency component.

With reference to Figure 14 a, high pass filter 440 comprises D-trigger 441, counter replacement section 442, counter 443 according to an embodiment of the invention.

Counter 443 receives the signal by low pass filter 430, has namely removed the signal of high fdrequency component, when the circulation of setting preset value (for example, 15～17 circulations), exports final wake-up signal WK_DT.

The function of counter replacement section 442 execution cycle property ground counter reset 443.Counter replacement section 442 can comprise can be by switch T, capacitor C, resistor R, the inverter I of the realizations such as transistor.

Switch T can be realized by for example P transistor npn npn.The source electrode of the switch T that is realized by the P transistor npn npn can connect power supply terminal, and grid can connect the lead-out terminal of D-trigger 441, can connect capacitor C between drain electrode and the ground connection.And, contact resistance device R again between the drain electrode of switch T and the ground connection.In addition, the input of inverter I is connected with the drain electrode of switch T, and be written into (LOAD) of output and counter 443 holds.

The rising edge clk_re of D-trigger 441 and the digital signal clk through restoring exports high level (high) signal synchronously, and when D-trigger 441 output high level signal, switch T is switched on (ON) and capacitor C is charged.That is, the rising edge clk_re of the capacitor C of counter replacement section 442 and digital signal clk is recharged synchronously.In addition, D-trigger 441 is reset synchronously with the rising edge clkdly_re of the inhibit signal of digital signal clk, and at this moment, switch T is disconnected (OFF), and the electric charge that charges to capacitor C is released.The velocity of discharge is 1/RC.Discharge signal is input to being written into of counter 443 (LOAD) end via inverter I, thus periodically counter reset 443 be written into (LOAD) signal.

Figure 14 b is the sequential chart of signal condition of the various piece of the high pass filter 440 shown in Figure 14 a.

WK_PCR among Figure 14 b represents charging and the discharge condition of capacitor C.With reference to Figure 14 b, capacitor C and the rising edge clk_re of digital signal clk through restoring charge synchronously, and the rising edge clkdly_re of capacitor C and the inhibit signal of digital signal clk through restoring discharges synchronously.As previously mentioned, the velocity of discharge is 1/RC, and the required time of discharging can be by R-C time constant (τ=RC) expression.Shown in Figure 14 b, when the voltage at capacitor C two ends in predetermined value (for example, put on switch T source terminal supply voltage 1/2) when above, its value be inverted device I counter-rotating and be applied to counter 443 be written into (LOAD) end, with counter reset 443.Counter 443 receiving digital signals clk, (τ=RC), then counter is initialised, and output signal will be restricted thus if the cycle of digital signal clk is greater than the R-C time constant.The R-C time constant can suitably be selected based on the cycle relevant with the period of the digital signal clk that will pass through.

Thus, high pass filter 440 is for the signal removal low frequency component that passes through low pass filter 430.

Figure 15 illustrates the existing response characteristic of waking receiver up and waking according to an embodiment of the invention receiver up when being applied to respectively Dedicated Short Range Communications, (DSRC:Dedicated Short Range Communications).

The system that uses is the Dedicated Short Range Communications, standard technique of the China of the wake-up signal of use 14kHz.Thus, provide the filter of the bandpass characteristics of the 4～30kHz that has an appointment take 14kHz as reference design, realized accordingly removing the phenomenon of makeing mistakes of waking up that disturbing wave causes.

Transverse axis among Figure 15 represents the Modulation and Amplitude Modulation frequency of disturbing wave, and the longitudinal axis represents to wake up the receiving sensitivity of receiver.In the prior art, reveal the highest receiving sensitivity as the 14kHz frequency meter that wakes modulating frequency up, and along with the rising of modulating frequency, presenting slowly (gradually) characteristic of reducing of receiving sensitivity.The general characteristic that this has for passive type electric power detector.In general, the situation that the electric power of the disturbing wave that receives is large is more, and according to this prior art, because terminal response is in the large disturbing wave of electric power, the situation that misoperation therefore occurs is more.In contrast, according to the present invention, because modulating frequency is limited in about 4～30kHz, so the possibility of the misoperation that causes of disturbing wave reduces significantly.Thus, when applying the present invention to wake receiver up, the power consumption that misoperation causes will reduce, and the life-span of the terminal by battery operation also can prolong.

Although above explanation is carried out centered by embodiment, but this only is exemplary, be not limitation of the invention, the technical staff with general knowledge in field does not have illustrative various modification and application under the present invention more than can proposing within the scope of the intrinsic propesties that does not break away from present embodiment.For example, can change each element that specifically appears at embodiment and implement.And the discrepancy relevant with application with this change should be interpreted as being included within the scope of the present invention of claims defined.

Claims

1. receiver that wakes up with function of removing disturbing wave, comprise for wake-up signal remove the low pass filter of high fdrequency component through the digital signal of conversion,

Described low pass filter comprises:

Delay element to be used for postponing described digital signal, is exported more than one inhibit signal;

Plural edge detector is to be used for detecting the respectively rising edge of described digital signal and rising edge and the drop edge of drop edge and described more than one inhibit signal; And

More than one state machine, synchronous to be used for rising edge and the drop edge of the rising edge of the described digital signal that detects by described edge detector and drop edge, described more than one inhibit signal, judge the state that defined by described digital signal and described more than one inhibit signal whether with predefined state consistency.

2. the receiver that wakes up with function of removing disturbing wave according to claim 1 is characterized in that described edge detector is made of first to fourth edge detector, and described state machine becomes to third state mechanism by first,

Described delay element is described the first to the 3rd time of delayed digital signal, exporting the first to the 3rd inhibit signal,

Described the first edge detector detects rising edge and the drop edge of described digital signal, and described the second to the 4th edge detector detects respectively rising edge and the drop edge of described the first to the 3rd inhibit signal,

Described first is synchronous with rising edge and the drop edge of the rising edge of described digital signal and drop edge, described the first to the 3rd inhibit signal respectively to third state machine, judge described digital signal and the defined four kinds of states of described the first to the 3rd inhibit signal whether with predefined state consistency.

3. the receiver that wakes up with function of removing disturbing wave according to claim 2 is characterized in that be respectively td, td/2, td/4 described the first to the 3rd time of delay, and f=1/ (2*td), f are the critical frequencies that will block.

4. the receiver that wakes up with function of removing disturbing wave according to claim 1 is characterized in that described state machine comprises:

First to fourth with the door, two signals in described digital signal and reverse signal, described inhibit signal and the reverse signal are transfused to differently;

First to fourth D-trigger, be used for receiving respectively described first to fourth with the output of door;

The 5th with door, produce the final output signal of described state machine to be used for receiving the output signal of described first to fourth D-trigger;

Described first to fourth D-trigger is used as clock signal with the drop edge of the drop edge of the rising edge of the rising edge of described digital signal, described inhibit signal, described digital signal, described inhibit signal respectively.

5. the receiver that wakes up with function of removing disturbing wave according to claim 4 is characterized in that,

Described first with door in be transfused to the reverse signal of described digital signal and described inhibit signal,

Described second with the door in be transfused to described digital signal and described inhibit signal,

The described the 3rd with door in be transfused to reverse signal and the described inhibit signal of described digital signal,

The described the 4th with the door in be transfused to the reverse signal of described digital signal and the reverse signal of described inhibit signal.

6. the receiver that wakes up with function of removing disturbing wave according to claim 1 is characterized in that described delay element comprises a plurality of inverters that are connected in series; And

Be connected in a plurality of electric capacity between each described inverter two ends.

7. the receiver that wakes up with function of removing disturbing wave according to claim 1 is characterized in that, described edge detector comprise the inhibit signal that receives respectively rim detection echo signal and described rim detection echo signal NAND gate and or door,

Described NAND gate detects the rising edge of described rim detection echo signal, and described or door detects the drop edge of described rim detection echo signal.

8. the described receiver that wakes up with function of removing disturbing wave of each in 7 according to claim 1 is characterized in that, comprising: the 5th with door, to be used for receiving the described first output signal to third state machine; And

The 6th with door, be used for receiving described digital signal and the described the 5th with the output signal of door, when the described the 5th is high level with the output signal of door, directly export described digital signal.

9. the receiver that wakes up with function of removing disturbing wave according to claim 1 is characterized in that, also comprises high pass filter, removes low frequency component with the digital signal through conversion to described wake-up signal,

Described high pass filter comprises:

The D-trigger is to be used for exporting synchronously high level signal with the rising edge of described digital signal;

Counter is to be used for calculating the period of described digital signal;

Counter replacement section is to be used for receiving the output signal of described D-trigger, the periodically described counter of initialization.

10. the receiver that wakes up with function of removing disturbing wave according to claim 9 is characterized in that, the rising edge of described D-trigger and described inhibit signal is synchronous and be reset,

Described counter replacement section comprises:

Switch is switched on when described D-trigger is exported high level signal being used for;

Capacitor with for being recharged, begins discharge when described D-trigger is reset when described switch is switched on;

Inverter is inputted as the initializing signal of described counter to be used for making the signal counter-rotating at described capacitor two ends.

11. the receiver that wakes up with function of removing disturbing wave according to claim 10 is characterized in that, described switch realizes with transistor,

Be connected with the lead-out terminal of described D-trigger on the described transistorized grid, be connected with power supply on the source electrode, be connected with an end of described capacitor, an end of resistor, the input of described inverter in the drain electrode,

The other end of described capacitor and the other end of described resistor are connected to ground connection.

Comprise the described transceiver that wakes receiver up 12. each in each in 7 or the claim 9 to 11 is described according to claim 1.