KR20130013637A - Nonvolatile memory device - Google Patents

Abstract

PURPOSE: A nonvolatile memory device is provided to minimize the size of a chip by integrating two decoders into one sharing decoder. CONSTITUTION: A memory core(190) includes a plurality of nonvolatile memory cells. A first read circuit(210_1) reads a first code word from the memory core in an RWW(Read While Write) operation. A second read circuit(210_2) reads a second code word from the memory core in an RMW(Read Modification Write) operation. A sharing decoder(220) is shared in the first read circuit and the second read circuit and selectively decodes the first code word or the second code word.

Description

Nonvolatile Memory Device

The present invention relates to a nonvolatile memory device.

A nonvolatile memory device using a resistance material includes a phase change random access memory (PRAM), a phase change memory (PCM), a resistive memory (RRAM), and a magnetic memory device (MRAM). ) Etc. Dynamic RAM (DRAM) or flash memory devices store data using charge, while non-volatile memory devices using resistors are used to store phase change material states such as chalcogenide alloys (PRAM), resistance change of variable resistance (RRAM), and resistance change (MRAM) of MTJ (Magnetic Tunnel Junction) thin film according to magnetization state of ferromagnetic material.

Here, when the phase change memory device is described as an example, the phase change material is changed to a crystalline state or an amorphous state while being heated and cooled, and the phase change material in the crystalline state has a low resistance and the phase change material in the amorphous state has a high resistance. . Therefore, the determination state may be defined as set data and the amorphous state may be defined as reset data.

On the other hand, as the memory capacity of a nonvolatile memory device increases, it is necessary to use an error correction circuit for correcting an error of a defective memory cell. The error correction circuit includes, for example, a method using a redundant memory cell, an Error Correction Code (ECC) method, and the like.

Here, the ECC method uses an ECC encoder and an ECC decoder, and the sizes of the ECC encoder and the ECC decoder are quite large. Therefore, it is difficult to reduce the chip size of the nonvolatile memory device using the ECC method.

An object of the present invention is to provide a nonvolatile memory device capable of minimizing size.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of the nonvolatile memory device of the present invention for solving the above problems is a memory core including a plurality of nonvolatile memory cells, the first code word from the memory core during a read while write (RWW) operation; A first read circuit, a second read circuit for reading a second codeword from the memory core during a read modulation write (RMW) operation, shared by the first read circuit and the second read circuit, and optionally, the first read circuit. And a shared decoder for decoding a codeword or decoding the second codeword.

Another aspect of the nonvolatile memory device of the present invention for solving the above problems is a memory core including a plurality of nonvolatile memory cells, the first code word read from the memory core during a read while write (RWW) operation; A first read circuit, a second read circuit for reading a second codeword from the memory core during a read modulation write (RMW) operation, and a first decoder coupled to the first read circuit to decode the first codeword And a second decoder coupled to the second read circuit to decode the second codeword, wherein the first decoder and the second decoder do not perform a decoding operation at the same time.

Another aspect of the nonvolatile memory device of the present invention for solving the above problems is to receive a first pulse generated based on the RWW read command, and to generate a protection signal that is enabled in at least a portion of the read period of the RWW operation. And a protection signal generator and a selection signal generator for receiving a second pulse generated based on the RMW read command and generating a selection signal based on whether the protection signal is enabled.

Other specific details of the invention are included in the detailed description and drawings.

1 is a block diagram illustrating a nonvolatile memory device in accordance with an embodiment of the present invention.
FIG. 2 is a diagram for describing an exemplary nonvolatile memory cell in the memory core shown in FIG. 1.
FIG. 3 is a circuit diagram for describing the read circuit shown in FIG. 1.
FIG. 4 is a block diagram illustrating the shared decoder illustrated in FIG. 1.
FIG. 5 is a block diagram illustrating the signal generator described with reference to FIG. 1.
FIG. 6 is a block diagram for describing the signal generator described with reference to FIG. 5 in more detail.
FIG. 7 is a timing diagram for describing an operation of the signal generator of FIG. 6.
8 is a block diagram illustrating a nonvolatile memory device in accordance with another embodiment of the present invention.
9 is a block diagram illustrating a memory system in accordance with some embodiments of the present invention.
FIG. 10 is a block diagram illustrating an application example of the memory system of FIG. 9.
FIG. 11 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 10.

Advantages and features of the present invention, and methods of achieving the same will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

When an element is referred to as being "connected to" or "coupled to" with another element, it may be directly connected to or coupled with another element or through another element in between. This includes all cases. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, embodiments of the present invention will be described using a phase change random access memory (PRAM). However, it will be apparent to those skilled in the art that the present invention can be applied to both a nonvolatile memory device using a resistor, such as a resistive memory device (RRAM) and a ferroelectric RAM (FRAM).

1 is a block diagram illustrating a nonvolatile memory device in accordance with an embodiment of the present invention. FIG. 2 is a diagram for describing an exemplary nonvolatile memory cell in the memory core shown in FIG. 1.

Referring to FIG. 1, a nonvolatile memory device 1 according to an embodiment of the present invention may include a memory core 190, a first read circuit 210_1, a second read circuit 210_2, a shared decoder 220, A first selector 301, a second selector 302, and the like. Through such a configuration, the nonvolatile memory device 1 according to an embodiment of the present invention can perform an error correction operation using ECC.

The memory core 190 may include a plurality of nonvolatile memory cells (see MC of FIG. 2). The nonvolatile memory cell MC may write or read data using a resistor. The nonvolatile memory cell MC includes a variable resistance element RC having a phase change material whose resistance varies according to data stored therein, and an access element AC for controlling a current flowing through the variable resistance element RC. can do. The access element AC may be a diode, a transistor, or the like coupled in series with the variable resistance element RC. In the figure, a diode is shown as a variable resistance element RC. In addition, the phase change material is GaSb, InSb, InSe. Sb2Te3, GeTe, GeSbTe, GaSeTe, InSbTe, SnSb2Te4, InSbGe, which combines three elements, AgInSbTe, which combines four elements, (GeSn) SbTe, GeSb (SeTe), Te81Ge15Sb2S2, etc. can be used. Of these, GeSbTe composed of germanium (Ge), antimony (Sb) and tellurium (Te) can be mainly used.

Although not shown in FIG. 1, an encoder (not shown) receives message data and generates parity bits capable of bit error correction. The write circuit (not shown) writes the message data and the parity bits to the memory core 190. Here, the "message data + parity bits" may be called "codeword".

The first read circuit 210_1 reads the first codeword RSACW from the memory core 190 during a read while write (RWW) operation. The first read circuit 210_1 is used for a normal read operation.

Here, the RWW operation means performing a read operation while performing a write operation. For example, the write operation may be performed in some areas, and the read operation may be simultaneously performed in other areas. Hereinafter, the read command input during the RWW operation is called "RWW read command", and the read operation during the RWW operation is called "RWW read". The RWW read command is the same as a normal read command except that it is a read command input during a write operation.

The second read circuit 210_2 reads the second codeword WSACW from the memory core 190 during a read modulation write (RMW) operation.

Here, the RMW operation means reading data stored in the memory core 190, comparing the read data with the data to be written, and writing only different bits. That is, in the RMW operation, the read operation must be preceded before the write operation. Hereinafter, the read command input during the RMW operation is referred to as an "RMW read command", and the read operation during the RMW operation is referred to as "RMW read".

The shared decoder 220 is shared by the first read circuit 210_1 and the second read circuit 210_2. The shared decoder 220 optionally decodes the first codeword RSACW provided from the first read circuit 210_1 or decodes the second codeword WSACW provided from the second read circuit 210_2. The shared decoder 220 may thus decode the first codeword RSACW and the second codeword WSACW to calculate an error location of the message data. Thereafter, the shared decoder may correct the message data to output the corrected message data CORRECTED_RSADATA or CORRECTED_WSADATA.

In addition, the first selector 301 and the second selector 302 operate in response to the selection signal WSADECEN. When the select signal WSADECEN is at a first level (eg, logic 0), the first and second selectors 301 and 302 couple the first read circuit 210_1 and the shared decoder 220. In addition, when the select signal WSADECEN is at the second level (eg, logic 1), the first and second selectors 301 and 302 couple the second read circuit 210_2 and the shared decoder 220. Let's do it. Here, the selection signal WSADECEN is provided from the signal generator 310. The configuration and operation of the signal generator 310 will be described later in detail.

Alternatively, although not clearly shown in the drawing, the first read circuit 210_1 may perform the sensing operation or the second read circuit 210_2 may perform the sensing operation according to the selection signal WSADECEN. That is, the sensing operation of the first read circuit 210_1 and the sensing operation of the second read circuit 210_2 may not be performed at the same time. This operation will be described later in detail with reference to FIG. 7.

The nonvolatile memory device 1 according to an embodiment of the present invention employs a shared decoder 220. That is, the decoder used in the normal read operation (or RWW read operation) and the decoder used in the RMW read operation are not separately provided. When the decoder used for the normal read operation and the decoder used for the RMW read operation operate simultaneously, mutual noise may occur. However, since the nonvolatile memory device 1 according to the exemplary embodiment of the present invention employs the shared decoder 220, it does not decode the first codeword and the second codeword at the same time. Therefore, such noise does not occur. In addition, since two decoders are integrated into one shared decoder, chip size can be minimized.

FIG. 3 is a circuit diagram for describing the read circuit shown in FIG. 1. Since the first read circuit 210_1 and the second read circuit 210_2 illustrated in FIG. 1 may have substantially the same circuit configuration, only the first read circuit 210_1 will be described. The circuit diagram shown in FIG. 3 is merely exemplary and is not limited thereto.

Referring to FIG. 3, the first read circuit 210_1 includes the discharge unit 211, the precharge unit 212, the compensator 214, the clamping unit 216, the sense amplifier 218, and the mux 219. And the like.

The precharge unit 212 precharges the sensing node to a predetermined level, for example, the power supply voltage VDD or the boosted voltage VPPSA during the precharge period, prior to the sensing operation. The precharge unit 212 may include a PMOS transistor controlled by a precharge control signal nPRE1 or nPRE2.

The compensator 214 compensates the level of the sensing node SDL generated by the current Icell flowing through the selected nonvolatile memory cell (MC of FIG. 2), and compensates the compensation current at the sensing node SDL. Serves to provide.

Specifically, when the nonvolatile memory cell is in the set state, the resistance of the phase change material is small because the resistance of the phase change material is small. In the reset state, the penetration current (Icell) is large because the resistance of the phase change material is large. ) Is small. Here, the amount of compensation current provided by the compensator 214 may be a degree to compensate for the through current Icell in the reset state. In this way, the level of the sensing node SDL in the reset state is kept constant, while the level of the sensing node SDL in the set state is lowered. Therefore, since the level of the sensing node SDL in the reset state and the level of the sensing node SDL in the set state have a large difference, it is easy to distinguish the set state from the reset state. In this way, the sensing margin can be increased. The compensation unit 214 may include a PMOS transistor controlled by the compensation control signal nPBIAS and a PMOS transistor controlled by the voltage signal VBIAS.

The clamping unit 216 clamps the level of the bit line BL coupled with the selected nonvolatile memory cell within a range suitable for reading. Specifically, clamping is performed at a predetermined level below the threshold voltage Vth of the phase change material. This is because the phase of the phase change material of the selected nonvolatile memory cell may change when the level exceeds the threshold voltage Vth. The clamping unit 216 may include an NMOS transistor controlled by a clamping control signal VCMP.

The discharge unit 211 discharges the sensing node SDL after the sensing operation. The discharge unit 211 may include an NMOS transistor controlled by a discharge control signal PDIS.

The sense amplifier 218 compares the level of the sensing node SDL with the reference level Vref and outputs a comparison result. The sense amplifier 218 may be a current sense amplifier or a voltage sense amplifier. The sense amplifier 218 is enabled by the sense amplifier control signal PSA.

The mux 219 selectively outputs the output signal of the sense amplifier 218. The mux 219 is enabled by the mux control signal PMUX.

FIG. 4 is a block diagram illustrating the shared decoder illustrated in FIG. 1. For example, the shared decoder 220 receives and decodes the first codeword RSACW.

Referring to FIG. 4, the shared decoder 220 may include a syndrome generator 222, an error position detector 224, an error corrector 226, and the like.

The syndrome generator 222 generates a syndrome SDR using the message data M_DATA and the parity bit ECCP (ie, the first codeword RSACW). The error location detector 224 uses the syndrome SDR to determine the error location of the message data M_DATA. For example, the error location detector 224 may use two or more syndromes (SDRs) to calculate the coefficients of the error location equation, and detect the error location based on the coefficients. The error corrector 226 corrects an error of the message data M_DATA based on the detected error position. The corrected message data is called CORRECTED_RSADATA.

FIG. 5 is a block diagram illustrating the signal generator described with reference to FIG. 1.

Referring to FIG. 5, the signal generator 310 may include a protection signal generator 320 and a selection signal generator 330.

In detail, the protection signal generator 320 receives the first pulse RAP generated based on the RWW read command and generates the protection signal ECCDECPRO enabled in at least a part of the read period of the RWW operation. In addition, the protection signal generator 320 may generate a first sensing start signal RSA_START and a first sensing end signal RSA_DONE respectively indicating the sensing start and the end during the RWW operation.

The selection signal generator 330 may receive the second pulse WSAP generated based on the RMW read command and generate the selection signal WSADECEN based on whether the protection signal ECCDECPRO is enabled. In addition, the selection signal generator 330 may generate a second sensing start signal WSA_START and a second sensing end signal WSA_DONE respectively indicating sensing start and end during the RMW operation.

FIG. 6 is a block diagram illustrating in detail the signal generator described with reference to FIG. 5.

Referring to FIG. 6, the protection signal generator 320 includes first delay units 324 and 326 and a first SR latch 322.

The first delay units 324 and 326 may delay the first pulse RSP to generate the first sensing start signal RSA_START and the first sensing end signal RSA_DONE.

The first SR latch 322 receives the first pulse RSAP and the first sensing end signal RSA_DONE to generate a protection signal ECCDECPRO. In a state where the first sensing end signal RSA_DONE is logic 0, When the first pulse RSAP is input (ie, logic 1 is input), the protection signal ECCDECPRO is enabled (eg, becomes logic 1). In addition, when the first sensing end signal RSA_DONE changes from logic 0 to logic 1, the protection signal ECCDECPRO is disabled.

The selection signal generator 330 does not immediately generate the selection signal WSADECEN even when the second pulse WSAP is input. The selection signal generator 330 checks the level of the protection signal ECCDECPRO and the level of the first sensing end signal RSA_DONE, and then generates the selection signal WSADECEN according to the result.

The selection signal generator 330 includes a second delay unit 332, a D flip-flop 334, an operation unit 336, 338, and 342, a third delay unit 344, and a second SR latch 346. can do.

The second delay unit 332 delays the second pulse WSAP to generate the check signal CK.

The D flip-flop 334 transmits a protection signal ECCDECPRO in response to the check signal CK.

The calculators 336, 338, and 342 receive the check signal CK, the transferred protection signal ECCDECPRO, and the first sensing end signal RSA_DONE. Here, the operation units 336, 338, and 342 include a first AND gate 336, a second AND gate 338, and an OR gate 342. The first AND gate 336 is provided with an inverted signal of the protection signal ECCDECPRO and a check signal CK. In addition, the second AND gate 338 is provided with the protection signal ECCDECPRO and the first sensing end signal RSA_DONE. The OR gate 342 is provided with the output of the first AND gate 336 and the output of the second AND gate 338.

The third delay unit 344 delays the output of the calculators 336, 338, and 342 to generate the second sensing end signal WSA_DONE. The second SR latch 346 receives the output of the operation units 336, 338, and 342 and the second sensing end signal WSA_DONE to generate a selection signal.

Here, the operations of the calculation units 336, 338, and 342 are summarized as follows.

When the second pulse WSAP is input, the level of the protection signal ECCDECPRO or the level of the first sensing end signal RSA_DONE is checked.

Suppose that the protection signal ECCDECPRO is in an enabled state (ie, a logic 1 state) at the time when the second pulse WSAP is input.

Therefore, since the inverted signal of the protection signal ECCDECPRO becomes logic zero, the first AND gate 336 outputs logic zero. In addition, since the protection signal ECCDECPRO is logic 1 but the first sensing end signal RSA_DONE is logic 0, the second AND gate 338 outputs logic 0. Thus, OR gate 342 also outputs logic zero. As a result, the selection signal WSADECEN also becomes logic zero. In summary, when the protection signal ECCDECPRO is enabled, the selection signal WSADECEN becomes logic zero.

In addition, when the sensing operation is terminated during the RWW operation, the first sensing end signal RSA_DONE is enabled (that is, logic 1). Accordingly, the second AND gate 338 outputs logic 1. Thus, the OR gate 342 also outputs logic one. As a result, the selection signal WSADECEN becomes logic one. In summary, when the sensing operation is terminated during the RWW operation, the selection signal WSADECEN becomes logic 1.

FIG. 7 is a timing diagram for describing an operation of the signal generator of FIG. 6. The timing diagram of FIG. 7 is merely exemplary and is not limited thereto.

3, 6, and 7, first, an RMW read command is input. Accordingly, the second compensation control signal PBIAS_WSA is enabled. According to the second compensation control signal PBIAS_WSA, the second pulse WSAP is enabled (see symbol a). According to the second pulse WSAP, the second sense amplifier control signal PSA_WSA is enabled (see symbol b).

On the other hand, the RWW read command is input later than the RMW read command. Accordingly, the first compensation control signal PBIAS_RSA is enabled. According to the first compensation control signal PBIAS_RSA, the first pulse RSAP is enabled (see symbol c). Here, according to the first pulse RSAP, the protection signal ECCDECPRO is enabled (see symbol d). The first sense amplifier control signal PSA_RSA is enabled according to the first pulse RSAP (see reference symbol e).

According to the first sense amplifier control signal PSA_RSA, the first sensing start signal RSA_START is enabled (see symbol f). According to the first sensing start signal RSA_START, the first mux control signal PMUX_RSA is enabled. Therefore, the first codeword RSACW, which is a sensing result, starts to be output (see symbol h). After a certain time elapses, the first mux control signal PMUX_RSA is disabled. According to the disabled first mux control signal PMUX_RSA, the first sensing end signal RSA_DONE is enabled (see symbol i).

As described above, according to the first sensing end signal RSA_DONE, the protection signal ECCDECPRO is disabled (see symbol j). When the protection signal ECCDECPRO is disabled in the enabled state (ie, in response to the falling edge of the protection signal ECCDECPRO), the selection signal WSADECEN is enabled (see symbol k).

When the selection signal WSADECEN is enabled, the second sensing start signal RSA_START is enabled (see symbol l). According to the second sensing start signal RSA_START, the second mux control signal PMUX_WSA is enabled (see symbol m). Accordingly, the second codeword WSACW, which is a sensing result, starts to be output (see reference numeral n). After a certain time elapses, the second mux control signal PMUX_WSA is disabled. According to the disabled second mux control signal PMUX_WSA, the second sensing end signal WSA_DONE is enabled (see symbol o). According to the second sensing end signal WSA_DONE, the selection signal WSADECEN is disabled.

In summary, even if the RMW read command is input first and the RWW read command is input later, if the second read circuit 210_2 does not start the RMW read operation, the first read circuit 210_1 performs the RWW read operation first. .

When the protection signal ECCDECPRO is in the enabled state, the second read circuit 210_2 may not perform the RMW read operation. This is because the selection signal WSADECEN is not enabled when the protection signal ECCDECPRO is enabled when the second pulse WSAP based on the RMW read command is input to the signal generator 310.

After the predetermined time has elapsed, when the protection signal ECCDECPRO becomes disabled from the enabled state, the selection signal WSADECEN is enabled. Accordingly, the second read circuit 210_2 may perform an RMW read operation.

8 is a block diagram illustrating a nonvolatile memory device in accordance with another embodiment of the present invention. For convenience of explanation, the description will be mainly focused on the contents different from those described with reference to FIGS. 1 to 7.

Referring to FIG. 8, the nonvolatile memory device 2 according to another exemplary embodiment of the present invention does not include a shared decoder (see 220 of FIG. 1). The first decoder 220_1 decoding the first codeword RSACW provided from the first read circuit 210_1 and the second decoder decoding the second codeword WSACW provided from the second read circuit 210_2. 220_2). However, the first decoder 220_1 and the second decoder 220_2 receive the selection signal WSADECEN from the signal generator 310 and operate exclusively. That is, the first decoder 220_1 and the second decoder 220_2 do not perform the decoding operation at the same time. For example, when the selection signal WSADECEN is at a first level (eg, logic 0), the first decoder 220_1 may decode the first codeword RSACW, and the selection signal WSADECEN may be When at the second level (eg, logic 1), the second decoder 220_2 may decode the second codeword WSACW.

As described above, the signal generator 310 further generates a protection signal ECCDECPRO that is enabled in at least a portion of the read interval of the RWW operation, and the signal generator 310 based on whether the protection signal ECCDECPRO is enabled. Therefore, the selection signal WSADECEN can be enabled.

Although not shown, when the protection signal ECCDECPRO is in the enabled state, the second read circuit 210_2 does not perform the RMW read operation even when the RMW read command is input.

In addition, when the RMW read command is input when the protection signal ECCDECPRO is in an enabled state, the second read circuit 210_2 may perform the RMW read operation after the protection signal ECCDECPRO is disabled.

On the other hand, the nonvolatile memory device 2 according to another embodiment of the present invention, even without adopting the shared decoder 220, the first decoder 220_1 used in the normal read operation (or RWW read operation) and the RMW read The second decoder 220_2 used in the operation does not operate at the same time. Therefore, noise that may occur when two decoders 220_1 and 220_2 operate simultaneously does not occur.

9 is a block diagram illustrating a memory system in accordance with some embodiments of the present invention.

Referring to FIG. 9, the memory system 1000 includes a nonvolatile memory device 1100 and a controller 1200.

The nonvolatile memory device 1100 may be configured and operate in the same manner as described with reference to FIGS. 1 to 8.

The controller 1200 is connected to a host and the nonvolatile memory device 1100. In response to a request from the host, the controller 1200 is configured to access the nonvolatile memory device 1100. For example, the controller 1200 is configured to control read, write, erase, and background operations of the nonvolatile memory device 1100. The controller 1200 is configured to provide an interface between the nonvolatile memory device 1100 and the host. The controller 1200 is configured to drive firmware for controlling the nonvolatile memory device 1100.

In exemplary embodiments, the controller 1200 may further include well-known components, such as random access memory (RAM), a processing unit, a host interface, and a memory interface. The RAM is used as at least one of an operating memory of the processing unit, a cache memory between the nonvolatile memory device 1100 and the host, and a buffer memory between the nonvolatile memory device 1100 and the host. do. The processing unit controls the overall operation of the controller 1200.

The host interface includes a protocol for performing data exchange between the host and the controller 1200. For example, the controller 1200 may include a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-express) protocol, an advanced technology attachment (ATA) protocol, External (host) through at least one of a variety of interface protocols, such as Serial-ATA protocol, Parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol. Are configured to communicate with each other. The memory interface interfaces with the nonvolatile memory device 1100. For example, the memory interface includes a NAND interface or a NOR interface.

The memory system 1000 may be configured to additionally include an error correction block. The error correction block is configured to detect and correct an error of data read from the nonvolatile memory device 1100 using an error correction code (ECC). By way of example, the error correction block is provided as a component of the controller 1200. The error correction block may be provided as a component of the nonvolatile memory device 1100.

The controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device. For example, the controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device to configure a memory card. For example, the controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device such that a personal computer memory card international association (PCMCIA), a compact flash card (CF), and a smart media card (SM, Memory cards such as SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash storage (UFS) and the like.

The controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device to configure a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 10 is used as a semiconductor drive SSD, an operation speed of a host connected to the memory system 1000 is significantly improved.

As another example, the memory system 1000 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, A mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box A digital camera, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, Ha Is provided as one of various components of an electronic device, such as one of a variety of electronic devices, one of various electronic devices that make up a telematics network, an RFID device, or one of various components that make up a computing system.

In exemplary embodiments, the nonvolatile memory device 1100 or the memory system 1000 may be mounted in various types of packages. For example, the nonvolatile memory device 1100 or the memory system 1000 may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), and plastic dual in. Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer -Can be packaged and implemented in the same way as Level Processed Stack Package (WSP).

FIG. 10 is a block diagram illustrating an application example of the memory system of FIG. 9.

Referring to FIG. 10, the memory system 2000 includes a nonvolatile memory device 2100 and a controller 2200. The nonvolatile memory device 2100 includes a plurality of nonvolatile memory chips. The plurality of non-volatile memory chips are divided into a plurality of groups. Each group of the plurality of nonvolatile memory chips is configured to communicate with the controller 2200 through one common channel. For example, the plurality of nonvolatile memory chips are shown to communicate with the controller 2200 through the first through kth channels CH1 through CHk.

Each nonvolatile memory chip is configured similarly to the nonvolatile memory device 100 described with reference to FIGS. 1 to 8.

In FIG. 10, a plurality of nonvolatile memory chips are connected to one channel. However, it will be understood that the memory system 2000 can be modified such that one non-volatile memory chip is connected to one channel.

FIG. 11 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 10.

Referring to FIG. 11, the computing system 3000 includes a central processing unit 3100, a random access memory (RAM) 3200, a user interface 3300, a power supply 3400, and a memory system 2000. .

The memory system 2000 is electrically connected to the central processing unit 3100, the RAM 3200, the user interface 3300 and the power source 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

In FIG. 11, the nonvolatile memory device 2100 is illustrated as being connected to the system bus 3500 through the controller 2200. However, the nonvolatile memory device 2100 may be configured to be directly connected to the system bus 3500.

In FIG. 11, the memory system 2000 described with reference to FIG. 10 is provided. However, the memory system 2000 may be replaced with the memory system 1000 described with reference to FIG. 9.

In exemplary embodiments, the computing system 3000 may be configured to include all of the memory systems 1000 and 2000 described with reference to FIGS. 9 and 10.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1: nonvolatile memory device 190: memory core
210_1: first lead circuit 210_2: second lead circuit
220: decoder 301: first selector
302: second selector

Claims (10)

A memory core including a plurality of nonvolatile memory cells;
A first read circuit which reads a first codeword from the memory core during a read while write (RWW) operation;
A second read circuit which reads a second codeword from the memory core during a read modulation write (RMW) operation; And
And a shared decoder shared by the first read circuit and the second read circuit and selectively decoding the first codeword or decoding the second codeword. The method of claim 1,
And a signal generator for generating a selection signal that determines whether the shared decoder can decode the first codeword or the second codeword. The method of claim 2,
The signal generator further generates a protection signal enabled in at least a portion of the read period of the RWW operation,
And the signal generator enables the selection signal based on whether the protection signal is enabled. The method of claim 3,
And the selection signal is enabled when the protection signal is disabled in the enabled state. The method of claim 3,
And the second read circuit does not perform an RMW read operation when the protection signal is enabled. The method of claim 3,
And the second read circuit performs an RMW read operation after the protection signal is disabled. The method of claim 1,
And the first read circuit performs the RWW read operation first, even if the RMW read command is input first and the RWW read command is input later, if the second read circuit has not started the RMW read operation. The method of claim 1,
Further comprising a selector that operates in response to the selection signal,
When the selection signal is at the first level, the selector couples the first read circuit and the shared decoder,
And the selector couples the second read circuit and the shared decoder when the select signal is at a second level. A memory core including a plurality of nonvolatile memory cells;
A first read circuit which reads a first codeword from the memory core during a read while write (RWW) operation;
A second read circuit which reads a second codeword from the memory core during a read modulation write (RMW) operation;
A first decoder coupled with the first read circuit to decode the first codeword; And
A second decoder coupled with the second read circuit to decode the second codeword,
And the first decoder and the second decoder do not perform a decoding operation at the same time. A protection signal generation unit receiving a first pulse generated based on the RWW read command and generating a protection signal enabled in at least a part of a read period of the RWW operation; And
And a selection signal generator configured to receive a second pulse generated based on an RMW read command and generate a selection signal based on whether the protection signal is enabled.

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