KR20130008724A - Multi-layered complex chip device - Google Patents

Abstract

PURPOSE: A stack complex chip element is provided to protect an electronic component from over voltage by using a varistor. CONSTITUTION: A suppressor layer overlapped with a part of the first inner electrode(13) and the second inner electrode(11). The suppressor layer includes a discharge unit(15). A discharge unit is formed between the first inner electrode and the second inner electrode. The discharge unit includes a depletion layer. The discharge unit is made of varistor powder.

Description

Multi-layered complex chip device

The present invention relates to a stacked composite chip device, and more particularly, to a stacked composite chip device in which an internal circuit is protected from static electricity.

Use a varis- tor to protect the circuit from abnormal voltages. Varistors are widely used as protection devices to protect important electronic components and circuits from overvoltage (surge voltage) and static electricity because the resistance changes according to the applied voltage.

No current flows through the varistors normally arranged in the circuit. However, if an overvoltage is applied at both ends of the varistor due to an overvoltage or more, a resistance of the varistor decreases rapidly, almost all current flows through the varistor, and no current flows to other elements, so that the circuit in which the varistor is disposed is protected from overvoltage.

In recent years, high-frequency, digital, high-integration, complex, light and thin, and low-cost, such as communication, information equipment, AV equipment is rapidly progressing.

As a result, communication, information equipment, AV equipment, and the like gradually become vulnerable to static electricity, and the demand and necessity of chip varistors are rapidly increasing. For example, as the transmission / reception frequency of mobile phones has recently been increased to more than GHz, and as expensive semiconductor chips contained in mobile phones have been directly integrated, vulnerability to static electricity is increasing day by day.

Accordingly, there is a need to block the inflow of static electricity through antennas or data transmission ports, which have not been a problem in the past.

In addition to varistors, an ESD absorber is also used to eliminate overvoltage and static electricity. Typically, the ESD absorber arranges a predetermined empty space between internal electrodes to block a relatively large overvoltage or overcurrent.

However, the ESD absorber exhibits excellent attenuation performance at a high level of ESD voltage, but has a low level of ESD voltage (for example, approximately ESD 3KV or less) There is a problem in that no operation is performed.

It is an object of the present invention to provide a stacked composite chip device having improved discharge resistance by forming a discharge portion between internal electrodes to protect the internal circuit from static electricity.

According to a feature of the present invention for achieving the above object, the present invention is formed by overlapping a portion of the first internal electrode and the second internal electrode and the discharge portion between the first internal electrode and the second internal electrode; The suppressor layer is formed, and a depletion layer is included in the said discharge part.

At least one of the first internal electrode and the second internal electrode is made of Ag: 80 to 99.5wt% and Pd: 0.5 to 20wt%.

The material forming the discharge part includes varistor calcined powder and glass.

The suppressor layer is formed of sheets of LTCC material.

One end of the first internal electrode is connected to the first external terminal, and one end of the second internal electrode is connected to the second external terminal and electrically connected thereto.

And a suppressor layer formed to overlap a portion of the first internal electrode and the second internal electrode and having a discharge portion formed between the first internal electrode and the second internal electrode, and between the first internal electrode and the discharge portion, An insulating layer is included in at least one of the second internal electrode and the discharge unit.

The first and second internal electrodes are made of Ag.

The material forming the discharge part includes varistor calcined powder and glass.

The insulating layer is made of at least one selected from Al ₂ O ₃ , ZrO, MgO.

The thickness of the insulating layer is in the range of 4.5 ~ 8㎛.

The suppressor layer is formed of sheets of LTCC material.

One end of the first internal electrode is connected to the first external terminal, and one end of the second internal electrode is connected to the second external terminal and electrically connected thereto.

According to the present invention, since a small amount of Ag contained in the discharge part is diffused and moved to the internal electrode during firing, a depletion layer without Ag is formed in the discharge part, thereby blocking the Ag pass, thereby improving ESD resistance.

In addition, the present invention can control the characteristics of the capacitance by using the interval between the first and second internal electrodes and can be adjusted because the capacitance can be adjusted by increasing the number of internal electrodes because the stacking type has the effect that it is easy to control the capacitance. .

In addition, since the insulating layer is included in at least one of the first internal electrode and the discharge unit, and between the second internal electrode and the discharge unit, the Ag pass is blocked to improve the ESD resistance.

In addition, the insulating layer has the effect of removing the operating voltage by changing the thickness while ensuring insulation.

1 is a block diagram showing a preferred embodiment of a stacked composite chip device according to the present invention.
2 shows a depletion layer after firing according to the internal electrode material.
3 is an enlarged view of a portion A in Fig. 2
Figure 4 is a block diagram showing another embodiment of a stacked composite chip device according to the present invention.
5 is a graph showing the relationship between the insulating layer and the operating voltage as a result of Table 3.
6 is a SEM photograph showing the suppressor layer when there is no insulation layer and when there is an insulation layer as a result of Table 3. FIG.
Figure 7 is a SEM photograph showing the suppressor layer according to the insulation layer thickness as a result of Table 4.
8 is a graph showing the relationship between the insulating layer thickness and the operating voltage as a result of Table 4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(One embodiment)

As shown in FIG. 1, in the stacked composite chip device according to an exemplary embodiment, a part of the first internal electrode 11 and the second internal electrode 13 are formed to overlap each other, and the discharge part 15 is formed between the overlapped ones. The depressor layer 19 is included, and the depletion layer 17 without Ag is included in the discharge part 15.

The first internal electrode 11 and the second internal electrode 13 are formed to be spaced apart vertically, and a part of the first internal electrode 11 and a part of the second internal electrode 13 overlap each other and overlap each other. The discharge unit 15 is printed. One end of the first internal electrode 11 is connected to the first external terminal 21 and one end of the second internal electrode 13 is electrically connected to the second external terminal 23.

The first internal electrode 11 and the second internal electrode 13 are formed of a conductive material. At least one of the first internal electrode 11 and the second internal electrode 13 is made of Ag and Pd, and specifically, Ag: 80 to 99.5 wt%, and Pd: 0.5 to 20 wt%.

Ag has excellent electrical conductivity, low resistance, and low temperature sintering.

When both the first and second internal electrodes are 100% Ag, Ag ions are released due to environmental influences such as voltage application, humidity, and temperature during chip operation. Form a path. Ag pass formation changes the non-conducting discharge portion into a conductor, causing a short and weakening electrostatic discharge (ESD) resistance. ESD means that a charged object is brought into contact with another object and charge transfer occurs in a short moment of 200 ns or less.

When the internal electrode is made of Ag and Pd, when Ag exceeds 99.5 wt% with respect to the total weight of the internal electrode, a problem occurs that a partial Ag pass is formed in the discharge part, and when it is less than 80 wt%, the electrical conductivity characteristic becomes low. There is.

Pd included in the internal electrode is used to form a depletion layer without Ag in the discharge portion during firing.

Ag and Pd are electrolytic solid solutions having the property of forming alloys with each other. Ag and Pd tend to attract each other to form a solid solution at the time of firing. At this time, Ag having a smaller specific gravity moves toward Pd having a higher specific gravity to form a total solid solution.

The discharge part 15 to be described below includes a small amount of Ag in the material itself, and the Ag diffuses and moves toward an internal electrode including Pd during firing, thereby forming a depletion layer 17 without Ag in the discharge part 15. do.

If Pd is less than 0.5wt% of the total weight of the internal electrode, Ag pass is partially formed in the discharge part, so that it is difficult to enhance ESD resistance, and if it exceeds 20wt%, the electrical conductivity is lowered due to the relative decrease of Ag content.

The discharge unit 15 absorbs static electricity when the external electrostatic discharge is introduced into the internal electrodes 11 and 13 through the external terminals 21 and 23 to induce discharge. Static electricity causes damage and malfunction of electronic components such as circuits. The material constituting the discharge portion 15 includes varistor calcined powder and glass.

After firing, a depletion layer free of Ag is formed in the discharge portion by Pd included in the internal electrode. The depletion layer blocks the Ag pass to improve the ESD resistance of the discharge.

The suppressor layer 19 may include a discharge unit 15 printed between the first internal electrode 11, the second internal electrode 13, and the first internal electrode 11 and the second internal electrode 13. ).

The suppressor layer 19 is formed of sheets made of Low Temperature Co-fire Ceramics (LTCC) material. LTCC materials have the advantages of miniaturization, high functionalization and complexation of low temperature and high frequency components. LTCC can be sintered below 1000 ℃, which is about 50 ~ 65% higher than that of general ceramics sintering temperature 1300 ~ 1600 ℃. As the LTCC material, SiO ₂ or Al ₂ O ₃ series can be used.

For reference, FIG. 1 illustrates that the first internal electrode 11 and the second internal electrode 13 exist one by one, but the first internal electrode 11 and the second internal electrode 13 are alternately multiple times. It may be regarded as being stacked, the number is not limited and can be changed depending on the characteristics of the desired capacitance.

Since the capacitance increases in proportion to the size of the area of the portion where the first internal electrode 11 and the second internal electrode 13 overlap, the characteristics of the capacitance are controlled by using the gap between the internal electrodes 11 and 13. The capacitance can be adjusted by increasing the number of internal electrodes 11 and 13.

Hereinafter, a method of manufacturing a stacked composite chip device will be described. For convenience of explanation, a process of manufacturing the suppressor layer will be described.

First, a slurry is manufactured in order to manufacture the several molded sheet | seat which can comprise a suppression layer in a body. For example, raw material powder is prepared by ball milling SiO ₂ or Al ₂ O ₃ -based LTCC material with water or alcohol with a solvent for 24 hours.

The PVB binder is added to the prepared raw material powder in an amount of about 6 wt% relative to the raw material powder and dissolved in a toluene / alcohol solvent. The slurry is then milled and mixed for about 24 hours in a small ball mill. The numerical values illustrated above are only examples and may vary depending on the manufacturing environment and needs.

Such a slurry is subjected to a method such as a doctor blade to produce a sheet having a desired thickness (e.g., about 15 mu m). The produced sheet is cut into desired length units to produce a plurality of sheets.

When the thickness of the sheet is set to about 15 탆, shrinkage in later lamination, compression bonding, and firing steps is taken into consideration. When the lamination, pressing, and firing steps are performed in the future, the thickness of one formed sheet becomes about 10 mu m.

Thereafter, first and second internal electrodes are printed on each sheet. At least one of the first and second internal electrodes is printed with a paste using a powder composed of Ag: 80 to 99.5wt% and Pd: 0.5 to 20wt%. In this case, the other one is printed with a paste using 100 wt% Ag.

Of course, both the first and second internal electrodes may be printed with a paste using a powder composed of Ag: 80 to 99.5wt% and Pd: 0.5 to 20wt%.

Subsequently, the discharge unit is printed on the second inner electrode as the lowermost layer, and the first inner electrode is stacked. When a plurality of internal electrodes are laminated in this way to form a body, the body is pressed after lamination. Use a pressure of approximately 500 to 3000 psi during lamination and pressing.

Next, the degreasing and baking process is performed with respect to the body formed by lamination | stacking and compression. The degreasing process is performed at about 300 ° C. and then calcined at about 800 ° C. to 900 ° C.

When the stacking, pressing, and firing processes are sequentially performed, the depletion layer 17 without Ag is included in the discharge part 15, and the depletion layer blocks the Ag pass, thereby manufacturing a multilayer composite chip device having improved ESD resistance. Will be.

Hereinafter, an embodiment of the present invention will be described in more detail with reference to the invention and comparative examples. However, it should be noted that the scope of an embodiment of the present invention is not limited by the following invention examples.

Table 1 shows the electrical characteristics of the multilayer composite chip device according to the internal electrode material.

The discharge part used glass.

division First internal electrode Second internal electrode Leakage current
(μA) Capacitance
(pF) DC load short
(%) Comparative Example 1 Ag (100 wt%) Ag (100 wt%) 0.00002 0.211 1.34 Inventory 1 Ag (80 wt%) +
Pd (20 wt%) Ag (80 wt%) +
Pd (20 wt%) 0.00001 0.128 0.00 Inventive Example 2 Ag (98.5 wt%) +
Pd (1.5 wt%) Ag (98.5 wt%) +
Pd (1.5 wt%) 0.00001 0.146 0.00 Inventory 3 Ag (100 wt%) Ag (98.5 wt%) +
Pd (1.5 wt%) 0.00001 0.168 0.00 Honorable 4 Ag (99.5 wt%) +
Pd (0.5 wt%) Ag (99.5 wt%) +
Pd (0.5 wt%) 0.00001 0.170 0.00 Comparative Example 2 Ag (99.6 wt%) +
Pd (0.4 wt%) Ag (99.6 wt%) +
Pd (0.4 wt%) 0.000015 0.198 1.32

Referring to Table 1, when at least one of the first internal electrode and the second internal electrode is made of Ag: 80 to 99.5 wt% and Pd: 0.5 to 20 wt%, it satisfies low capacitance of less than 1 pF, minimizes leakage current, and shorts. Does not occur. Larger leakage currents can cause malfunctions.

On the other hand, in Comparative Examples 1 and 2, a short occurred at DC load.

Table 2 shows the ESD resistance of the stacked composite chip device according to the internal electrode material.

(contact 8kV fixed) division First internal electrode Second internal electrode Before authorization 1 time
After authorization 5 times
After authorization 10th
After authorization Comparative Example 1 Ag (100 wt%) Ag (100 wt%) 0.00002 0.00017 0.00009 short Inventory 1 Ag (80 wt%) +
Pd (20 wt%) Ag (80 wt%) +
Pd (20 wt%) 0.00002 0.00001 0.00001 0.00002 Inventive Example 2 Ag (98.5 wt%) +
Pd (1.5 wt%) Ag (98.5 wt%) +
Pd (1.5 wt%) 0.00002 0.20214 0.00048 0.00004 Inventory 3 Ag (100 wt%) Ag (98.5 wt%) +
Pd (1.5 wt%) 0.00001 0.00001 0.00005 0.59073 Honorable 4 Ag (99.5 wt%) +
Pd (0.5 wt%) Ag (99.5 wt%) +
Pd (0.5 wt%) 0.00001 0.017012 0.00018 0.00005 Comparative Example 2 Ag (99.6 wt%) +
Pd (0.4 wt%) Ag (99.6 wt%) +
Pd (0.4 wt%) 0.00001 0.00020 0.00011 short

Referring to Table 2, when the content of Ag exceeds 99.5 wt%, both internal electrodes are vulnerable to EDS as the number of applications increases, and a short occurs after 10 applications.

2 is a view showing a depletion layer after firing according to the internal electrode material, and FIG. 3 is an enlarged view of portion A of FIG. 2.

2 and 3, when at least one of the first internal electrode and the second internal electrode is made of Ag: 80 to 99.5wt% and Pd: 0.5 to 20wt%, the depletion layer without Ag is formed in the discharge portion. It was formed, the area of the depletion layer was increased with the higher content of Pd.

On the other hand, when both the first and second internal electrodes were 100wt% Ag, an Ag pass was formed, a large leakage current, a high capacitance, and a short circuit occurred after 10 application times.

Through this, when at least one of the first internal electrode and the second internal electrode is made of Ag: 80 ~ 99.5 wt%, Pd: 0.5 ~ 20wt% it can be seen that the ESD resistance is improved and the occurrence of short is prevented.

(Another embodiment)

In another exemplary embodiment of the stacked composite chip device, as illustrated in FIG. 4, a part of the first internal electrode 11 and the second internal electrode 13 overlap each other, and the first internal electrode 11 and the second internal electrode are overlapped. And a suppressor layer 27 having a discharge portion printed between the internal electrodes 13, and between the first internal electrode 11 and the discharge portion 15, the second internal electrode 13 and the discharge portion 15. Insulation layer 25 is further included in at least one of).

Compared to one embodiment, another embodiment includes an insulating layer 25 that is physically inserted instead of a depletion layer 17 formed by a chemical method, and Ag is used as the first and second internal electrodes 11 and 13. There is a difference.

Specifically, the first and second internal electrodes 11 and 13 are made of 100% Ag, and the discharge part includes varistor calcined powder and glass.

As described above, 100% Ag has the advantages of excellent electrical conductivity, low resistance, and low temperature sintering, but due to environmental influence, Ag ions are released and released Ag ions react with the discharge part to partially pass the Ag pass to the discharge part. form a path.

The Ag pass should be blocked because it converts the non-conducting discharge part into a conductor, causing a short and weakening the electrostatic discharge (ESD) resistance.

An insulating layer 25 is included between at least one of the first internal electrode 11 and the discharge unit 15 and between the second internal electrode 13 and the discharge unit 15 to block the Ag pass.

The insulating layer 25 may be made of one or more selected from Al ₂ O ₃ , ZrO, and MgO. The insulating layer 25 separates at least one of the first and second internal electrodes 11 and 13 from the discharge part 15 to prevent Ag diffusion of the internal electrodes. Insulation layer can be used in the case of material which has insulation function and stable at high temperature besides Al ₂ O ₃ , ZrO, MgO.

The thickness of the insulating layer 25 is in the range of 4.5 to 8 mu m. The thickness of the insulating layer is to have an ESD discharge voltage while ensuring insulation.

In addition, since the thickness of the insulating layer 25 is related to the operating voltage of the stacked composite chip device, it is possible to control the operating voltage by adjusting the thickness of the insulating layer in the above-described range. However, if the insulating layer is less than 4.5㎛ thickness it is difficult to ensure insulation, if it exceeds 8㎛ it is preferable to control in the above range because the operating voltage is increased to 20kV or more.

The suppressor layer 27 is made of LTCC material, one end of the first internal electrode 11 is connected to the first external terminal 21, and one end of the second internal electrode 13 is the second external terminal 23. The other components, such as connected to and electrically connected), are the same as in the above-described exemplary embodiment, and thus detailed descriptions thereof will be omitted.

Hereinafter, another embodiment of the present invention will be described in more detail with reference to the invention and comparative examples.

Table 3 shows the effect of improving the ESD resistance of the multilayer composite chip device by inserting the insulating layer.

Experimental conditions: insulating layer (Al ₂ O ₃ ), the first and second internal electrodes (Ag), the discharge (glass)

division IL
@ 12V Cp (pF)
@ 1 MHz action
Voltage Reaction
Voltage Short when checking operation Waveform attenuation short DC test Insulating layer
(×) 0.034 0.135 4.5kV
(3 ~ 6kV) - 100% - 0.78% Insulating layer
(Al ₂ O ₃ layer
Simplex printing) 0.00013 0.124 8.3kV
(6 ~ 10kV) 3.85 kV
(3 ~ 7kV) 0% 0% 0% Insulating layer
(Al ₂ O ₃ layer
Duplex printing) 0.00001 0.123 15.35kV
(11 ~ 20kV) 5.2 kV
(4 ~ 6kV) 10% 0% 0%

[IL: current, DC test: insulation resistance]

Looking at Table 3, it is confirmed that the ESD resistance is improved by forming the insulating layer with a waveform reduction short and an insulation resistance of 0.

The results in Table 3 are also confirmed in Figs. 5 and 6, the operation voltage is increased by the insulating layer is formed, but the short generation is lowered and the insulation resistance is also lowered.

Table 4 shows the change of the operating voltage according to the insulation layer thickness.

division Al ₂ O ₃ Thickness (㎛) Operating voltage
(kV) Between the first internal electrode and the discharge unit Between the second internal electrode and the discharge unit Average A Insulating layer
(Al ₂ O ₃ layer
Duplex printing) 4.62 5.14 4.88 11 B 5.01 6 5.505 14 C 6.2 5.14 5.67 16 D 5.54 9.37 7.455 20

Referring to Table 4, FIG. 7, and FIG. 8, it is confirmed that the operating voltage increases as the thickness of the insulating layer becomes thick. It can be seen that it is possible to remove the operating voltage by changing the thickness of the insulating layer through this.

Although not shown, when the thickness of the insulating layer was less than 4.5 μm, it was shorted when the operation was confirmed and there was no improvement in ESD resistance.

Within the scope of the basic technical idea of the present invention, many other modifications are possible to those skilled in the art, and the scope of the present invention should be interpreted based on the appended claims. will be.

11: first internal electrode 13: second internal electrode
15: discharge part 17: depletion layer
19: suppressor layer 21: first external terminal
23: second external terminal 25: insulating layer
27: suppressor layer

Claims (12)

And a suppressor layer in which a part of the first internal electrode and the second internal electrode overlap each other, and a discharge part is formed between the first internal electrode and the second internal electrode.
Stacked composite chip device, characterized in that the discharge portion includes a depletion layer. The method according to claim 1,
At least one of the first internal electrode and the second internal electrode
Stacked composite chip device, characterized in that consisting of Ag: 80 ~ 99.5wt%, Pd: 0.5 ~ 20wt%. The method according to claim 1,
The material constituting the discharge portion is a laminated composite chip device, characterized in that it comprises a varistor calcined powder, glass. The method according to claim 1,
And wherein said suppressor layer is formed of sheets of LTCC material. The method according to claim 1,
One end of the first internal electrode is connected to the first external terminal, and one end of the second internal electrode is connected to the second external terminal is a multilayer composite chip device characterized in that it is electrically connected. And a suppressor layer in which a part of the first internal electrode and the second internal electrode overlap each other, and a discharge part is formed between the first internal electrode and the second internal electrode.
Stacked composite chip device, characterized in that an insulating layer is included between at least one of the first internal electrode and the discharge portion, between the second internal electrode and the discharge portion. The method of claim 6,
The first and second internal electrodes are stacked composite chip device, characterized in that made of Ag. The method of claim 6,
The discharge unit is a multilayer composite chip device, characterized in that it comprises a varistor calcined powder, glass. The method of claim 6,
The insulating layer is a stacked composite chip device, characterized in that consisting of at least one selected from Al ₂ O ₃ , ZrO, MgO. The method according to claim 6 or 9,
Stacked composite chip device, characterized in that the thickness of the insulating layer is in the range of 4.5 ~ 8㎛. The method of claim 6,
And wherein said suppressor layer is formed of sheets of LTCC material. The method of claim 6,
One end of the first internal electrode is connected to the first external terminal, and one end of the second internal electrode is connected to the second external terminal is a multilayer composite chip device characterized in that it is electrically connected.

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