KR20120133181A

KR20120133181A - Method for fabricating the array substrate in liquid crystal display device

Info

Publication number: KR20120133181A
Application number: KR1020110051721A
Authority: KR
Inventors: 남경진; 백정선
Original assignee: 엘지디스플레이 주식회사
Priority date: 2011-05-30
Filing date: 2011-05-30
Publication date: 2012-12-10

Abstract

PURPOSE: A method for fabricating an array substrate in a liquid crystal display device is provided to form a sacrificial reflection layer in the lower part of a photoresist layer and to form a photoresist pattern having a fine pattern by an exposure and development process. CONSTITUTION: A conductive layer(130) is formed on a substrate(100). A sacrificial light reflection layer(140) is formed on the conductive layer. A photoresist layer(151) is formed on the sacrificial light reflection layer. A photoresist pattern is formed by performing an exposure and developing process on the photoresist layer using a mask. The photoresist pattern is used as an etching mask. The sacrificial light reflection layer and a conductive layer are patterned. The photoresist pattern and the sacrificial light reflection layer are removed.

Description

Method for fabricating the array substrate in liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a method of manufacturing a liquid crystal display array substrate capable of improving light transmittance due to fine patterning of electrodes.

In general, the liquid crystal display device is not only driven by low power consumption, but also widely used in the display industry because of its thinness.

Such a liquid crystal display device includes a color filter substrate and a thin film transistor substrate corresponding to each other with a liquid crystal interposed therebetween. Here, when voltage is applied to the electrodes disposed on the color filter substrate and the thin film transistor substrate, the vertical electric fields formed by the applied voltage difference control the direction of the liquid crystal molecules. At this time, according to the direction of the liquid crystal molecules, the transmittance of the light passing through the liquid crystal is adjusted so that the liquid crystal display displays an image.

Here, when the liquid crystal display adopts a method of driving the liquid crystal by vertical electric fields up and down, there is a problem that the viewing angle characteristics are deteriorated. In order to solve this problem, a liquid crystal driving method using an in-plane switching (IPS) using a horizontal electric field has been proposed.

In such a transverse electric field type liquid crystal display, a pixel electrode having a bar shape and a common electrode are alternately arranged at predetermined intervals in each pixel. When the data voltage is applied to the pixel electrode and the common voltage is applied to the pixel electrode, the transverse electric field type liquid crystal display forms a transverse electric field in a horizontal direction with respect to the substrate. In this case, the liquid crystal is driven by the transverse electric field to provide an image having excellent left and right symmetrical viewing angle characteristics.

However, the transverse electric field type liquid crystal display device has improved viewing angle characteristics compared to other methods, but the liquid crystal corresponding to the upper portion of the pixel electrode and the upper portion of the common electrode is not driven, so that the light transmittance through the liquid crystal display device is reduced. there was.

Furthermore, when at least one of the common electrode and the pixel electrode is formed of a material that cannot transmit light, the light transmittance of the liquid crystal display may be further reduced.

Accordingly, the present invention has been made to solve a problem that may occur in a liquid crystal display device, and in particular, to provide a method of manufacturing a liquid crystal display array substrate capable of improving light transmittance due to fine patterning of electrodes. There is this.

Provided is a method of manufacturing a liquid crystal display array substrate of a solution according to the present invention. In the manufacturing method of the liquid crystal display device array substrate having a plurality of electrodes having a predetermined interval and each pixel on the substrate having a plurality of pixels,

The forming of the electrode may include forming a conductive layer on the substrate; Forming a sacrificial light reflection layer on the conductive layer; Forming a photoresist layer on the sacrificial light reflection layer; Forming a photoresist pattern by performing an exposure and development process using a mask on the photoresist layer; Patterning a sacrificial light reflection layer and a conductive layer using the photoresist pattern as an etching mask; And removing the photoresist pattern and the sacrificial light reflection layer.

Here, the method may further include forming a bonding auxiliary layer between the conductive layer and the sacrificial light reflection layer between forming the conductive layer on the substrate and forming the sacrificial light reflection layer on the conductive layer. have.

In addition, the bonding auxiliary layer may be formed of a material etched by the same etchant as the sacrificial light reflection layer.

In addition, the bonding auxiliary layer may be formed of Mo.

In addition, the bonding auxiliary layer may be formed in a thickness range of 50 kPa to 100 kPa.

In addition, the sacrificial reflective layer may be formed of any one of Al, AlNd, and AlPaCu.

In addition, the conductive layer may be formed of a single layer formed of any one of ITO, IZO, and MoTi, or a laminate of two or more.

In addition, the electrode may have a line width of 2㎛ to 3㎛.

In addition, the electrode may be at least one of a pixel electrode and a common electrode.

In addition, an embossing pattern may be further provided on the sacrificial light reflection layer.

In addition, the embossing pattern may be formed on the sacrificial light reflection layer corresponding to the opening of the mask.

The liquid crystal display array substrate according to the exemplary embodiment of the present invention may form a photoresist pattern having a fine pattern as a sacrificial reflective layer is provided under the photoresist layer and then subjected to an exposure and development process. Accordingly, due to the fine patterning of the photoresist pattern, it is possible to form an electrode having a fine line width, thereby improving the light transmittance of the liquid crystal display device.

1 is a plan view schematically illustrating a liquid crystal display array substrate according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.
3 to 8 are cross-sectional views illustrating a manufacturing process of a liquid crystal display array substrate according to a second embodiment of the present invention.
9 to 12 are cross-sectional views illustrating a manufacturing process of a liquid crystal display array substrate according to a third embodiment of the present invention.
13 is a photograph showing a side of a photoresist pattern according to a comparative example.
14 and 15 are photographs showing the side surfaces of the photoresist patterns according to Experimental Examples 1 and 2. FIG.
16 is a photograph showing the side surface of the photoresist pattern, Mo pattern, AlNd and ITO pattern according to Experimental Example 3.

Embodiments of the present invention will be described in detail with reference to the drawings of the liquid crystal display array substrate. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention.

Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 is a plan view schematically illustrating a liquid crystal display array substrate according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 2, a liquid crystal display array substrate according to an exemplary embodiment of the present invention may include a substrate 100, a gate wiring 101, a data wiring 102, a common wiring 103, and a thin film transistor Tr. The pixel electrode 132 and the common electrode 136 may be included.

In detail, the substrate 100 may be formed of a transparent substrate that may transmit light. In an embodiment of the present invention, the material and shape of the substrate 100 are not limited. For example, the material of the substrate 100 may be glass or resin. In addition, the shape of the substrate 100 may be in the form of a plate or film.

A plurality of pixel areas may be defined on the substrate 100. Here, the plurality of pixel regions may be defined by the gate wiring 101 and the data wiring 102 arranged to cross each other on the substrate 100. Here, the gate wiring 101 and the data wiring 102 may be insulated from each other by the gate insulating film 110 interposed therebetween.

The common wiring 103 may be spaced apart from the gate wiring 101 and disposed on the substrate 100. In this case, the gate wiring 101 and the common wiring 103 may be formed of the same conductive material.

The thin film transistor Tr may be disposed in each pixel area of the substrate 100. The thin film transistor Tr may include a gate electrode 104, a gate insulating layer 110, a semiconductor pattern 124, and source and drain electrodes 134 and 144.

The gate electrode 104 may be electrically connected to the gate wiring 101. Here, the gate electrode 104 may be formed by protruding a part of the gate wiring 101. That is, the gate electrode 104 and the gate wiring 101 may be integrally formed.

The gate insulating layer 110 is disposed on the substrate 100 including the gate electrode 104. Here, the gate insulating layer 110 may be formed of a silicon oxide film or a silicon nitride film, but the embodiment is not limited thereto.

The semiconductor pattern 124 may include an active pattern 124a and an ohmic contact pattern 124b. Here, the ohmic contact pattern 124b may be interposed between the active pattern 124a and the source electrode 134 and between the active pattern 124a and the drain electrode 144. Here, the active pattern 124a may be formed of amorphous silicon. In addition, the ohmic contact pattern 124b may be formed of amorphous silicon doped with impurities.

The source and drain electrodes 134 and 144 may be disposed on the semiconductor pattern 124 with a space spaced apart from each other, that is, a channel region. Here, the source electrode 134 is disposed on the semiconductor pattern 124 and is electrically connected to the data line 102. Here, the source electrode 134 may be formed by protruding a part of the data line 102. That is, the source electrode 134 and the data wire 102 may be integrally formed. In this case, the source electrode 134 may be formed to surround at least three surfaces of the drain electrode 144. Here, the source electrode 134 may have a 'U' shape. Accordingly, the surface area of the channel region between the source electrode 134 and the drain electrode 144 may be increased, and thus the electrical characteristics of the thin film transistor Tr may be improved.

The passivation layer 120 may be disposed on the substrate 100 including the thin film transistor Tr. Here, the passivation layer 120 may be made of an insulating material.

The pixel electrode 132 and the common electrode 136 may be disposed in each pixel area to form an electric field for driving the liquid crystal. The pixel electrode 132 and the common electrode 136 may be disposed on the passivation layer 120. The pixel electrode 132 may be electrically connected to the drain electrode 144 of the thin film transistor Tr through a contact hole formed in the passivation layer 120.

The pixel electrode 132 may be formed of a transparent conductive material that can transmit light. For example, the pixel electrode 132 may be formed of ITO or IZO. Alternatively, the pixel electrode 132 may be formed of any one of a double layer of MoTi, ITO and MoTi, and a double layer of IZO and MoTi.

However, the embodiment of the present invention does not limit the arrangement of the pixel electrode 132, and as another example, the pixel electrode 132 is disposed on the gate insulating layer 110 and integrally formed with the drain electrode 144. It may be.

The pixel electrode 132 may include first and second pixel electrodes 132a and 132b. Here, the first pixel electrode 132a may be spaced apart from each other in the pixel area. The first pixel electrode 132a may have a bar shape. In this case, the first pixel electrode 132a may have a bent structure to further improve the viewing angle. In addition, the second pixel electrode 132b may serve to electrically connect the plurality of first pixel electrodes 132a with each other. The second pixel electrode 132b may be integrally formed with the first pixel electrodes 132a. A portion of the second pixel electrode 132b may be electrically connected to the drain electrode 144 of the thin film transistor Tr. In addition, the second pixel electrode 132b may overlap the common wiring 103 with an insulating layer, for example, the gate insulating layer 110 and the passivation layer 120, to form a storage capacitance.

The common electrode 136 may be disposed on the passivation layer 120. Here, the common electrode 136 may be formed of a transparent conductor that can transmit light. For example, the common electrode 136 may be formed of ITO or IZO. Alternatively, the common electrode 136 may be formed of any one of a double layer of MoTi, ITO and MoTi, and a double layer of IZO and MoTi.

The common electrode 136 may include first and second common electrodes 136a and 136b. Here, the first common electrode 136a may be spaced apart from each other in the pixel area. In this case, the first common electrode 136a may be alternately disposed with the first pixel electrode 132a. Accordingly, the first common electrodes 136a may have a bent structure like the first pixel electrode 132a. In addition, the second common electrode 136 may serve to electrically connect the first common electrodes 136a to each other. Here, the second common electrode 136 may be electrically connected to the common wiring through the common contact hole formed in the passivation layer 120 and the gate insulating layer 110.

In the embodiment of the present invention, the common electrode 136 is described as being disposed on the passivation layer, but the present invention is not limited thereto. In another example, the common electrode 136 is disposed on the substrate 100, and the gate electrode 104 is disposed on the protective layer. It may be formed of the same material.

Further, in the exemplary embodiment of the present invention, the liquid crystal display is described as having alternately arranged pixel electrodes and a common electrode, but the present invention is not limited thereto. The liquid crystal display device includes a pixel electrode and a common electrode to form a fringe field. Any one of the electrodes may be spaced apart from each other, and the other electrode may be disposed in the form of a plate in the entire area of the pixel area. In this case, an insulating film, for example, a gate insulating film or a protective film may be interposed between the pixel electrode and the common electrode.

Here, when the electrical signal of the thin film transistor Tr is applied to the pixel electrode 132 and the common voltage is applied to the common electrode 136, between the first common electrode 136a and the first pixel electrode 132a. A transverse electric field may be formed in the. In this case, at least one of the first common electrode 136a and the first pixel electrode 132a may have a line width smaller than that of the prior art, for example, 2 μm to 3 μm. Here, the line width of the first pixel electrode or the first common electrode of the conventional liquid crystal display device is inevitably formed to exceed 3 μm due to process constraints. Accordingly, the line width of the first common electrode 136a or the first pixel electrode 132a can be reduced in the exemplary embodiment of the present invention, and the light transmittance of the liquid crystal display can be increased.

3 to 8 are cross-sectional views illustrating a manufacturing process of a liquid crystal display array substrate according to a second embodiment of the present invention.

Referring to FIG. 3, in order to manufacture a liquid crystal display array substrate, first, the common wiring 103 spaced apart from the gate wiring 101, the data wiring 102, and the gate wiring 101 intersecting each other on the substrate 100. In addition, the thin film transistor Tr is formed in the intersection region of the gate wiring 101 and the data wiring 102, that is, the pixel region.

Specifically, after the first conductive film is formed on the substrate 100, the first conductive film is patterned in a predetermined shape to form the gate wiring 101, the gate electrode 104 connected to the gate wiring 101, and the gate wiring 101. And common wiring 103 spaced apart from each other.

Thereafter, the gate insulating layer 110 is formed on the substrate 100 including the gate electrode 104, the gate wiring 101, and the common wiring 103. Here, the gate insulating layer 110 may be formed of a silicon oxide film or a silicon nitride film. In this case, the gate insulating layer 110 may be formed through chemical vapor deposition.

Thereafter, the semiconductor pattern 124 is formed on the gate insulating layer 110 corresponding to the gate electrode 104. The semiconductor pattern 124 may include an active pattern 124a and an ohmic contact pattern 124b formed by patterning an amorphous silicon layer and an amorphous silicon layer doped with impurities.

Subsequently, after the second conductive film is formed on the gate insulating film 110 including the semiconductor pattern 124, the second conductive film is patterned in a predetermined shape to intersect the data wiring 102 and the data wiring (intersecting with the gate wiring 101). A source electrode 134 electrically connected to the 102 and disposed on the semiconductor pattern 124 and a drain electrode 144 spaced apart from the source electrode 134 and disposed on the semiconductor pattern 124 may be formed. Here, the ohmic contact pattern 124b is etched using the source and drain electrodes 134 and 144 as an etch mask, so that the space between the source and drain electrodes 134 and 144 on the active pattern 124a, that is, the active pattern ( The channel region of 124a may be exposed.

Referring to FIG. 4, after the gate wiring 101, the data wiring 102, the common wiring 103, and the thin film transistor Tr are formed, the gate wiring 101, the data wiring 102, and the common wiring 103 are formed. ) And a passivation layer 120 having a contact hole 121 exposing the drain electrode 144 of the thin film transistor Tr on the gate insulating layer 110 including the thin film transistor Tr.

In order to form the passivation layer 120, an inorganic insulating material is deposited on the gate insulating layer 110 including the gate wiring 101, the data wiring 102, the common wiring 103, and the thin film transistor Tr. After forming the insulating film, the inorganic insulating film may be patterned to form a contact hole 121 exposing the drain electrode 144. Here, the inorganic insulating material may be a silicon nitride film or a silicon oxide film. In this case, the inorganic insulating layer may be formed through chemical vapor deposition.

In the process of forming the contact hole 121 exposing the drain electrode 144 in the passivation layer 120, although not shown in the drawing, a part of the common wiring 103 is exposed to the passivation layer 120 and the gate insulating layer 110. The common contact hole may be further formed.

In the embodiment of the present invention, the protective film is formed of an inorganic insulating film, but the present invention is not limited thereto. The protective film may be formed of an organic insulating film.

Referring to FIG. 5, after forming the passivation layer 120 including the contact hole 121, the conductive layer 130 and the sacrificial light reflection layer 140 are sequentially formed on the passivation layer 120.

The conductive layer 130 may be formed of any one of ITO, IZO, MoTi, a double layer of ITO and MoTi, and a double layer of IZO and MoTi. In addition, the sacrificial light reflection layer 140 may be formed of a material having a higher reflectance than other materials, such as Al, AlNd, and AlPaCu.

Here, as an example of the method of forming the conductive layer 130 and the sacrificial light reflection layer 140, a sputtering method or a vacuum deposition method may be mentioned.

In addition, although not illustrated, a bonding auxiliary layer may be further formed between the conductive layer 130 and the sacrificial light reflection layer 140. Here, the bonding auxiliary layer may serve to prevent the sacrificial light reflection layer 140 from filling the conductive layer 130 in the photo process. In this case, the bonding auxiliary layer may be formed of a material that is etched through the same etchant as the sacrificial light reflection layer 140. Accordingly, even if the bonding auxiliary layer is formed, it may be necessary to prepare a separate etchant, or to add an etching process or a separate removal process. For example, the bonding auxiliary layer may be formed of Mo.

In addition, the bonding auxiliary layer may be formed in a thickness range of 50 kPa to 100 kPa. This is because when the bonding auxiliary layer is formed to be less than 50 GPa, it may be difficult to form a uniform thin film in the process. In addition, when the bonding auxiliary layer is formed to exceed the thickness of 100 kHz, the etching process time by the bonding auxiliary layer can be increased.

After forming the conductive layer 130 and the sacrificial light reflection layer 140, a photoresist layer 151 is formed on the sacrificial light reflection layer 140. Here, the photoresist layer 151 may be formed through a general coating process.

After the photoresist layer 151 is formed, a mask M having an opening M1 and a blocking portion M2 is provided.

Thereafter, an exposure process of irradiating light onto the photoresist layer 151 including the mask M is performed. The light may be irradiated onto the photoresist layer 151 corresponding to the opening M1 of the mask M. In this case, the light may be reflected by the sacrificial light reflection layer 140 to be diffused into the photoresist layer 151 corresponding to the blocking portion M2 of the mask M. FIG.

Referring to FIG. 6, after performing an exposure process, the exposed photoresist layer 151 is developed to form a photoresist pattern 152. Here, the photoresist pattern 152 may be formed to have a smaller CD than the opening due to the light reflection of the sacrificial light reflection layer 140.

Referring to FIG. 7, the sacrificial light reflection layer 140 and the conductive layer 130 are sequentially etched using the photoresist pattern 152 as an etch mask, so that the sacrificial light reflection pattern 141 and the pixel electrode 132 and The common electrode 136 may be formed. In this case, the sacrificial light reflection pattern 141 is disposed on the pixel electrode 132 and the common electrode 136.

The pixel electrode 132 may include first and second pixel electrodes 132a and 132b. Here, a plurality of first pixel electrodes 132a may be disposed on the pixel area to be spaced apart from each other. The second pixel electrode 132b may electrically connect the first pixel electrodes 132a to each other and may be electrically connected to the drain electrode 144 of the thin film transistor Tr. In addition, the common electrode 136 may include first and second common electrodes 136a and 136b. Here, the first common electrode 136a may be alternately disposed with the first pixel electrode 132a and disposed in a plurality of pixel regions. The second common electrode 136 may electrically connect the first common electrodes 136a to each other, and may be electrically connected to the common wiring 103.

Here, the etching process may be performed by a wet etching process. In this case, the sacrificial light reflection pattern 141 may be formed to have a smaller CD than the photoresist pattern 152 due to the nature of the wet etching process. In addition, after the sacrificial light reflection pattern 141 is formed, an etching process for forming the pixel electrode 132 and the common electrode 136 is performed, so that the pixel electrode 132 and the common electrode 136 are sacrificial light. It may be formed to have a smaller CD than the reflective pattern 141.

In this case, the pixel electrode 132 and the common electrode 136 may be formed to have a line width of 2 μm to 3 μm.

In the exemplary embodiment of the present invention, the pixel electrode 132 and the common electrode 136 are described as being alternately arranged with each other through the same mask process, but embodiments are not limited thereto. For example, any one of the pixel electrode 132 and the common electrode 136 is formed on the gate insulating layer 110 to be disposed in the entire region of the pixel region, and the other electrode is spaced apart on the passivation layer 120. It may be formed to have a plurality. Accordingly, the liquid crystal display device can form a fringe field, thereby further increasing the light transmittance. In this case, when forming a plurality of electrodes having a spaced space in the pixel region, it may be formed through a patterning process using a sacrificial light reflection layer.

Referring to FIG. 8, after forming the common electrode 136 and the pixel electrode 132, the photoresist pattern 152 and the sacrificial light reflection pattern 141 are removed. Here, when the bonding auxiliary layer is formed, the bonding auxiliary layer may also be removed in the process of removing the sacrificial light reflection pattern 141. This is because the bonding auxiliary layer is made of a material that can be etched by the same etchant as the sacrificial light reflection pattern 141.

In the exemplary embodiment of the present invention, the photo process using the sacrificial light reflection layer 140 is performed to form fine line widths of the common electrode 136 and the pixel electrode 132, but the present invention is not limited thereto. . For example, the photo process using the sacrificial light reflection layer 140 is applied to the patterning process for forming the thin film transistor Tr and the wirings, for example, the gate wiring 101, the data wiring 102, and the common wiring 103. The transistor Tr or the wiring may be formed to have a fine line width.

Therefore, as in the embodiment of the present invention, the sacrificial light reflection layer 140 is provided below the photoresist layer 151 in the photo process for forming the common electrode 136 and the pixel electrode 132, compared with the prior art. Thus, fine patterning of the photoresist pattern 152 may be possible. In addition, due to the miniaturization of the photoresist pattern 152, the common electrode 136 and the pixel electrode 132 having a fine line width may be formed. In addition, after etching the sacrificial light reflection layer 140, the common electrode 136 and the pixel electrode 132 are etched so that a CD smaller than the photoresist pattern 152 may be removed than when the sacrificial light reflection layer 140 is not present. The width of the common electrode 136 and the pixel electrode 132 can be further reduced.

As described above, the pixel electrode 132 and the common electrode 136 formed according to the exemplary embodiment of the present invention may have a fine line width, thereby further improving the light transmittance of the liquid crystal display.

9 to 12 are cross-sectional views illustrating a manufacturing process of a liquid crystal display array substrate according to a third embodiment of the present invention.

Here, the same manufacturing process as the second embodiment described above may be included except that the embossing pattern is formed on the sacrificial reflective layer. Accordingly, repeated description with the second embodiment will be omitted.

Referring to FIG. 9, in order to manufacture a liquid crystal display array substrate, first of all, the gate wiring 101, the data wiring 102, the common wiring 103, and the gate wiring 101 and the data wiring on the substrate 100 are formed. The thin film transistor Tr is formed in the intersection area.

Subsequently, a passivation layer 120 including a contact hole exposing the drain electrode 144 of the thin film transistor Tr is formed on the substrate 100 including the thin film transistor Tr.

Thereafter, the conductive layer 130 and the sacrificial light reflection layer 140 are formed on the passivation layer 120. An embossing pattern 145 may be further formed on the sacrificial light reflection layer 140 corresponding to the blocking portion M2 of the mask M to be described later. Here, the embossing pattern 145 may be formed by attaching a film in a patterning process or an embossing form of resin. Another method of forming the embossing pattern 145 may be formed by patterning the surface of the sacrificial light reflection layer 140. In this case, the embossing pattern 145 may be integrally formed with the sacrificial light reflection layer 140.

In the exemplary embodiment of the present invention, the embossing pattern 145 is described as being disposed to correspond to the blocking portion M2 of the mask M, but is not limited thereto. The embossing pattern 145 may be a sacrificial light reflection layer 140. It may be disposed on the front of the).

Referring to FIG. 10, after the embossing pattern 145 is formed, the photoresist layer 151 is formed on the sacrificial light reflection layer 140 including the embossing pattern 145.

Thereafter, a mask M having an opening M1 and a blocking portion M2 is provided on the photoresist layer 151, and then an exposure process is performed. In the exposure process, the light passing through the opening M1 of the mask M is reflected by the sacrificial reflective layer 140 so that the light is diffused into the photoresist layer 151 corresponding to the blocking portion M2 of the mask M. Can be. In this case, the reflected light may be diffused more uniformly to the region corresponding to the blocking portion M2 of the mask M by the embossing pattern 145.

Referring to FIG. 11, an exposure process is performed on the photoresist layer 151, and a photoresist pattern 152 is formed by performing a developing process on the exposed photoresist layer 151.

Thereafter, the sacrificial light reflection layer 140 is etched using the photoresist pattern 152 as an etching mask to form the sacrificial light reflection pattern 141. Here, the etching process for forming the sacrificial light reflection pattern 141 may be a wet etching process.

Thereafter, the conductive layer 130 is etched using the photoresist pattern 152 or the sacrificial light reflection pattern 141 as an etching mask, and the pixel electrode 132 including the first and second pixel electrodes 132a and 132b and The common electrode 136 including the first and second common electrodes 136a and 136b may be formed.

Referring to FIG. 12, after the common electrode 136 and the pixel electrode 132 are formed, the photoresist pattern 152 and the embossing pattern 145 disposed on the common electrode 136 and the pixel electrode 132 are formed. The sacrificial light reflection pattern 141 is removed.

As in the embodiment of the present invention, as the sacrificial light reflection layer 140 is provided with an embossing pattern 145 capable of uniformly diffusing light into the photoresist layer corresponding to the blocking portion of the mask, a finer photoresist pattern ( 152 may be formed. Accordingly, the pixel electrode 132 and the common electrode 136 having finer line widths can be formed.

13 is a photograph showing a side of a photoresist pattern according to a comparative example.

14 and 15 are photographs showing the side surfaces of the photoresist patterns according to Experimental Examples 1 and 2. FIG.

Here, the photoresist pattern PR according to the comparative example may be formed by sequentially forming an ITO layer and a photoresist layer on a substrate, and then performing an exposure process and a developing process on the photoresist layer. At this time, novolak-type resin was used for the photoresist layer. In addition, the exposure process used the mask which has an opening of a 4 micrometer line width.

Thereafter, the ITO layer was patterned by using the photoresist pattern PR as an etching mask.

In Experimental Example 1, a photoresist pattern PR was formed through the same process as in Comparative Example except that a sacrificial light reflection layer was formed between the ITO layer and the photoresist layer. Here, the sacrificial light reflection layer formed AlNd at a thickness of 500 kPa.

In Experimental Example 2, the photoresist pattern PR was formed through the same process as in Experimental Example 1, except that the sacrificial light reflection layer was formed to have a thickness of 1000 GPa with AlNd.

As shown in FIG. 13, the CD of the photoresist pattern PR according to the comparative example was 4 μm. Moreover, CD of ITO pattern was 3.6 micrometers. On the other hand, as shown in FIG. 14, the CD of the photoresist pattern PR according to Example 1 was 3.3 μm, and as shown in FIG. 15, the CD of the photoresist pattern PR according to Example 2 was 3.4 μm.

Accordingly, it was confirmed that when the sacrificial light reflection layer was provided under the photoresist layer, the photoresist pattern PR having a fine line width could be formed. In addition, it was confirmed that the thickness of the sacrificial light reflection layer did not significantly affect the CD of the photoresist pattern PR.

16 is a photograph showing the side surface of the photoresist pattern, Mo pattern, AlNd and ITO pattern according to Experimental Example 3.

Here, in Experimental Example 3, an ITO layer, a bonding auxiliary layer, a sacrificial light reflection layer, and a photoresist layer were sequentially formed on the photoresist pattern PR and the ITO pattern substrate, and then an exposure process and a developing process on the photoresist layer. Was performed to form the photoresist pattern PR. At this time, the bonding auxiliary layer was formed to a thickness of 100 kPa. In addition, the sacrificial light reflection layer formed AlNd at a thickness of 500 kPa. In addition, novolak-type resin was used for the photoresist layer. In addition, the exposure process used the mask which has an opening of a 4 micrometer line width.

Thereafter, the ITO layer, the sacrificial light reflection layer, and the photoresist layer were wet etched using the photoresist pattern PR as an etching mask to form an ITO pattern and a sacrificial light reflection pattern.

As shown in FIG. 16, when the bonding auxiliary layer was further provided, a photoresist pattern having a CD of 3.6 μm could be formed. Accordingly, even if the bonding auxiliary layer is further provided, there is an effect of reducing the CD of the photoresist pattern.

In addition, the CD of the sacrificial light reflection pattern, i.e., AlNd, was 3 mu m, and the CD of the ITO pattern was 2.6 mu m. Accordingly, it was confirmed that an ITO pattern having a line width of 3 μm or less was formed through a photo process and a patterning process using a sacrificial light reflection layer.

101: gate wiring 102: data wiring
103: common wiring 110: gate insulating film
120: protective film 132: pixel electrode
136: common electrode 140: sacrificial light reflection layer
141: sacrificial light reflection pattern 145: embossed pattern
Tr: thin film transistor

Claims

In the method of manufacturing a liquid crystal display device array substrate having a plurality of electrodes having a predetermined interval and each pixel on a substrate having a plurality of pixels,
The step of forming the electrode
Forming a conductive layer on the substrate;
Forming a sacrificial light reflection layer on the conductive layer;
Forming a photoresist layer on the sacrificial light reflection layer;
Forming a photoresist pattern by performing an exposure and development process using a mask on the photoresist layer;
Patterning a sacrificial light reflection layer and a conductive layer using the photoresist pattern as an etching mask; And
Removing the photoresist pattern and the sacrificial light reflection layer;
Method of manufacturing a liquid crystal display array substrate comprising a.

The method of claim 1,
Between forming a conductive layer on the substrate and forming a sacrificial light reflection layer on the conductive layer,
And forming a bonding auxiliary layer between the conductive layer and the sacrificial light reflection layer.

The method of claim 2,
And the bonding auxiliary layer is formed of a material etched by the same etchant as the sacrificial light reflection layer.

The method of claim 2,
And wherein the bonding auxiliary layer is formed of Mo.

The method of claim 2,
The bonding auxiliary layer is a liquid crystal display device array substrate manufacturing method of forming a thickness in the range of 50Å to 100Å.

The method of claim 1,
And the sacrificial reflective layer is formed of any one of Al, AlNd, and AlPaCu.

The method of claim 1,
The conductive film is a single layer formed of any one of ITO, IZO and MoTi or a method of manufacturing a liquid crystal display array substrate formed of two or more laminates.

The method of claim 1,
The electrode is a method of manufacturing a liquid crystal display device array substrate having a line width of 2㎛ 3㎛.

The method of claim 1,
And the electrode is at least one of a pixel electrode and a common electrode.

The method of claim 1,
And an embossing pattern on the sacrificial light reflection layer.

11. The method of claim 10,
And the embossing pattern is formed on the sacrificial light reflection layer corresponding to the opening of the mask.