KR20120129154A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20120129154A
KR20120129154A KR1020110047249A KR20110047249A KR20120129154A KR 20120129154 A KR20120129154 A KR 20120129154A KR 1020110047249 A KR1020110047249 A KR 1020110047249A KR 20110047249 A KR20110047249 A KR 20110047249A KR 20120129154 A KR20120129154 A KR 20120129154A
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KR
South Korea
Prior art keywords
vernier
forming
hard mask
region
thickness
Prior art date
Application number
KR1020110047249A
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Korean (ko)
Inventor
박사로한
이기령
이상오
황승현
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020110047249A priority Critical patent/KR20120129154A/en
Publication of KR20120129154A publication Critical patent/KR20120129154A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

A method of manufacturing a semiconductor device is provided. A method of manufacturing a semiconductor device according to an embodiment of the present invention includes providing a substrate having an overlay vernier region; Forming a vernier in the overlay vernier region on the substrate; Forming a second interlayer insulating film on the substrate on which the vernier is formed; A first hard mask having a third thickness in a region where a vernier not overlapped with the vernier is formed on the second interlayer insulating layer, and a second thickness that is thinner than the third thickness in a region where the vernier is formed. Forming; Forming a mask pattern for forming the vernier on the first hard mask; Etching the first hard mask and the second interlayer insulating layer using the mask pattern as an etch barrier to form trenches for verniers; And forming the vernier in the trench for the vernier.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having an overlay vernier used to reduce pattern alignment errors.

In general, semiconductor devices have various layers that are stacked vertically. In this case, it is very important to remove alignment errors from the lowermost semiconductor substrate to the uppermost layer, for which an overlay vernier is formed. The overlay vernier is formed around the chip of the semiconductor wafer and is typically formed in the scribe lane area.

The overlay vernier is composed of a vernier formed in the lower portion and a vernier formed in the upper portion, and indirectly measures the alignment error between the patterns by measuring the positional information on which the vernier and the vernier overlapped during the manufacturing process of the semiconductor device.

1A to 1D are views for explaining a method of forming an overlay vernier according to the prior art and its problems.

Referring to FIG. 1A, a second interlayer insulating layer 120 is formed on a first interlayer insulating layer 110 having a vernier 111 formed in an overlay vernier region A and a storage node contact 113 formed in a cell region B. ). Subsequently, the polysilicon layer 130 for hard mask for lower layer patterning is formed on the second interlayer insulating layer 120.

In this case, since the polysilicon layer 130 for the hard mask is an opaque material, the parent Vernier 111 is not visible, and thus the polymask for the hard mask Polysilicon formed in the overlay vernier region A in order to read the Mornier 111. A key open process for removing the film 130 is performed.

Referring to FIG. 1B, an amorphous carbon hard mask layer 141 and a silicon oxynitride (SiON) layer 142 are formed on the polymask 130 for the hard mask and the second interlayer insulating layer 120. .

Subsequently, a mask pattern 150 is formed on the silicon oxynitride layer 142 using a photoresist layer to form trenches for vernier and trenches for storage nodes. Javernier and storage nodes will be formed in trenches for javernier and trenches for storage nodes, respectively.

 Referring to FIG. 1C, the silicon nitride oxide layer 142, the amorphous carbon hard mask layer 141, the hard silicon polysilicon layer 130, and the second interlayer insulating layer 120 are etched using the mask pattern 150 as an etching mask. do.

However, in this process, when etching based on the cell region B having a high pattern density due to the loading effect caused by the difference in the pattern density of the overlay vernier region A and the cell region B, the pattern density The second interlayer insulating film 120 in the low overlay vernier region A is excessively etched, and the trenches for the vernier are not formed properly.

Therefore, since it is impossible to form a vernier, overlay vernier reading for measuring alignment error cannot be performed normally, so that the yield of formation of a semiconductor device is reduced and the risk of defects is increased.

Referring to FIG. 1D, a conductive film is formed along the entire surface of the result of the etching process, and the storage node 160B is formed by removing the conductive film formed on the second interlayer insulating layer 120. At this time, the conductive film D remains on the side surface of the second interlayer insulating film 120 of the overly etched overlay vernier region A (see dotted line).

Subsequently, although not shown, the second interlayer insulating layer 120 is removed in a subsequent dip out process to expose the outer wall of the storage node 160B. However, in this process, a lifting phenomenon in which the conductive film D remaining on the side surface of the second interlayer insulating film 120 of the overlay vernier region A is pulled out occurs and a defect occurs on the entire surface of the wafer during the subsequent process. Acts as.

The problem to be solved by the present invention is to prevent the problem that the pattern of the overlay vernier region is not formed properly according to the loading effect due to the difference in the pattern density of the cell region and the overlay vernier region during the overlay vernier forming process. It is to provide a method for manufacturing a semiconductor device.

According to one or more exemplary embodiments, a method of manufacturing a semiconductor device includes: providing a substrate having an overlay vernier region; Forming a vernier in the overlay vernier region on the substrate; Forming a second interlayer insulating film on the substrate on which the vernier is formed; A first hard mask having a third thickness in a region where a vernier not overlapped with the vernier is formed on the second interlayer insulating layer, and a second thickness that is thinner than the third thickness in a region where the vernier is formed. Forming; Forming a mask pattern for forming the vernier on the first hard mask; Etching the first hard mask and the second interlayer insulating layer using the mask pattern as an etch barrier to form trenches for verniers; And forming the vernier in the trench for the vernier.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: providing a substrate having an overlay vernier region and a cell region; Forming a vernier in the overlay vernier region on the substrate and forming a storage node contact in the cell region; Forming a second interlayer insulating film on the substrate on which the vernier and storage node contacts are formed; A third thickness in the cell region and a region where a vernier is not formed that overlaps with the vernier on the second interlayer insulating layer, and a second thickness that is thinner than the third thickness in the region where the vernier is formed 1 forming a hard mask; Forming a mask pattern for forming the vernier and storage nodes on the first hard mask; Etching the first hard mask and the second interlayer insulating layer using the mask pattern as an etch barrier to form a trench for a storage node exposing a vernier trench and the storage node contact; And forming the vernier in the trench for the vernier, and forming the storage node in the trench for the storage node.

According to the method of manufacturing a semiconductor device of the present invention, it is possible to provide a method of manufacturing a semiconductor device, in which a pattern of an overlay vernier region is properly formed to increase yield and prevent occurrence of defects.

1A to 1D are views for explaining a method of forming an overlay vernier according to the prior art and its problems.
2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
4 is a plan view showing a vernier and a vernier formed in the overlay vernier region using the method of manufacturing a semiconductor device of the present invention.

Hereinafter, the most preferred embodiment of the present invention will be described. In the drawings, the thickness and spacing are expressed for convenience of description and may be exaggerated compared to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. It should be noted that, in the case of adding the reference numerals to the constituent elements of the drawings, the same constituent elements have the same number as much as possible even if they are displayed on different drawings.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 2A, a first interlayer insulating layer 210 having a vernier 211 and a storage node contact 213 is formed on a substrate (not shown) having an overlay vernier region A and a cell region B. Form.

Specifically, after the conductive film (not shown) is formed on the substrate (not shown), the conductive film is selectively etched to form the vernier 211 in the overlay vernier region A, and the cell region B The storage node contact 213 is formed in the contact hole 213. Subsequently, after forming the first interlayer insulating layer 210, for example, an oxide layer covering the moverier 211 and the storage node contact 213, a planarization process is performed to expose the moverier 211 and the storage node contact 213. .

Subsequently, a second interlayer insulating film 220, for example, an oxide film is formed on the first interlayer insulating film 210 having the vernier 211 and the storage node contact 213, and the first interlayer insulating film 220 is formed on the first interlayer insulating film 220. A first material film 231 for a hard mask having a thickness T1, for example, polysilicon is formed.

Referring to FIG. 2B, the hard mask first material layer 231 of the overlay vernier region A in which the vernier 211 is formed is selectively removed. As a result, the first material film 231 for the hard mask does not exist on the second interlayer insulating film 220 in the region where the vernier 211 is formed.

Referring to FIG. 2C, a second material layer 232 for hard mask having a second thickness T2 is formed along the entire surface of the resultant material in which the first material layer 231 for hard mask is selectively removed.

The structure in which the hard mask second material layer 232 is stacked on the hard mask first material layer 231 is called a first hard mask 230.

 As a result, the first hard mask 230 has a third thickness T1 + T2 in which the first thickness T1 and the second thickness T2 are added in the region where the vernier is to be formed and the cell region B. In the region where the vernier 211 is formed, it has a second thickness T2. That is, the thickness of the first hard mask 230 in the region where the vernier is to be formed and the cell region B is greater than the thickness in the region where the vernier 211 is formed. As such, since the thickness of the first hard mask 230 of the region where the vernier is to be formed is as thick as the thickness of the first hard mask 230 of the cell region B, the trench formation process for the vernier described later may be easily performed. have.

On the other hand, the second thickness T2 of the first hard mask 230 may be a thickness having a transmittance such that the vernier 211 formed in the overlay vernier region A is visible. Materials such as polysilicon used as hard masks generally have a lower transmittance as the thickness increases. Therefore, overlay vernier reading for eliminating alignment error of the semiconductor device is possible only when the first hard mask 230 has a thickness enough to show the transversal 211 on the substrate. This can be achieved.

Referring to FIG. 2D, a second hard mask 241 and a third hard mask 242 are formed on the first hard mask 230. Subsequently, a mask pattern 250 is formed on the third hard mask 242 to form the trenches for the vernier and the trenches for the storage node.

The second hard mask 241 and the third hard mask 242 may each include an amorphous carbon film, a spin on carbon (SOC) film, or a silicon oxynitride (SiON) film. However, the present invention is not limited thereto.

As described above, by forming a plurality of hard masks on the first hard mask 230, more precise patterning is possible than when a single layer hard mask is formed. However, this is only an exemplary embodiment, and one or more hard masks may be stacked on the first hard mask 230 or may not be stacked.

Referring to FIG. 2E, the third hard mask 242, the second hard mask 241, the first hard mask 230, and the second interlayer insulating layer 220 are etched using the mask pattern 250 as an etch barrier. The vernier trench 251 is formed in the vernier region A, and the storage node trench 252 is formed in the cell region B to expose the storage node contact 213. At this time, the vernier trench 251 is formed in the overlay vernier region A so as not to overlap with the vernier 211.

Referring to FIG. 2F, a conductive layer 260 is formed along the upper portion of the second interlayer insulating layer 220, the trench 251 for the vernier, and the trench 252 for the storage node.

Referring to FIG. 2G, the conductive layer 260 formed on the second interlayer insulating layer 220 is removed.

In this case, the conductive layer 260 may be removed through a planarization process such as an etch back process or a chemical mechanical polishing (CMP) process so that the upper portion of the second interlayer insulating layer 220 is exposed. It is not.

As a result, the javernier 260A is formed in the trench for vernier 251, and the storage node 260B is formed in the trench 252 for the storage node, which contacts the storage node contact 213.

Subsequently, although not shown in the figure, the second interlayer insulating film 220 is removed by performing a dip out process. As described above, since the vernier 260A is normally formed, the vernier 260A remains on the side of the second interlayer insulation layer 120 of the overlay vernier region A when the second interlayer insulation layer (see 120 of FIG. 1D), which is a problem in the prior art, is removed. There is no room for a lifting phenomenon in which the conductive film (see D in FIG. 1D) falls off and a problem of acting as a defect on the wafer.

3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention. Hereinafter, only differences between the first embodiment and the second embodiment will be described.

Referring to FIG. 3, instead of the second interlayer insulating layer 220 of FIG. 2G, a structure in which the third interlayer insulating layer 321, the support layer 322, and the fourth interlayer insulating layer 323 are sequentially stacked is used. In this case, the third interlayer insulating film 321 and the fourth interlayer insulating film 323 may include an oxide film, and the support film 322 may include a nitride film.

In this case, only the third interlayer insulating layer 321 and the fourth interlayer insulating layer 323 are removed except the support layer 322 by performing a dip out process. For example, only the oxide film can be removed while leaving the nitride film.

The supporting film formed by the present process may prevent the vernier and storage nodes from falling down during the dip out process.

4 is a plan view showing a vernier and a vernier formed in the overlay vernier region using the method of manufacturing a semiconductor device of the present invention.

Referring to FIG. 4, the mother vernier 411 may be formed, for example, in a frame shape, and the mother vernier 480 is surrounded by the mother vernier 411.

Reference numeral 490 denotes the shape of the first material layer 231 for the hard mask in which the region where the vernier 211 is formed in the overlay vernier region A is selectively removed. Since the vernier 480 is formed in the region indicated by the reference numeral 490, the vernier 480 and the vernier 411 may be formed so as not to overlap.

FIG. 4 is an example for showing the shapes of the vernier and javernier, and it should be noted that the present invention is not necessarily limited to the form shown in FIG. 4.

A: overlay vernier area B: cell area
210: first interlayer insulating film 211: vernier
213: storage node contact 220: second interlayer insulating film
230: first hard mask 231: first material film for hard mask 232: second material film for hard mask
T1: first thickness T2: second thickness

Claims (12)

Providing a substrate having an overlay vernier region;
Forming a vernier in the overlay vernier region on the substrate;
Forming a second interlayer insulating film on the substrate on which the vernier is formed;
A first hard mask having a third thickness in a region where a vernier not overlapped with the vernier is formed on the second interlayer insulating layer, and a second thickness that is thinner than the third thickness in a region where the vernier is formed. Forming;
Forming a mask pattern for forming the vernier on the first hard mask;
Etching the first hard mask and the second interlayer insulating layer using the mask pattern as an etch barrier to form trenches for verniers; And
Forming the vernier in the trench for the vernier
The manufacturing method of a semiconductor device.
The method of claim 1,
Forming the first hard mask is
Forming a first material film for a hard mask having a first thickness on the second interlayer insulating film;
Selectively removing the first material film for the hard mask in the region where the vernier is formed; And
Forming a second material film for the hard mask having the second thickness along the entire surface of the selectively removed resultant;
The manufacturing method of a semiconductor device.
The method according to claim 1 or 2,
The second thickness of the first hard mask is
The thickness of the transmittance is such that the vernier
The manufacturing method of a semiconductor device.
The method of claim 1,
After forming the first hard mask.
The method may further include forming at least one hard mask on the first hard mask.
The manufacturing method of a semiconductor device.
The method of claim 1,
The vernier is formed to surround the vernier
The manufacturing method of a semiconductor device.
The method of claim 1,
Forming the zavernier,
Forming a conductive film in the trench for javernier; And
Removing the conductive film formed on the second interlayer insulating film;
The manufacturing method of a semiconductor device.
Providing a substrate having an overlay vernier region and a cell region;
Forming a vernier in the overlay vernier region on the substrate and forming a storage node contact in the cell region;
Forming a second interlayer insulating film on the substrate on which the vernier and storage node contacts are formed;
A third thickness in the cell region and a region where a vernier is not overlapped with the vernier on the second interlayer insulating layer, and a second thickness that is thinner than the third thickness in the region where the vernier is formed 1 forming a hard mask;
Forming a mask pattern for forming the vernier and storage nodes on the first hard mask;
Etching the first hard mask and the second interlayer insulating layer using the mask pattern as an etch barrier to form a trench for a storage node exposing a vernier trench and the storage node contact; And
Forming the vernier in the trench for the vernier, and forming the storage node in the trench for the storage node;
The manufacturing method of a semiconductor device.
The method of claim 7, wherein
Forming the first hard mask,
Forming a first material film for a hard mask having a first thickness on the second interlayer insulating film;
Selectively removing the first material film for the hard mask in the region where the vernier is formed; And
Forming a second material film for the hard mask having the second thickness along the entire surface of the selectively removed resultant;
The manufacturing method of a semiconductor device. 9. The method according to claim 7 or 8,
The second thickness of the first hard mask is
The thickness of the transmittance is such that the vernier
The manufacturing method of a semiconductor device.
The method of claim 7, wherein
After forming the first hard mask.
The method may further include forming at least one hard mask on the first hard mask.
The manufacturing method of a semiconductor device.
The method of claim 7, wherein
The vernier is formed to surround the vernier
The manufacturing method of a semiconductor device.
The method of claim 7, wherein
Forming the zavernier and the storage node,
Forming a conductive film in the trench for the vernier and the trench for the storage node;
Removing the conductive film formed on the second interlayer insulating film;
The manufacturing method of a semiconductor device.
KR1020110047249A 2011-05-19 2011-05-19 Method for manufacturing semiconductor device KR20120129154A (en)

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KR1020110047249A KR20120129154A (en) 2011-05-19 2011-05-19 Method for manufacturing semiconductor device

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