KR20120123984A - Semiconductor memory device and method of forming the same - Google Patents

Abstract

PURPOSE: A semiconductor memory device and a manufacturing method thereof are provided to improve electrical characteristics of a semiconductor device by forming the size of crystal grain of channel regions which is adjacent to a gate pattern on a large scale. CONSTITUTION: A laminate structure comprises a gate pattern and a selection gate pattern. The gate pattern comprises a bottom selection pattern, cell gate patterns, and a top gate pattern. A semiconductor patter passes through the laminate structure and is electrically connected to a substrate. A channel structure comprises a first region(P1) having a first semiconductor layer and a second region(P2) having a second semiconductor layer(133). The channel structure additionally comprises a padding pattern(156) which is surrounded by the first area.

Description

Semiconductor memory device and manufacturing method thereof

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor memory device and a method for manufacturing the same.

As the electronic industry develops rapidly, the degree of integration of semiconductor memory devices is increasing. The integration of semiconductor memory devices is an important factor in determining the price of a product. In other words, as the degree of integration increases, the product price of the semiconductor memory device may decrease. Accordingly, there is a growing demand for improving the degree of integration of semiconductor memory devices. In general, the degree of integration of a semiconductor memory device is mainly determined by the planar area occupied by a unit memory cell, and thus is greatly influenced by the level of fine pattern formation technology. However, the miniaturization of patterns is approaching the limit due to the high cost of equipment and the difficulty of the semiconductor manufacturing process.

In order to overcome this limitation, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. However, for mass production of 3D semiconductor memory devices, a process technology capable of realizing reliable product characteristics while reducing manufacturing cost per bit than that of 2D semiconductor memory devices is required.

One object of the present invention is to provide a semiconductor memory device having improved electrical characteristics and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor memory device optimized for high integration and a method of manufacturing the same.

Provided is a semiconductor device for achieving the above technical problem. The device may include a stack structure including cell gate patterns and a selection gate pattern on the cell gate patterns, and a semiconductor pattern penetrating the stack structure and electrically connected to the substrate, wherein the semiconductor pattern may include the cell gate. And a first semiconductor region, which is an active region of the patterns, and a second semiconductor region, which is an active region of the selection gate pattern, wherein a grain size of the second semiconductor region is larger than a grain size of the first semiconductor region.

In example embodiments, the grains of the second semiconductor region may have a greater length in a direction perpendicular to the substrate than a width in a direction parallel to the surface of the substrate.

The buried pattern may further include a buried pattern surrounded by the first semiconductor region, and an upper surface of the buried pattern may be provided between an uppermost layer of the cell gate patterns and the selection gate pattern.

The buried pattern may further include a buried pattern surrounded by the first semiconductor region and the second semiconductor region, and an upper surface of the buried pattern may be higher than an upper surface of the selection gate pattern.

There is provided a method of manufacturing a semiconductor device for achieving the above technical problem. The method includes repeatedly stacking first and second material films on a substrate, patterning the first and second material films to form a first through region that exposes the substrate, the first through Forming a first semiconductor layer and a buried film in a region in turn, etching a portion of the first semiconductor layer to form a second through region, and forming a second semiconductor layer in the second through region, The second semiconductor layer may be formed by an epitaxial process of seeding the first semiconductor layer exposed by the second through region.

In example embodiments, the forming of the second through region may further include etching an upper portion of the buried film, and an upper surface of the etched buried film may be higher than an upper surface of the etched first semiconductor layer.

The method may further include replacing the second material layer with gate electrodes, wherein the gate electrodes include cell gate patterns and a selection gate pattern on the cell gate patterns. An etching process may be performed at a depth between an uppermost layer of the cell gate patterns and the selection gate pattern.

In example embodiments, the forming of the second through region may further include etching an upper portion of the buried film, and an upper surface of the etched buried film may be lower than a lower surface of the selection gate pattern.

In example embodiments, the forming of the second through region may further include etching an upper portion of the buried layer, and the etching process of the buried layer may be performed at a depth higher than an upper surface of the selection gate pattern.

According to an embodiment of the present invention, a channel pattern having different structures of channel regions adjacent to the cell gate pattern and the selection gate pattern may be provided. It is possible to improve the electrical characteristics of the semiconductor device by forming a relatively large grain size of channel regions adjacent to the selection gate pattern.

1 is a circuit diagram of a semiconductor device in accordance with embodiments of the present invention.
2 is a perspective view of a semiconductor device according to a first exemplary embodiment of the present invention.
3 is an enlarged view of the channel structure of FIG. 2.
4 to 14 are cross-sectional views and top views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
15 is a perspective view of a semiconductor device according to a second exemplary embodiment of the present invention.
FIG. 16 is an enlarged view of the channel structure of FIG. 15.
17 to 24 are cross-sectional views and a top view illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
25 and 26 are perspective views illustrating a structure of an information storage film according to embodiments of the present invention.
27 is a schematic block diagram illustrating an example of a memory system including a semiconductor device formed according to example embodiments.
28 is a schematic block diagram illustrating an example of a memory card including a semiconductor device according to example embodiments.
29 is a schematic block diagram illustrating an example of an information processing system including a semiconductor device according to example embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the present specification, when it is mentioned that a layer is on another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. The size and thickness of the components are exaggerated for clarity. In addition, although the terms first, second, third, etc. are used to describe various regions, layers, etc. in various embodiments of the present specification, these regions, films should not be limited by these terms. . These terms are only used to distinguish any given region or layer from other regions or layers. Therefore, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in other embodiments. Each embodiment described and illustrated herein also includes its complementary embodiment. The expression 'and / or' is used herein to include at least one of the components listed before and after. Portions denoted by like reference numerals denote like elements throughout the specification.

1 is a circuit diagram of a semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 1, a semiconductor memory device according to example embodiments may include a common source line CSL, a plurality of bit lines BL0-BL3, and a common source line CSL and the bit lines BL0. A plurality of cell strings CSTR disposed between -BL3 may be included.

The common source line CSL may be a conductive thin film disposed on a semiconductor substrate or an impurity region formed in the substrate. The bit lines BL0-BL3 may be conductive patterns spaced apart from the semiconductor substrate. The bit lines BL0-BL3 are two-dimensionally arranged, and a plurality of cell strings CSTR are connected to each other in parallel. Accordingly, the cell strings CSTR are two-dimensionally arranged on the common source line CSL or the substrate.

Each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit lines BL0-BL3, and the ground and string select transistor. And a plurality of memory cell transistors MCT disposed between the gates GST and SST. The ground select transistor GST, the string select transistor SST and the memory cell transistors MCT may be connected in series. In addition, the ground select line GSL, the plurality of word lines WL0-WL3, and the string select lines SSL0- disposed between the common source line CSL and the bit lines BL0-BL3. SSL2 may be used as gate electrodes of the ground select transistor GST, the memory cell transistors MCT, and the string select transistors SST, respectively.

The ground select transistors GST may be disposed at substantially the same distance from the substrate, and their gate electrodes may be commonly connected to the ground select line GSL to be in an equipotential state. For this purpose, the ground select line GSL may be a plate-shaped or comb-shaped conductive pattern disposed between the common source line CSL and the memory cell transistor MCT adjacent to the common source line CSL. have. Similarly, gate electrodes of the memory cell transistors MCT, which are disposed at substantially the same distance from the common source line CSL, are also commonly connected to one of the word lines WL0-WL3 to have an equipotential state. Can be in. For this purpose, each of the word lines WL0-WL3 may be a flat or comb-shaped conductive pattern parallel to the upper surface of the substrate. Meanwhile, since one cell string CSTR is configured of a plurality of memory cell transistors MCT having different distances from the common source line CSL, the common source line CSL and the bit lines ( Multi-layered word lines WL0-WL3 are disposed between BL0-BL3.

Each of the cell strings CSTR may include a channel structure extending vertically from the common source line CSL and connected to the bit lines BL0-BL3. The channel structure may include a semiconductor layer. The semiconductor layer may be formed to pass through the ground select line GSL and the word lines WL0-WL3. In addition, the semiconductor layer may include a body portion and impurity regions formed at one end or both ends of the body portion. For example, a drain region may be formed on top of the semiconductor layer.

An information storage layer may be disposed between the word lines WL0-WL3 and the semiconductor layer. According to an embodiment, the information storage layer may be a charge storage layer. For example, the information storage film may be one of an insulating film including a trap insulating film, a floating gate electrode, or conductive nano dots.

A dielectric layer used as the gate insulating layer of the ground select transistor GST or the string select transistor SST between the ground select line GSL and the semiconductor layer or between the string select lines SSL0-SSL2 and the semiconductor layer. This can be arranged. At least one gate insulating layer of the ground and string selection transistors GST and SST may be formed of the same material as the information storage layer of the memory cell transistor MCT, but may also be a gate insulating layer for a conventional MOSFET. have.

The ground and string select transistors GST and SST and the memory cell transistors MCT may be MOS field effect transistors using a semiconductor layer as a channel region. In example embodiments, the semiconductor layer may form a MOS capacitor together with the ground select line GSL, the word lines WL0-WL3, and the string select lines SSL0-SSL2. Can be. In this case, the ground select transistor GST, the memory cell transistors MCT, and the string select transistor SST are the ground select line GSL, the word lines WL0-WL3, and the string select line. Can be electrically connected by sharing inversion layers formed by fringe fields from SSL0-SSL2.

2 and 3, a semiconductor device according to a first embodiment of the present invention is described. 2 is a perspective view of a semiconductor device according to a first exemplary embodiment of the present invention, and FIG. 3 is an enlarged view of the channel structure of FIG. 2.

2 and 3, a laminate structure is provided on a substrate 100. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may be of a first conductivity type. For example, the first conductivity type may be p-type. The stack structure may include gate patterns and insulating patterns repeatedly stacked alternately on the substrate 100. The gate patterns may include a lower select gate pattern 157L, cell gate patterns 157m and 157, and an upper select gate pattern 157U. The cell gate patterns may include an uppermost cell gate pattern 157m and cell gate patterns 157 thereunder. A buffer insulating layer 105 may be provided between the substrate 100 and the lower selection gate pattern 157L. The buffer insulating layer 105 may be a silicon oxide layer. For example, the lower and upper selection gate patterns 157L and 157U may be formed thicker than the cell gate patterns 157m and 157. Alternatively, the lower and upper selection gate patterns 157L and 157U may be formed to have substantially the same thickness as the cell gate patterns 157m and 157.

The insulating patterns may include an uppermost insulating pattern 120Ua, a lowermost insulating pattern 120La, and intermediate insulating patterns 120a between the uppermost insulating pattern 120Ua and the lowermost insulating pattern 120La. The gate patterns 157U, 157m, 157, and 157L and the insulating patterns 120Ua, 120a, and 120La may extend in a horizontal direction, for example, a y direction. Only six of the gate patterns 157U, 157m, 157, and 157L and the insulating patterns 120Ua, 120a, and 120La are shown, but these are omitted for simplicity. In addition, although the lower and upper selection gate patterns 157L and 157U are illustrated one by one, each of the lower and upper selection gate patterns 157L and 157U may be formed of two or more gate patterns.

The gate patterns 157U, 157m, 157, and 157L may include at least one selected from a metal, a metal silicide, a conductive metal nitride, and a doped semiconductor material. The insulating patterns 120Ua, 120a, and 120La may be provided in spaced spaces between the gate patterns 157U, 157m, 157, and 157L. For example, the insulating patterns 120Ua, 120a, and 120La may be oxide layers or oxynitride layers.

Channel structures 139 may extend from the substrate 100 and pass through the gate patterns 157U, 157m, 157, and 157L and the insulating patterns 120Ua, 120a, and 120La. The channel structures 139 may be provided in the first through regions 125 passing through the gate patterns 157U, 157m, 157, and 157L and the insulating patterns 120Ua, 120a, and 120La.

The channel structures 139 may include a first region P1 including a first semiconductor layer 132 and a second region P2 including a second semiconductor layer 133. The first region may be an active region of the cell gate patterns 157m and 157 and the lower selection gate pattern 157L, and the second region P2 may be the upper selection gate pattern 157U. It may be an active region of. The second region P2 may be provided on the first region P1. A boundary between the first region P1 and the second region P2 may be provided between the upper selection gate pattern 157U and the uppermost cell gate pattern 157m. The second region P2 may be adjacent to the upper selection gate pattern 157U, and the first region P1 may be adjacent to the cell gate patterns 157m and 157. That is, when the upper select gate pattern 157U is a gate electrode of the string select transistor, a part of the second region P2 may be a channel region of the string select transistor. When the cell gate patterns 157m and 157 are gate electrodes of memory cell transistors, a portion of the first region P1 may be a channel region of the memory cell transistors.

The grain size of the second region P2 may be larger than the grain size of the first region P1. For example, the grains of the second region P2 may have a length in a direction perpendicular to the substrate 100 (z direction) than a width in a direction parallel to the surface of the substrate 100 (x direction and y direction). Can be larger. For example, an aspect ratio of grains in the second region P2 may be about 2 to about 100. For example, the length of the crystal grains in the second direction P2 in the z direction may be greater than the thickness of the upper selection gate pattern 157U. That is, the string select transistor may have a channel region having a larger grain size than the memory cell transistors. Therefore, the area of grain boundaries in the channel region of the string select transistor can be reduced. Thereby, it is possible to improve the electrical characteristics of the semiconductor element such as leakage current which may be generated by the grain boundary.

The channel structures 139 may further include a buried pattern 156 surrounded by the first region P1. For example, a macaroni filled with the buried pattern 156 may be formed in the lower portion of the channel structures 139 in the semiconductor pattern 136 formed along the lower surface and the inner wall of the first through regions 125. It may be in the form or a shell (shell). The buried pattern 156 may be spaced apart from the substrate 100 by the semiconductor pattern 136. Alternatively, the upper portion of the channel structures 139 may not include the buried pattern 156. For example, the upper portions of the channel structures 139 may be regions in which the semi-green pattern 136 is completely filled in the first through regions 125. Accordingly, the string select transistor can secure a relatively wide channel region compared to the memory cell transistors.

An upper surface of the buried pattern 156 may be provided between the upper selection gate pattern 157U and the uppermost cell gate pattern 157m. For example, the buried pattern 156 may include at least one of a silicon oxide layer and a silicon oxynitride layer. The semiconductor pattern 136 may include at least one of silicon of a first conductivity type, an intrinsic state, or silicon-germanium.

The channel structures 139 arranged in the x direction form one row, and the channel structures 139 arranged in the y-axis direction form one column. A plurality of rows and a plurality of columns may be arranged on the substrate 100. An isolation pattern 175 may be disposed between the adjacent pair of columns. That is, the device isolation pattern 175 may extend in the y direction. The device isolation pattern 175 may include an insulating material. For example, the device isolation pattern 175 may be formed of a high density plasma oxide film, a spin on glass layer, and / or a CVD oxide film. The first impurity region 170 may be formed in the substrate 100 under the device isolation pattern 175. For example, the first impurity region 170 may have a line shape extending in the y direction. The first impurity region 170 may be a region doped with impurities of a second conductivity type. The second conductivity type may be a different conductivity type than the first conductivity type. An information storage layer 150 may be provided between the gate patterns 157U, 157m, 157, and 157L and the channel structures 139. The structure of the information storage film 150 will be described in more detail below with reference to FIGS. 25 and 26.

The second impurity region 198 may be provided on the semiconductor pattern 136 adjacent to the uppermost insulating pattern 120Ua. The second impurity region 198 may be an impurity region of the same conductivity type as the first impurity region 170. Bit lines BL extending in a direction crossing the gate patterns 157U, 157m, 157, and 157L (for example, x directions) and electrically connected to the second impurity region 198 are provided. . The bit lines BL may be connected to the channel structures 139 through contact plugs 199. The bit lines BL may include at least one selected from a metal, a conductive metal nitride, and a doped semiconductor material.

According to the first embodiment of the present invention, the selection transistor may have a channel region having a larger grain size than the memory cell transistors. Therefore, it is possible to alleviate the increase in the leakage current by the grain boundary. In addition, the select transistor can secure a relatively large volume of channel region compared to memory cell transistors, thereby reducing channel resistance.

4 to 14 are cross-sectional views and top views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 4, a substrate 100 is prepared. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a compound semiconductor substrate. For example, the substrate 100 may be doped with impurities of a first conductivity type.

A laminate structure in which first material layers and second material layers are alternately and repeatedly stacked on the substrate 100 may be provided. The second material layers may include a material different from the first material layers. For example, the first material layers may be sacrificial layers 110L, 110m, 110, and 110U. The second material layers may be insulating layers 120L, 120, and 120U. The sacrificial layers 110L, 110m, 110, and 110U may be formed of a material having an etch selectivity with respect to the insulating layers 120L, 120, and 120U. For example, the insulating layers 120L, 120, and 120U may be formed of an oxide, and the sacrificial layers 110L, 110m, 110, and 110U may include nitride and / or oxynitride.

The sacrificial layers 110L, 110m, 110, and 110U may be formed to have the same thickness. Unlike the sacrificial layers 110L, 110m, 110, and 110U, the upper select gate sacrificial layer 110U and the lower select gate sacrificial layer 110L are the upper select gate sacrificial layer 110U and the lower select gate sacrificial layer. It may be formed relatively thicker than the cell gate sacrificial layers 110m and 110 between the layers 110L. The upper select gate sacrificial layer 110U may occupy a space in which the upper select gate pattern to be described below will be formed, and the cell gate sacrificial layers 110m and 110 may occupy a space in which the cell gate patterns to be described below will be formed. Can be. The cell gate sacrificial layers may include an uppermost cell gate sacrificial layer 110m and cell gate sacrificial layers 110 below. The lower selection gate sacrificial layer 110L may occupy a space in which the lower selection gate pattern to be described below will be formed. The uppermost insulating layer 120U among the insulating layers 120L, 120, and 120U may be formed relatively thicker than the insulating layers 120 and 120L thereunder.

Before forming the sacrificial layers 110L, 110m, 110, and 110U and the insulating layers 120L, 120, and 120U, a buffer insulating layer 105 may be formed on the substrate 100. The sacrificial layers 110L, 110m, 110, and 110U and the insulating layers 120L, 120, and 120U may be formed on the buffer insulating layer 105. For example, the lower selection gate sacrificial layer 110L may be formed directly on the buffer insulating layer 105. The buffer insulating layer 105 may be formed of a dielectric material having an etch selectivity with respect to the sacrificial layers 110L, 110m, 110, and 110U. For example, the buffer insulating layer 105 may be formed of an oxide, in particular, a thermal oxide.

The buffer insulating layer 105, the insulating layers 120L, 120U, 120, and the sacrificial layers 110U, 110m, 110, and 110L are successively patterned to form first through regions exposing the substrate 100. 125) can be formed. The first through regions 125 may be formed using an anisotropic etching process. When the first through regions 125 are formed, an upper portion of the substrate 100 may be etched together as a result of over etching. The first through regions 125 may be two-dimensionally arranged on the substrate 100. The first through regions 125 may be circular, elliptical or polygonal in plan view.

Referring to FIG. 5, a first preliminary semiconductor layer 131 may be formed along sidewalls and a bottom of the first through regions 125. The first preliminary semiconductor layer 131 may be a silicon layer. For example, the first preliminary semiconductor layer 131 may not completely fill the first through regions 125. A buried film 155 may be formed on the first preliminary semiconductor layer 131 to fill the first through regions 125. For example, the buried film 155 may include at least one of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The first preliminary semiconductor layer 131 and the buried film 155 may be formed through chemical vapor deposition (CVD) or atomic layer deposition (ALD). In an embodiment, the formation of the first preliminary semiconductor layer 131 may include recrystallization by a first heat treatment process. When the semiconductor layer is substantially amorphous after deposition, the polycrystalline silicon film having relatively small grains may be formed by the recrystallization. The first heat treatment process may be a solid phase crystallization process. After the first preliminary semiconductor layer 131 and the buried film 155 are deposited, the uppermost insulating layer 120U may be exposed by a planarization process. Alternatively, the planarization process may not be performed.

6 to 8, an upper portion of the first preliminary semiconductor layer 131 is etched to form a first semiconductor layer 132. FIG. 7 is an enlarged view of the first semiconductor layer 132 of FIG. 6, and FIG. 8 is a top view of the first semiconductor layer 132. Top surfaces of the first semiconductor layer 132 may be exposed by the second through regions 126. The etching process may be performed at a depth between an upper surface of the uppermost cell gate sacrificial layer 110m and a lower surface of the upper selection gate sacrificial layer 110U. That is, lower surfaces of the second through regions 126 may be disposed between the upper surface of the uppermost cell gate sacrificial layer 110m and the lower surface of the upper selection gate sacrificial layer 110U.

An upper portion of the buried film 155 may be etched to form a buried pattern 156. For example, an upper surface of the buried pattern 156 may be disposed between the upper surface of the uppermost cell gate sacrificial layer 110m and the lower surface of the upper selection gate sacrificial layer 110U. The height of the top surface of the buried pattern 156 may be equal to or higher than the height of the top surface of the first semiconductor layer 132. An upper surface of the buried pattern 156 and an upper surface of the first semiconductor layer 132 may form a lower surface of the second through regions 126. Accordingly, the upper surface of the first semiconductor layer 132 may expose a relatively small number of crystal grains by the second through regions 126 as compared with the case where the buried pattern 156 is not provided.

The second through regions 126 may be formed by various etching processes such as dry etching, wet etching, or a combination thereof. In example embodiments, etching for forming the first semiconductor layer 132 and the buried pattern 156 may be simultaneously performed. In this case, the etching process may be performed with an etching recipe that has a slightly different etching rate with respect to the first semiconductor layer 132 and the buried pattern 156. As the etching process proceeds, a step may occur between the top surface of the first semiconductor layer 132 and the top surface of the buried pattern 156 due to the difference in the etching rates.

In another embodiment, an etching process for forming the first semiconductor layer 132 and the buried pattern 156 may be performed. In another embodiment, after etching the first preliminary semiconductor layer 131 and the buried film 155 together, one of the first preliminary semiconductor layer 131 or the buried film 155 may be further etched. Additional processes can be performed. When the buried layer 155 is etched, a portion of the uppermost insulating layer 120U or the upper selection gate sacrificial layer 110U may be etched together.

9 to 11, a second semiconductor layer 133 may be formed to fill the second through regions 126. FIG. 10 is an enlarged view of the first and second semiconductor layers 132 and 133 of FIG. 9, and FIG. 11 is a top view of the second semiconductor layer 133. The second semiconductor layer 133 may include at least one of silicon or silicon-germanium. The second semiconductor layer 133 is formed through an epitaxial growth process in which the top surface of the first semiconductor layer 132 exposed by the second through regions 126 is seeded. Can be formed. That is, an epitaxial process may be performed by using the crystal grains forming the upper surface of the first semiconductor layer 132 as seeds. The first semiconductor layer 132 exposes a relatively small number of crystal grains as compared to the case where the buried pattern 156 is absent. Therefore, when the second semiconductor layer 133 is grown with the first semiconductor layer 132 as the seed, the second semiconductor layer 133 is formed with a relatively small number of crystal grains as shown in FIG. 11. Can be configured. Each of the crystal grains grown using the first semiconductor layer 132 as a seed may contact each other on the buried pattern 156 to form a grain boundary. During the growth process, some grains may be merged with each other, one grain may be divided into a plurality of grains, or only some of the seed grains may be maintained until the process is completed, but the second semiconductor layer 133 may be maintained. The number of grains may be formed in a number similar to the number of seed grains. Crystal grains constituting the second semiconductor layer 133 may have a shape extending in a direction perpendicular to the upper surface of the substrate 100. The second semiconductor layer 133 may be formed higher than an upper surface of the uppermost insulating layer 120U, and may be substantially the same height as the uppermost insulating layer 120U through a planarization process. The second semiconductor layer 133 may be intrinsic or doped with a first type impurity.

Referring to FIG. 12, the sacrificial layers 110U, 110m, 110, and 110L may be removed. The removal process may include forming the first trench 140 by successively patterning the insulating layers 120U, 120, and 120L and the sacrificial layers 110U, 110m, 110, and 110L. By forming the first trench 140, the insulating layers 120U, 120, and 120L may be separated into insulating patterns 120Ua, 120a, and 102La, respectively. Forming the first trench 140 may be performed by an anisotropic etching process. The sacrificial patterns 110La, 110m, 110a, and 110Ua exposed by the first trench 140 may be removed by a selective etching process to form recess regions 145L, 145, and 145U. In the selective etching process, an etch rate of the sacrificial patterns 110La, 110m, 110a, and 110Ua may be etched from the insulating patterns 120La, 120a, 120Ua, the buffer insulating layer 105, and the semiconductor pattern 136. May be greater than the rates. Accordingly, after the selective etching process, the insulating patterns 120La, 120a, and 120Ua, the buffer insulating layer 105, and the channel structures 139 may remain. The recess regions 145L, 145, and 145U may expose portions of sidewalls of the channel structures 139 that are in contact with the sacrificial patterns 110La, 110m, 110a, and 110Ua, respectively.

Referring to FIG. 13, an information storage layer 150 may be formed on a resultant product on which the recess regions 145L, 145, and 145U are formed. The information storage layer 150 may be formed using a deposition technique (eg, CVD or ALD) that may provide excellent step coverage. As a result, the information storage layer 150 may be formed substantially conformally along the recess regions 145L, 145, and 145U. The information storage layer 150 may fill a portion of the recess regions 145L, 145, and 145U. The structure of the information storage film 150 will be described in more detail below with reference to FIGS. 25 and 26.

After forming the information storage layer 150, a gate conductive layer 158 may be formed to fill the recess regions 145L, 145, and 145U. The gate conductive layer 158 may fill at least a portion of the first trench 140. The gate conductive layer 158 may be electrically separated from the channel structures 139 and the substrate 100 by the information storage layer 150. The gate conductive layer 158 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer chemical vapor deposition (ALD). The gate conductive layer 158 may include at least one selected from a metal, a metal silicide, a conductive metal nitride, a doped semiconductor material, and the like.

Referring to FIG. 14, after the gate conductive layer 158 is formed, a portion of the gate conductive layer 158 positioned outside the recess regions 145L, 145, and 145U is removed to remove the recess region. Gate electrodes 157L, 157m, 157, and 157U are formed in the fields 145L, 145, and 145U. The gate conductive layer 158 located outside the recess regions 145L, 145, and 145U may be removed by a wet etching process and / or a dry etching process. As a result, the second trench 141 may be formed.

The lowermost pattern of the gate electrodes may be a lower selection gate pattern 157L, and the uppermost pattern may be an upper selection gate pattern 157U. Cell gate patterns 157m and 157 may be provided between the lower select gate pattern 157L and the upper select gate pattern 157U. The cell gate patterns may include an uppermost cell gate pattern 157m and cell gate patterns 157 thereunder.

A first impurity region 170 may be formed in the substrate 100 under the bottom of the second trench 141. The first impurity region 170 may extend along the second trench 141. The first impurity region 170 may be formed by implanting impurity ions of a second conductivity type. The uppermost insulating pattern 120Ua may be used as an ion implantation mask.

A second impurity region 198 may be formed on the channel structures 139. The second impurity region 198 may be an impurity doped region of the second conductivity type. A lower surface of the second impurity region 198 may be higher than an upper surface of the upper selection gate pattern 157U. The second impurity region 198 may be formed simultaneously with the first impurity region 170. Alternatively, the second impurity region 198 may be formed before forming the first impurity region 170. In this case, the second impurity region 198 may be formed after forming the channel structures 139 and before forming the second trench 141. Alternatively, the second impurity region 198 may be formed after forming the first impurity region 170.

An isolation pattern 175 may be formed to fill the second trench 141. Forming the device isolation pattern 175 may include forming a device isolation layer filling the second trench 141 on the substrate 100 and the information storage layer 150 on the uppermost insulating pattern 120Ua. And performing a planarization process on the upper surface of the etch stop layer. The device isolation pattern 175 may include an insulating material. For example, the device isolation pattern 175 may be formed of a high density plasma oxide film, a spin on glass layer, and / or a CVD oxide film. After forming the device isolation pattern 175, the exposed information storage layer 150 may be etched to expose the uppermost insulating pattern 120Ua. In this case, the second impurity region 198 may be exposed together.

Referring back to FIG. 2, bit lines BL electrically connected to the second impurity region 198 may be formed. The bit lines BL may extend in the x direction. An interlayer insulating layer (not shown) covering the uppermost insulating pattern 120Ua and the device isolation pattern 175 may be formed, and the bit lines BL may be formed on the interlayer insulating layer. The bit lines BL may be electrically connected to the second impurity region 198 via contact plugs 199 penetrating the interlayer insulating layer. The contact plugs 199 may include at least one of a metal, a conductive metal nitride, or a doped semiconductor material.

15 and 16, a semiconductor device according to a second embodiment of the present invention will be described. 15 is a perspective view of a semiconductor device according to a second exemplary embodiment of the present invention, and FIG. 16 is an enlarged view of the channel structure of FIG. 15. Some structures and forming methods of this embodiment are similar to those of the first embodiment above. Therefore, for the sake of brevity of description, descriptions of overlapping technical features may be omitted below.

15 and 16, a laminated structure is provided on a substrate 100. The stack structure may include gate patterns and insulating patterns repeatedly stacked alternately on the substrate 100. The gate patterns may include a lower select gate pattern 157L, cell gate patterns 157m and 157, and an upper select gate pattern 157U. The cell gate patterns may include an uppermost cell gate pattern 157m and cell gate patterns 157 thereunder. A buffer insulating layer 105 may be provided between the substrate 100 and the lower selection gate pattern 157L. The insulating patterns may include an uppermost insulating pattern 120Ua, a lowermost insulating pattern 120La, and intermediate insulating patterns 120a between the uppermost insulating pattern 120Ua and the lowermost insulating pattern 120La.

Channel structures 139 may extend from the substrate 100 and pass through the gate patterns 157U, 157m, 157, and 157L and the insulating patterns 120Ua, 120a, and 120La. The channel structures 139 may be provided in the first through regions 125 passing through the gate patterns 157U, 157m, 157, and 157L and the insulating patterns 120Ua, 120a, and 120La.

The channel structures 139 may include a first region P1 including a first semiconductor layer 132 and a third region P3 including a second semiconductor layer 133. The first region may be an active region of the cell gate patterns 157m and 157 and the lower selection gate pattern 157L, and the third region P3 may be the upper selection gate pattern 157U. It may be an active region of. The third region P3 may be provided on the first region P1. A boundary between the first region P1 and the third region P3 may be provided between the upper selection gate pattern 157U and the uppermost cell gate pattern 157m. The first and second semiconductor layers 132 and 133 may form part of the semiconductor pattern 136. The third region P3 may be adjacent to the upper selection gate pattern 157U, and the first region P1 may be adjacent to the cell gate patterns 157m and 157. That is, when the upper select gate pattern 157U is a gate electrode of the string select transistor, a part of the third region P3 may be a channel region of the string select transistor. When the cell gate patterns 157m and 157 are gate electrodes of a memory cell transistor, a portion of the first region P1 may be a channel region of the memory cell transistor.

The grain size in the third region P3 may be larger than the grain size in the first region P1. For example, crystal grains in the third region P3 may be disposed in a direction perpendicular to the substrate 100 (z direction) than a width in a direction parallel to the surface of the substrate 100 (x direction or y direction). May be larger in length. For example, an aspect ratio of grains in the third region P3 may be about 2 to about 100. For example, the length of the crystal grains in the third direction P3 in the z direction may be greater than the thickness of the upper selection gate pattern 157U. That is, the string select transistor may have a channel region having a larger grain size than the memory cell transistors. Therefore, the area of grain boundaries in the channel region of the string select transistor can be reduced. Thereby, it is possible to improve the electrical characteristics of the semiconductor element such as leakage current which may be generated by the grain boundary.

The channel structures 139 may further include a buried pattern 156 surrounded by the semiconductor pattern 136. For example, the semiconductor pattern 136 may be provided along the lower surface and the inner wall of the first through regions 125, and the buried pattern 156 may be filled in the semiconductor pattern 136. The buried pattern 156 may be spaced apart from the substrate 100 by the semiconductor pattern 136. An upper surface of the buried pattern 156 may be higher than an upper surface of the upper selection gate pattern 157U.

An isolation pattern 175 extending between the channel structures 139 may be provided. The first impurity region 170 may be formed in the substrate 100 under the device isolation pattern 175. The first impurity region 170 may have a line shape extending in the y direction. The first impurity region 170 may be a region doped with a second conductivity type impurity. The second conductivity type may be a different conductivity type than the first conductivity type.

First and second information storage layers DA1 and DA2 may be provided between the gate patterns 157U, 157m, 157, and 157L and the channel structures 139. The first information storage layer DA1 may extend vertically along sidewalls of the first through regions 125. The second information storage layer DA2 may extend along the top, bottom, and sidewalls of the gate patterns 157U, 157m, 157, and 157L. Structures of the information storage layers DA1 and DA2 will be described below in more detail with reference to FIGS. 25 and 26.

The second impurity region 198 may be provided on the semiconductor pattern 136 adjacent to the uppermost insulating pattern 120Ua. The second impurity region 198 may be an impurity region of the same conductivity type as the first impurity region 170. Bit lines BL extending in a direction crossing the gate patterns 157U, 157m, 157, and 157L (for example, x directions) and electrically connected to the second impurity region 198 are provided. . The bit lines BL may be connected to the channel structures 139 through contact plugs 199. The bit lines BL may include at least one selected from a metal, a conductive metal nitride, and a semiconductor material.

17 to 24 are cross-sectional views and a top view illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

Referring to FIG. 17, a laminate structure in which first material layers and second material layers are alternately and repeatedly stacked on the substrate 100 may be provided. The first material layers may be sacrificial layers 110L, 110m, 110, and 110U. The second material layers may be insulating layers 120L, 120, and 120U. The sacrificial layers may include an upper selection gate sacrificial layer 110U, cell gate sacrificial layers 110m and 110, and a lower selection gate sacrificial layer 110L. Before forming the sacrificial layers 110L, 110m, 110, and 110U and the insulating layers 120L, 120, and 120U, a buffer insulating layer 105 may be formed on the substrate 100.

The buffer insulating layer 105, the insulating layers 120L, 120U, 120, and the sacrificial layers 110U, 110m, 110, and 110L are successively patterned to form first through regions exposing the substrate 100. 125) can be formed. The first through regions 125 may be formed using an anisotropic etching process. The first through regions 125 may be two-dimensionally arranged along the x direction and the y direction. The first through regions 125 may be circular, elliptical or polygonal in plan view.

A first information storage layer DA1 may be formed along sidewalls and bottom surfaces of the first through regions 125. The first information storage layer DA1 may include at least one insulating layer. A detailed configuration of the first information storage layer DA1 will be described below in more detail with reference to FIGS. 25 and 26.

Referring to FIG. 18, a first preliminary semiconductor layer 131 and a buried film 155 may be sequentially formed in the first through regions 125. The first preliminary semiconductor layer 131 may be formed on the first information storage layer DA1. Before forming the first preliminary semiconductor layer 131, a lower portion of the first information storage layer DA1 may be etched to expose the substrate 100. Therefore, the first preliminary semiconductor layer 131 may be electrically connected to the substrate 100. The etching of the first information storage layer DA1 forms a spacer (not shown) exposing a lower portion of the first information storage layer DA1 on sidewalls of the first through regions 125. The spacer may be used as an etching mask. The spacer may comprise a silicon material. The spacer may be removed after the etching process or may not form a portion of the first preliminary semiconductor layer 131. The formation of the first preliminary semiconductor layer 131 may include a recrystallization process by a first heat treatment process. By the recrystallization process, the first preliminary semiconductor layer 131 may be a polycrystalline silicon film having relatively small crystal grains. For example, the first heat treatment process may be a solid phase crystallization process. After the first preliminary semiconductor layer 131 and the buried film 155 are deposited, the uppermost insulating layer 120U may be exposed by a planarization process. Alternatively, the planarization process may not be performed.

19 to 21, an upper portion of the first preliminary semiconductor layer 131 is etched to form a first semiconductor layer 132. FIG. 20 is an enlarged view of the first semiconductor layer 132 of FIG. 19, and FIG. 21 is a top view of the first semiconductor layer 132. The first semiconductor layer 132 may have an upper surface exposed by the second through regions 126. The etching process may be performed at a depth between an upper surface of the uppermost cell gate sacrificial layer 110m and a lower surface of the upper selection gate sacrificial layer 110U. That is, lower surfaces of the second through regions 126 may be disposed between the upper surface of the uppermost cell gate sacrificial layer 110m and the lower surface of the upper selection gate sacrificial layer 110U.

An upper portion of the buried film 155 may be etched to form a buried pattern 156. For example, an upper surface of the buried pattern 156 may be higher than an upper surface of the upper selection gate sacrificial layer 110U and lower than an upper surface of the uppermost insulating layer 120U. When the buried layer 155 is etched, an upper portion of the first information storage layer DA1 may be etched together. Alternatively, the upper portion of the first information storage layer DA1 may not be etched.

Upper surfaces of the first semiconductor layers 132 may form lower surfaces of the second through regions 126. Accordingly, the upper surface of the first semiconductor layer 132 may expose a relatively small number of crystal grains in the second through regions 126, as compared with the case where the buried pattern 156 is not present.

The second through regions 126 may be formed by various etching processes such as dry etching, wet etching, or a combination thereof. In example embodiments, etching for forming the first semiconductor layer 132 and the buried pattern 156 may be simultaneously performed. In this case, the etching process may be performed with an etching recipe having a relatively high etching rate with respect to the first semiconductor layer 132. In another embodiment, an etching process for forming the first semiconductor layer 132 and the buried pattern 156 may be performed. In another embodiment, the buried pattern 156 may be formed after the formation of the second semiconductor layer 133 to be described below.

Referring to FIGS. 22 and 23, a second semiconductor layer 133 may be formed to fill the second through regions 126. FIG. 22 is an enlarged view of the first and second semiconductor layers 132 and 133 of FIG. 21. An upper side view of the second semiconductor layer 133 may be substantially the same as that of FIG. 11. The second semiconductor layer 133 may include at least one of silicon or silicon-germanium. The second semiconductor layer 133 may be formed through an epitaxial growth process of seeding the first semiconductor layer 132 exposed by the second through regions 126. Can be. That is, an epitaxial process may be performed by using the crystal grains forming the upper surface of the first semiconductor layer 132 as seeds. The first semiconductor layer 132 exposes a relatively small number of crystal grains as compared to the case where the buried pattern 156 is absent. Therefore, when the second semiconductor layer 133 is grown with the first semiconductor layer 132 as the seed, the second semiconductor layer 133 is formed with a relatively small number of crystal grains as shown in FIG. 11. Can be configured. Each of the crystal grains grown using the first semiconductor layer 132 as a seed may contact each other on the buried pattern 156 to form a grain boundary. During the growth process, some grains may be merged with each other, one grain may be divided into a plurality of grains, or only some of the seed grains may be maintained until the process is completed, but the second semiconductor layer 133 may be maintained. The number of grains may be formed in a number similar to the number of seed grains. Crystal grains constituting the second semiconductor layer 133 may have a shape extending in a direction perpendicular to the upper surface of the substrate 100. The second semiconductor layer 133 may be formed higher than an upper surface of the uppermost insulating layer 120U, and may be substantially the same height as the uppermost insulating layer 120U through a planarization process. The second semiconductor layer 133 may be intrinsic or doped with a first type impurity.

Referring to FIG. 24, after the sacrificial layers 110U, 110m, 110, and 110L are removed to form recess regions (not shown), a second information storage layer DA2 and a gate are formed in the recess regions. Electrodes 157L, 157m, 157, 157U are formed. The lowermost pattern of the gate electrodes may be a lower selection gate pattern 157L, and the uppermost pattern may be an upper selection gate pattern 157U. Cell gate patterns 157m and 157 may be provided between the lower select gate pattern 157L and the upper select gate pattern 157U. The cell gate patterns may include an uppermost cell gate pattern 157m and cell gate patterns 157 thereunder.

A first impurity region 170 may be formed in the substrate 100 under the bottom surface of the second trench 141. The first impurity region 170 may be formed by implanting dopant ions of the second type. A second impurity region 198 may be formed on the channel structures 139. The second impurity region 198 may be a region doped with a dopant of the second type. A lower surface of the second impurity region 198 may be higher than an upper surface of the upper selection gate pattern 157U. For example, the second impurity region 198 may be formed simultaneously with the first impurity region 170. An isolation pattern 175 may be formed to fill the second trench 141.

Referring back to FIG. 15, bit lines BL may be formed to be electrically connected to the second impurity region 198. The bit lines BL may extend in the x direction. The bit lines BL may be electrically connected to the second impurity region 198 via contact plugs 199 passing through the interlayer insulating layer (not shown). The contact plugs 199 may include at least one of a metal, a conductive metal nitride, or a doped semiconductor material.

25 and 26 are perspective views illustrating a structure of an information storage film according to embodiments of the present invention.

25 is a perspective view illustrating an information storage film 150 according to embodiments of the present invention. More specifically, the information storage film 150 of FIG. 25 may be the information storage film shown in the first embodiment of the present invention.

The buried pattern DP and the semiconductor pattern SP may be provided in the first through regions 125, and the information storage layer 150 may be provided on the sidewall of the semiconductor pattern SP. The information storage layer 150 may include a tunnel insulating layer TIL, a charge storage layer CL, and a blocking insulating layer BLL that are sequentially stacked in the recess regions 145. The films constituting the information storage film 150 may be formed using a deposition technique (eg, chemical vapor deposition or atomic layer deposition technique) that may provide excellent step coverage.

The charge storage layer CL may be one of insulating layers rich in trap sites and insulating layers including nanoparticles, and may be formed using one of chemical vapor deposition or atomic layer deposition techniques. For example, the charge storage layer CL may include one of an insulating film including a trap insulating film, a floating gate electrode, or conductive nano dots. For example, the charge storage layer CL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, nanocrystalline silicon, and a laminated trap layer. It may include.

The tunnel insulating layer TIL may be one of materials having a band gap larger than that of the charge storage layer CL, and may be formed using one of chemical vapor deposition or atomic layer deposition techniques. For example, the tunnel insulating film TIL may be a silicon oxide film formed using one of the above-described deposition techniques. In addition, a predetermined heat treatment step performed after the deposition process on the tunnel insulating film TIL may be further performed. The heat treatment step may be a rapid thermal nitriding process (RTN) or an annealing process performed in an atmosphere including at least one of nitrogen and oxygen.

The blocking insulating layer BLL may be a single insulating layer. In contrast, the blocking insulating layer BLL may include first and second blocking insulating layers (not shown). The first and second blocking insulating layers may be formed of different materials, and one of the first and second blocking insulating layers may have a band gap smaller than that of the tunnel insulating layer TIL and larger than the charge storage layer CL. It may be one of the materials having. In addition, the first and second blocking insulating layers may be formed using one of chemical vapor deposition or atomic layer deposition techniques, and at least one of them may be formed through a wet oxidation process. In example embodiments, the first blocking insulating layer may be one of high dielectric layers such as an aluminum oxide layer and a hafnium oxide layer, and the second blocking insulating layer may be formed of a material having a dielectric constant smaller than that of the first blocking insulating layer. In example embodiments, the second blocking insulating layer may be one of the high dielectric layers, and the first blocking insulating layer may be formed of a material having a dielectric constant smaller than that of the second blocking insulating layer.

26 is a perspective view illustrating a structure of an information storage film according to other embodiments of the present invention. More specifically, the information storage layers DA1 and DA2 of FIG. 26 may be the information storage layers shown in the second embodiment of the present invention. The information storage film according to the present embodiment may include a first information storage film DA1 and a second information storage film DA2. The first information storage layer DA1 may be formed in the first through regions 125 and may extend along sidewalls of the first through regions 125. The second information storage layer DA2 may be formed in the recess regions 145. The first and second information storage layers DA1 and DA2 may each include at least one of the blocking insulating layer BLL, the charge storage layer CL, and the tunnel insulating layer TIL.

27 is a schematic block diagram illustrating an example of a memory system including a semiconductor memory device manufactured according to the manufacturing method of embodiments of the present disclosure.

Referring to FIG. 27, the memory system 1100 may include a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, It can be applied to a memory card or any device capable of transmitting and / or receiving information in a wireless environment.

The memory system 1100 includes an input / output device 1120 such as a controller 1110, a keypad, a keyboard and a display, a memory 1130, an interface 1140, and a bus 1150. Memory 1130 and interface 1140 are in communication with one another via bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other similar process device. Memory 1130 may be used to store instructions performed by the controller. The input / output device 1120 may receive data or a signal from the outside of the memory system 1100 or output data or a signal to the outside of the memory system 1100. For example, the input / output device 1120 may include a keyboard, a keypad, or a display device.

The memory 1130 includes a nonvolatile memory device according to embodiments of the present invention. The memory 1130 may also further include other types of memory, volatile memory that can be accessed at any time, and various other types of memory. The interface 1140 serves to transmit data to and receive data from the communication network.

28 is a schematic block diagram illustrating an example of a memory card including a semiconductor memory device manufactured according to the manufacturing method of the embodiments of the present invention.

Referring to FIG. 28, a flash memory device 1210 according to embodiments of the present invention may be mounted in a memory card 1200 to support a high capacity of data storage. The memory card 1200 according to the embodiments of the present invention includes a memory controller 1220 that controls overall data exchange between the host and the flash memory device 1210.

The SRAM 1221 is used as the operating memory of the processing unit 1222. The host interface 1223 includes a data exchange protocol of a host that is connected to the memory card 1200. Error correction block 1224 detects and corrects errors contained in data read from multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs various control operations for exchanging data of the memory controller 1220. Although it is not shown in the drawing, the memory card 1200 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned.

29 is a schematic block diagram illustrating an example of an information processing system equipped with a semiconductor memory device manufactured according to the manufacturing method of the embodiments of the present invention.

Referring to FIG. 29, the memory system 1310 of the present invention is mounted in an information processing system such as a mobile device or a desktop computer. The information processing system 1300 according to the present invention includes a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350 electrically connected to a memory system 1310 and a system bus 1360, respectively. Include. The memory system 1310 may be configured substantially the same as the memory system or the memory system mentioned above. The memory system 1310 stores data processed by the CPU 1330 or data externally input. The above-described memory system 1310 may include a semiconductor disk device (SSD), in which case the information processing system 1300 may stably store large amounts of data in the memory system 1310. As the reliability increases, the memory system 1310 may reduce resources required for error correction, thereby providing a high speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention may be further provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. Self-explanatory to those who have learned.

In addition, the flash memory device or the memory system according to the present invention may be mounted in various types of packages. For example, a flash memory device or a memory system according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package. (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline ( SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer- It can be packaged and mounted in the same manner as Level Processed Stack Package (WSP).

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

100: substrate 105: buffer insulating film
110: sacrificial film 120: insulating film
139: channel structure 157: gate patterns
156: buried pattern 175: device isolation pattern

Claims (10)

A stack structure including cell gate patterns and a selection gate pattern on the cell gate patterns; And
A semiconductor pattern electrically connected to the substrate through the stack structure;
The semiconductor pattern is:
A first region that is an active region of the cell gate patterns; And
A second region which is an active region of the selection gate pattern,
The grain size of the second region is larger than the grain size of the first region. The method of claim 1,
The crystal grains of the second region are larger in length in the direction perpendicular to the substrate than in width in the direction parallel to the surface of the substrate. The method of claim 1,
Further comprising a buried pattern surrounded by the first region,
And a top surface of the buried pattern is provided between an uppermost layer of the cell gate patterns and the selection gate pattern. The method of claim 1,
And a buried pattern surrounded by the first region and the second region,
The upper surface of the buried pattern is higher than the upper surface of the selection gate pattern. Repeatedly stacking first and second material films on the substrate;
Patterning the first and second material films to form a first through region exposing the substrate;
Sequentially forming a first semiconductor layer and a buried film in the first through region;
Etching a portion of the first semiconductor layer to form a second through region; And
Forming a second semiconductor layer in the second through region,
And the second semiconductor layer is formed by an epitaxial process of seeding the first semiconductor layer exposed by the second through region. The method of claim 5, wherein
And a grain size of the second semiconductor layer is larger than a grain size of the first semiconductor layer in a direction perpendicular to the upper surface of the substrate. The method according to claim 6,
Forming the second through region further comprises etching an upper portion of the buried film,
The top surface of the etched buried film is a manufacturing method of a semiconductor memory device higher than the top surface of the etched first semiconductor layer. The method according to claim 6,
Replacing the second material film with gate electrodes,
The gate electrodes include cell gate patterns and a selection gate pattern on the cell gate patterns,
The etching process of the first semiconductor layer is performed to a depth between the uppermost layer of the cell gate patterns and the selection gate pattern. The method of claim 8,
Forming the second through region further comprises etching an upper portion of the buried film,
The upper surface of the etched buried film is a semiconductor memory device manufacturing method lower than the lower surface of the selection gate pattern. The method of claim 8,
Forming the second through region further comprises etching an upper portion of the buried film,
And etching the buried film to a depth higher than an upper surface of the selection gate pattern.

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