KR101843567B1 - Semiconductor memory device and method of forming the same - Google Patents

Abstract

A semiconductor device is provided. There is provided a semiconductor pattern that is electrically connected to a substrate through a laminate structure and a laminate structure including cell gate patterns and a selection gate pattern on cell gate patterns. The semiconductor pattern includes a first region which is an active region of the cell gate patterns and a second semiconductor region which is an active region of the select gate pattern, and the grain size of the second region is larger than the grain size of the first semiconductor region.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor memory device and a manufacturing method thereof.

As the electronics industry develops, the degree of integration of semiconductor memory devices is increasing. The degree of integration of semiconductor memory devices is an important factor in determining the price of a product. That is, as the degree of integration increases, the product price of the semiconductor memory device may decrease. As a result, there is a growing demand for improvement in the degree of integration of semiconductor memory devices. Generally, the degree of integration of the semiconductor memory device is largely influenced by the level of the fine pattern forming technique, since it is mainly determined by the planar area occupied by the unit memory cell. However, miniaturization of patterns is becoming more and more limited due to expensive equipment and difficulty of semiconductor manufacturing process.

In order to overcome these limitations, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. However, in order to mass-produce a three-dimensional semiconductor memory device, a process technology capable of reducing the manufacturing cost per bit of the two-dimensional semiconductor memory device and realizing a reliable product characteristic is required.

SUMMARY OF THE INVENTION The present invention provides a semiconductor memory device having improved electrical characteristics and a method of manufacturing the same.

It is another object of the present invention to provide a semiconductor memory device optimized for high integration and a manufacturing method thereof.

A semiconductor device for achieving the above object is provided. Wherein the device comprises a laminate structure including cell gate patterns and a select gate pattern on the cell gate patterns and a semiconductor pattern electrically connected to the substrate through the laminate structure, And a second semiconductor region that is an active region of the select gate pattern, wherein a grain size of the second semiconductor region may be larger than a grain size of the first semiconductor region.

In one embodiment, the crystal grains of the second semiconductor region may have a greater length in a direction perpendicular to the substrate than a width in a direction parallel to the surface of the substrate.

In one embodiment, the semiconductor device further includes a buried pattern surrounded by the first semiconductor region, and an upper surface of the buried pattern may be provided between the uppermost one of the cell gate patterns and the select gate pattern.

In one embodiment, the semiconductor device further includes a buried pattern surrounded by the first semiconductor region and the second semiconductor region, wherein an upper surface of the buried pattern may be higher than an upper surface of the select gate pattern.

A method of fabricating a semiconductor device for achieving the above object is provided. The method includes: laminating first and second material layers alternately and repeatedly on a substrate; patterning the first and second material layers to form a first through region exposing the substrate; Forming a first semiconductor layer and a buried film in the region in order; etching a portion of the first semiconductor layer to form a second penetrating region; and forming a second semiconductor layer in the second penetrating region, The second semiconductor layer may be formed by an epitaxial process in which the first semiconductor layer exposed by the second through region is a seed.

In one embodiment, forming the second penetrating region further includes etching the top of the buried layer, and the top surface of the etched buried layer may be higher than the top surface of the etched first semiconductor layer.

In one embodiment, the method further comprises replacing the second material layer with gate electrodes, wherein the gate electrodes comprise cell gate patterns and a select gate pattern on the cell gate patterns, The etch process may be performed at a depth between the top of the cell gate patterns and the select gate pattern.

In one embodiment, forming the second through region further includes etching the upper portion of the buried layer, and the upper surface of the etched buried layer may be lower than the lower portion of the select gate pattern.

In one embodiment, forming the second through region further comprises etching the top of the buried layer, and the etching process of the buried layer may be performed to a depth greater than the top surface of the select gate pattern.

According to an embodiment of the present invention, channel patterns having different structures of channel regions adjacent to the cell gate pattern and the selection gate pattern may be provided. The grain size of the channel regions adjacent to the select gate pattern can be relatively increased to improve the electrical characteristics of the semiconductor device.

1 is a circuit diagram of a semiconductor device according to embodiments of the present invention.
2 is a perspective view of a semiconductor device according to a first embodiment of the present invention.
Figure 3 is an enlarged view of the channel structure of Figure 2;
FIGS. 4 to 14 are cross-sectional views and top view views illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
15 is a perspective view of a semiconductor device according to a second embodiment of the present invention.
16 is an enlarged view of the channel structure of Fig.
17 to 24 are cross-sectional views and a top view of the semiconductor device according to the second embodiment of the present invention.
25 and 26 are perspective views illustrating a structure of an information storage layer according to embodiments of the present invention.
27 is a schematic block diagram illustrating an example of a memory system including a semiconductor device formed in accordance with embodiments of the present invention.
28 is a schematic block diagram showing an example of a memory card having semiconductor elements according to the embodiments of the present invention.
29 is a schematic block diagram showing an example of an information processing system for mounting a semiconductor device according to the embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In this specification, when a layer is referred to as being on another layer or substrate, it may be directly formed on another layer or substrate, or a third layer may be interposed therebetween. Also, in the drawings, The size and thickness of the configurations are exaggerated for clarity. Also, while the terms first, second, third, etc. in the various embodiments of the present disclosure are used to describe various regions, layers, etc., these regions and films should not be limited by these terms . These terms are merely used to distinguish certain regions or layers from other regions or layers. Thus, the membrane referred to as the first membrane in one embodiment may be referred to as the second membrane in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Like numbers refer to like elements throughout the specification.

1 is a circuit diagram of a semiconductor memory device according to embodiments of the present invention.

1, a semiconductor memory device according to embodiments of the present invention includes a common source line CSL, a plurality of bit lines BL0-BL3, and a common source line CSL and bit lines BL0 And a plurality of cell strings CSTR disposed between the cell strings BLl and BLl.

The common source line CSL may be an electrically conductive thin film disposed on the semiconductor substrate or an impurity region formed in the substrate. The bit lines BL0-BL3 may be conductive patterns that are spaced apart from the semiconductor substrate and disposed thereon. The bit lines BL0-BL3 are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines BL0-BL3. Accordingly, the cell strings CSTR are two-dimensionally arranged on the common source line CSL or the substrate.

Each of the cell strings CSTR includes a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit lines BL0-BL3, And a plurality of memory cell transistors MCT arranged between the memory cells GST and SST. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series. In addition, the ground selection line GSL, the plurality of word lines WL0-WL3 and the string selection lines SSL0-BL3 disposed between the common source line CSL and the bit lines BL0- SSL2 may be used as the gate electrodes of the ground selection transistor GST, the memory cell transistors MCT, and the string selection transistors SST, respectively.

The ground selection transistors GST may be disposed at substantially the same distance from the substrate, and their gate electrodes may be connected in common to the ground selection line GSL to be in an equipotential state. To this end, the ground selection line GSL may be a plate-like or comb-shaped conductive pattern disposed between the common source line CSL and the memory cell transistor MCT closest thereto. have. Likewise, the gate electrodes of the memory cell transistors MCT, which are disposed at substantially the same distance from the common source line CSL, are also commonly connected to one of the word lines WL0-WL3, Lt; / RTI > To this end, each of the word lines WL0-WL3 may be a flat plate-shaped or comb-shaped conductive pattern parallel to the upper surface of the substrate. On the other hand, since one cell string CSTR is composed of a plurality of memory cell transistors MCT having different distances from the common source line CSL, the common source line CSL and the bit lines BL0 to BL3 are arranged between the word lines WL0 to WL3.

Each of the cell strings CSTR may include a channel structure that extends vertically from the common source line CSL and connects to the bit lines BL0 to BL3. The channel structure may include a semiconductor layer. The semiconductor layer may be formed to penetrate the ground selection line GSL and the word lines WL0 to WL3. In addition, the semiconductor layer may include impurity regions formed at one or both ends of the body portion and the body portion. For example, a drain region may be formed at the top of the semiconductor layer.

Meanwhile, an information storage layer may be disposed between the word lines WL0-WL3 and the semiconductor layer. According to one embodiment, the information storage film may be a charge storage film. For example, the information storage film may be one of an insulating film including a trap insulating film, a floating gate electrode, or conductive nano dots.

A dielectric film used as a gate insulating film of the ground selection transistor GST or the string selection transistor SST is formed between the ground selection line GSL and the semiconductor layer or between the string selection lines SSL0- Can be arranged. The gate insulating film of at least one of the ground and string select transistors GST and SST may be formed of the same material as that of the information storage film of the memory cell transistor MCT but may be a gate insulating film for a typical MOSFET have.

The ground and string select transistors GST and SST and the memory cell transistors MCT may be MOS field effect transistors (MOSFETs) using a semiconductor layer as a channel region. According to another embodiment, the semiconductor layer may comprise a MOS capacitor together with the ground selection line GSL, the word lines WL0-WL3 and the string selection lines SSL0-SSL2 . In this case, the ground selection transistor GST, the memory cell transistors MCT and the string selection transistor SST are connected to the ground selection line GSL, the word lines WL0 to WL3, Can be electrically connected by sharing an inversion layer formed by a fringe field from the gate line (SSL0-SSL2).

2 and 3, a semiconductor device according to a first embodiment of the present invention is described. FIG. 2 is a perspective view of a semiconductor device according to a first embodiment of the present invention, and FIG. 3 is an enlarged view of the channel structure of FIG.

Referring to Figures 2 and 3, a laminate structure is provided on a substrate 100. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may be of the first conductivity type. For example, the first conductivity type may be p-type. The stacked structure may include gate patterns and insulating patterns which are alternately stacked on the substrate 100 repeatedly. The gate patterns may include a lower select gate pattern 157L, cell gate patterns 157m and 157, and an upper select gate pattern 157U. The cell gate patterns may include an uppermost cell gate pattern 157m and cell gate patterns 157 below the uppermost cell gate pattern 157m. A buffer insulating layer 105 may be provided between the substrate 100 and the lower selection gate pattern 157L. The buffer insulating layer 105 may be a silicon oxide layer. For example, the lower and upper select gate patterns 157L and 157U may be thicker than the cell gate patterns 157m and 157, respectively. Alternatively, the lower and upper selection gate patterns 157L and 157U may be formed to have substantially the same thickness as the cell gate patterns 157m and 157, respectively.

The insulating patterns may include an uppermost insulating pattern 120Ua, a lowermost insulating pattern 120La and intermediate insulating patterns 120a between the uppermost insulating pattern 120Ua and the lowest insulating pattern 120La. The gate patterns 157U, 157m, 157 and 157L and the insulation patterns 120Ua, 120a and 120La may extend in the horizontal direction, for example, the y direction. Only six of the gate patterns 157U, 157m, 157 and 157L and the insulating patterns 120Ua, 120a and 120La are shown, but these are omitted for the sake of simplicity. Although the lower and upper selection gate patterns 157L and 157U are shown one by one, they may be formed of two or more gate patterns.

The gate patterns 157U, 157m, 157, and 157L may include at least one selected from a metal, a metal silicide, a conductive metal nitride, and a doped semiconductor material. The insulating patterns 120Ua, 120a and 120La may be provided in the spaced spaces between the gate patterns 157U, 157m, 157 and 157L. For example, the insulating patterns 120Ua, 120a and 120La may be an oxide film or a nitrided oxide film.

The channel structures 139 extending from the substrate 100 and passing through the gate patterns 157U, 157m, 157 and 157L and the insulating patterns 120Ua, 120a and 120La may be provided. The channel structures 139 may be provided in the first penetration areas 125 passing through the gate patterns 157U, 157m, 157 and 157L and the insulation patterns 120Ua, 120a and 120La.

The channel structures 139 may include a first region P1 including a first semiconductor layer 132 and a second region P2 including a second semiconductor layer 133. [ The first region may be an active region of the cell gate patterns 157m and 157 and the lower select gate pattern 157L and the second region P2 may be an active region of the upper select gate pattern 157U. Lt; / RTI > The second region P2 may be provided on the first region P1. A boundary between the first region P1 and the second region P2 may be provided between the upper select gate pattern 157U and the uppermost cell gate pattern 157m. The second region P2 may be adjacent to the upper select gate pattern 157U and the first region P1 may be adjacent to the cell gate patterns 157m and 157. [ That is, when the upper select gate pattern 157U is the gate electrode of the string select transistor, a part of the second region P2 may be a channel region of the string select transistor. If the cell gate patterns 157m and 157 are gate electrodes of the memory cell transistors, a part of the first region P1 may be a channel region of the memory cell transistors.

The grain size of the second region P2 may be greater than the grain size of the first region P1. For example, the crystal grains in the second region P2 may have a length in a direction (z direction) perpendicular to the substrate 100, in a direction parallel to the surface of the substrate 100 (x direction and y direction) Can be larger. As an example, the aspect ratio of the grains in the second region P2 may be about 2 to 100. For example, the length in the z direction of the crystal grains in the second region P2 may be greater than the thickness of the upper select gate pattern 157U. That is, the string selection transistor may have a channel region having a relatively larger grain size than the memory cell transistors. Therefore, the area of the grain boundary in the channel region of the string selection transistor can be reduced. Thereby, it is possible to improve the electrical characteristics of the semiconductor element such as the leakage current which can be generated by the grain boundaries.

The channel structures 139 may further include a buried pattern 156 surrounded by the first region P1. The bottom of the channel structures 139 may be formed in the semiconductor pattern 136 formed along the lower and inner sidewalls of the first through regions 125 by a macaroni filled with the embedding pattern 156. [ Or in the form of a shell. The embedded pattern 156 may be spaced apart from the substrate 100 by the semiconductor pattern 136. Alternatively, the top of the channel structures 139 may not include the embedding pattern 156. [ For example, an upper portion of the channel structures 139 may be a region filled with the semi-filled pattern 136 in the first through regions 125. Therefore, the string selection transistor can secure a relatively wide channel region as compared with the memory cell transistors.

An upper surface of the buried pattern 156 may be provided between the upper select gate pattern 157U and the uppermost cell gate pattern 157m. For example, the buried pattern 156 may include at least one of a silicon oxide film and a silicon oxynitride film. The semiconductor pattern 136 may include at least one of silicon of the first conductivity type or intrinsic state, or silicon-germanium.

The channel structures 139 arranged in the x-direction form one row, and the channel structures 139 arranged in the y-axis direction form one column. A plurality of rows and a plurality of columns may be arranged on the substrate 100. A device isolation pattern 175 may be disposed between a pair of adjacent columns. That is, the device isolation pattern 175 may extend in the y direction. The device isolation pattern 175 may include an insulating material. For example, the device isolation pattern 175 may be formed of a high-density plasma oxide film, an SOG film (Spin On Glass layer), a CVD oxide film, or the like. A first impurity region 170 may be formed in the substrate 100 under the device isolation pattern 175. As an example, the first impurity region 170 may be in the form of a line extended in the y direction. The first impurity region 170 may be a region doped with an impurity of the second conductivity type. The second conductive type may be a conductive type different from the first conductive type. An information storage layer 150 may be provided between the gate patterns 157U, 157m, 157, and 157L and the channel structures 139. FIG. The structure of the information storage layer 150 will be described in more detail with reference to FIGS. 25 and 26. FIG.

A second impurity region 198 may be provided on the semiconductor pattern 136 adjacent to the uppermost insulating pattern 120Ua. The second impurity region 198 may be an impurity region having the same conductivity type as that of the first impurity region 170. Bit lines BL extending in a direction (for example, x direction) intersecting with the gate patterns 157U, 157m, 157, and 157L and electrically connected to the second impurity region 198 are provided . The bit lines BL may be connected to the channel structures 139 via contact plugs 199. The bit lines BL may comprise at least one selected from a metal, a conductive metal nitride, or a doped semiconductor material.

According to the first embodiment of the present invention, the selection transistor may have a channel region having a relatively large grain size as compared with the memory cell transistors. Therefore, it is possible to alleviate the increase of the leakage current by the grain boundaries. In addition, the select transistor can secure a relatively large volume of channel region as compared with the memory cell transistors, thereby reducing the channel resistance.

FIGS. 4 to 14 are cross-sectional views and top view views illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

Referring to Fig. 4, a substrate 100 is prepared. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a compound semiconductor substrate. For example, the substrate 100 may be doped with an impurity of the first conductivity type.

A laminated structure in which the first material films and the second material films are alternately and repeatedly laminated on the substrate 100 may be provided. The second material layers may include a material different from the first material layers. For example, the first material layers may be sacrificial layers 110L, 110m, 110, and 110U. The second material films may be the insulating films 120L, 120, and 120U. The sacrificial layers 110L, 110m, 110, and 110U may be formed of a material having an etch selectivity with respect to the insulating layers 120L, 120, and 120U. For example, the insulating layers 120L, 120, and 120U may be formed of an oxide, and the sacrificial layers 110L, 110m, 110, and 110U may include a nitride and / or an oxide nitride.

The sacrificial layers 110L, 110m, 110, and 110U may have the same thickness. Alternatively, the upper select gate sacrificial layer 110U and the lower select gate sacrificial layer 110L may be formed between the upper select gate sacrificial layer 110U and the lower select gate sacrificial layer 110U, among the sacrificial layers 110L, 110m, 110, May be relatively thicker than the cell gate sacrificial films 110m and 110 between the films 110L. The upper select gate sacrificial layer 110U occupies a space where the upper select gate pattern is to be formed, and the cell gate sacrificial layers 110m and 110 occupy a space where cell gate patterns to be described below are to be formed . The cell gate sacrificial layers may include an uppermost cell gate sacrificial layer 110m and cell gate sacrificial layers 110 thereunder. The lower selection gate sacrificial layer 110L may occupy a space where the lower selection gate pattern is to be formed, which will be described below. The uppermost insulating film 120U among the insulating films 120L, 120, and 120U may be formed to be relatively thicker than the insulating films 120 and 120L thereunder.

A buffer insulating layer 105 may be formed on the substrate 100 before forming the sacrificial layers 110L, 110m, 110 and 110U and the insulating layers 120L, 120 and 120U. The sacrificial layers 110L, 110m, 110 and 110U and the insulating layers 120L, 120 and 120U may be formed on the buffer insulating layer 105. [ For example, the lower select gate sacrificial layer 110L may be formed directly on the buffer insulating layer 105. The buffer insulating layer 105 may be formed of a dielectric material having an etch selectivity with respect to the sacrificial layers 110L, 110m, 110, and 110U. For example, the buffer insulating layer 105 may be formed of an oxide, particularly, a thermal oxide.

The buffer insulating layer 105, the insulating layers 120L, 120U and 120 and the sacrificial layers 110U, 110m, 110 and 110L are continuously patterned to form first through regions 125 may be formed. The first through regions 125 may be formed using an anisotropic etching process. At the time of forming the first through regions 125, the top of the substrate 100 may be etched together as a result of over etch. The first through regions 125 may be two-dimensionally arranged on the substrate 100. The first through regions 125 may be circular, elliptical or polygonal in plan view.

Referring to FIG. 5, the first preliminary semiconductor layer 131 may be formed along the sidewalls and the bottom of the first through regions 125. The first preliminary semiconductor layer 131 may be a silicon layer. For example, the first preliminary semiconductor layer 131 may not completely fill the first through regions 125. A buried layer 155 filling the first through regions 125 may be formed on the first preliminary semiconductor layer 131. For example, the buried layer 155 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The first preliminary semiconductor layer 131 and the buried layer 155 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). In one embodiment, the formation of the first preliminary semiconductor layer 131 may include recrystallization by a first heat treatment process. If the semiconductor layer after the deposition is substantially amorphous, it may be a polycrystalline silicon film having a relatively small crystal grain size by the recrystallization. The first heat treatment process may be a solid phase crystallization process. After the first preliminary semiconductor layer 131 and the buried layer 155 are deposited, the uppermost insulating layer 120U may be exposed by a planarization process. Alternatively, the planarization process may not be performed.

Referring to FIGS. 6 to 8, an upper portion of the first preliminary semiconductor layer 131 is etched to form a first semiconductor layer 132. FIG. 7 is an enlarged view of the first semiconductor layer 132 in FIG. 6, and FIG. 8 is a top view of the first semiconductor layer 132. The upper surface of the first semiconductor layer 132 may be exposed by the second through regions 126. The etch process may be performed at a depth between the top surface of the topmost cell gate sacrificial layer 110m and the bottom surface of the top select gate sacrificial layer 110U. That is, the lower surface of the second through regions 126 may be disposed between the upper surface of the uppermost cell gate sacrificial layer 110m and the lower surface of the upper select gate sacrificial layer 110U.

The upper portion of the buried layer 155 may be etched to form the buried pattern 156. [ For example, the upper surface of the buried pattern 156 may be disposed between the upper surface of the uppermost cell gate sacrificial layer 110m and the lower surface of the upper select gate sacrificial layer 110U. The height of the upper surface of the buried pattern 156 may be equal to or higher than the height of the upper surface of the first semiconductor layer 132. The upper surface of the buried pattern 156 and the upper surface of the first semiconductor layer 132 may be the lower surface of the second through regions 126. Therefore, the upper surface of the first semiconductor layer 132 can expose a relatively small number of crystal grains by the second through regions 126 compared to the case where the buried pattern 156 is not present.

The second through regions 126 may be formed by various etching processes such as dry etching, wet etching, or a combination thereof. In one embodiment, the etching for the formation of the first semiconductor layer 132 and the buried pattern 156 may proceed at the same time. In this case, the etching process may proceed to a slightly different etch recipe with respect to the first semiconductor layer 132 and the buried pattern 156. As the etching process proceeds, a step may be generated between the upper surface of the first semiconductor layer 132 and the upper surface of the buried pattern 156 due to the etching rate difference.

In another embodiment, the etching process for forming the first semiconductor layer 132 and the buried pattern 156 may be performed, respectively. In another embodiment, the first preliminary semiconductor layer 131 and the buried layer 155 are etched together, and then one of the first preliminary semiconductor layer 131 and the buried layer 155 is further etched An additional process can be performed. At the time of etching the buried layer 155, the uppermost insulating layer 120U or a portion of the upper select gate sacrificial layer 110U may be etched together.

9 to 11, a second semiconductor layer 133 filling the second through regions 126 may be formed. FIG. 10 is an enlarged view of the first and second semiconductor layers 132 and 133 of FIG. 9, and FIG. 11 is a top view of the second semiconductor layer 133. The second semiconductor layer 133 may include at least one of silicon or silicon-germanium. The second semiconductor layer 133 is formed by an epitaxial growth process in which the upper surface of the first semiconductor layer 132 exposed by the second penetration regions 126 is seeded . That is, the epitaxial process can be performed using the seeds of the crystal grains forming the upper surface of the first semiconductor layer 132 as a seed. The first semiconductor layer 132 exposes a relatively small number of crystal grains as compared with the case where the buried pattern 156 is absent. Therefore, when the second semiconductor layer 133 is grown with the seeds of the first semiconductor layer 132 as seeds, the second semiconductor layer 133 may have a relatively small number of crystal grains Lt; / RTI > Each of the grains grown by seeding the first semiconductor layer 132 may be in contact with each other on the buried pattern 156 to form a crystal grain boundary. During the growth process, some of the crystal grains may be combined with each other, one crystal grain may be divided into a plurality of crystal grains, or growth may be maintained until the process is completed in only some of the seed crystal grains. May be formed in a number similar to the number of the seed crystal grains. The crystal grains constituting the second semiconductor layer 133 may have a shape elongated in a direction perpendicular to the upper surface of the substrate 100. The second semiconductor layer 133 may be formed to be higher than the upper surface of the uppermost insulating layer 120U and then be substantially the same height as the uppermost insulating layer 120U through a planarization process. The second semiconductor layer 133 may be intrinsic or may be doped with a first type impurity.

Referring to FIG. 12, the sacrificial films 110U, 110m, 110, and 110L may be removed. The removal process may include forming the first trench 140 by continuously patterning the insulating films 120U, 120, and 120L and the sacrificial films 110U, 110m, 110, and 110L. By the formation of the first trench 140, the insulating layers 120U, 120 and 120L can be separated into insulating patterns 120Ua, 120a and 102La, respectively. The formation of the first trench 140 may be performed by an anisotropic etching process. The sacrificial patterns 110La, 110m, 110a, and 110Ua exposed by the first trench 140 may be removed by the selective etching process to form the recess regions 145L, 145, and 145U. In the selective etching process, the etching rates of the sacrificial patterns 110La, 110m, 110a, and 110Ua are determined by etching the insulating patterns 120La, 120a, and 120Ua, the buffer insulating film 105, Rate. Accordingly, after the selective etching process, the insulating patterns 120La, 120a, and 120Ua, the buffer insulating layer 105, and the channel structures 139 may remain. The recess regions 145L, 145 and 145U may expose portions of the sidewalls of the channel structures 139 that are in contact with the sacrificial patterns 110La, 110m, 110a, and 110Ua, respectively.

Referring to FIG. 13, an information storage layer 150 may be formed on the resulting recessed regions 145L, 145, and 145U. The information storage layer 150 may be formed using a deposition technique (e.g., CVD or ALD) capable of providing excellent step coverage. Accordingly, the information storage layer 150 may be formed substantially conformally along the recessed regions 145L, 145, and 145U. The information storage layer 150 may fill a portion of the recessed regions 145L, 145, and 145U. The structure of the information storage layer 150 will be described in more detail with reference to FIGS. 25 and 26. FIG.

After the information storage layer 150 is formed, a gate conductive layer 158 filling the recessed regions 145L, 145, and 145U may be formed. The gate conductive layer 158 may fill at least a portion of the first trench 140. The gate conductive layer 158 may be electrically separated from the channel structures 139 and the substrate 100 by the data storage layer 150. The gate conductive layer 158 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer chemical vapor deposition (ALD). The gate conductive layer 158 may include at least one selected from a metal, a metal silicide, a conductive metal nitride, and a doped semiconductor material.

14, after forming the gate conductive layer 158, a part of the gate conductive layer 158 located outside the recess regions 145L, 145, and 145U is removed, Gate electrodes 157L, 157m, 157, and 157U are formed in the gate lines 145L, 145, and 145U. The gate conductive layer 158 located outside the recessed regions 145L, 145, and 145U may be removed by a wet etch and / or dry etch process. As a result, the second trench 141 can be formed.

The lowermost pattern among the gate electrodes may be the lower select gate pattern 157L and the uppermost pattern may be the upper select gate pattern 157U. Cell gate patterns 157m and 157 may be provided between the lower selection gate pattern 157L and the upper selection gate pattern 157U. The cell gate patterns may include an uppermost cell gate pattern 157m and cell gate patterns 157 below the uppermost cell gate pattern 157m.

A first impurity region 170 may be formed in the substrate 100 under the bottom surface of the second trench 141. The first impurity region 170 may extend along the second trench 141. The first impurity region 170 may be formed by implanting impurity ions of the second conductivity type. The uppermost insulating pattern 120Ua may be used as an ion implantation mask.

A second impurity region 198 may be formed on the channel structures 139. The second impurity region 198 may be an impurity doped region of the second conductivity type. The lower surface of the second impurity region 198 may be higher than the upper surface of the upper select gate pattern 157U. The second impurity region 198 may be formed simultaneously with the first impurity region 170. Alternatively, the second impurity region 198 may be formed before the first impurity region 170 is formed. In this case, the second impurity region 198 may be formed after forming the channel structures 139 and before forming the second trench 141. Alternatively, the second impurity region 198 may be formed after the first impurity region 170 is formed.

A device isolation pattern 175 filling the second trenches 141 may be formed. The device isolation pattern 175 may be formed by forming an isolation layer filling the second trench 141 on the substrate 100 and forming the isolation layer on the uppermost insulation layer 120Ua. Lt; RTI ID = 0.0 > planarization < / RTI > process with an etch stop film. The device isolation pattern 175 may include an insulating material. For example, the device isolation pattern 175 may be formed of a high-density plasma oxide film, an SOG film (Spin On Glass layer), a CVD oxide film, or the like. After the element isolation pattern 175 is formed, the exposed uppermost insulating layer 120Ua may be exposed by etching the exposed information storage layer 150. FIG. In this case, the second impurity region 198 may be exposed together.

Referring again to FIG. 2, bit lines BL which are electrically connected to the second impurity region 198 may be formed. The bit lines BL may extend in the x direction. An interlayer insulating film (not shown) may be formed to cover the uppermost insulating pattern 120Ua and the device isolation pattern 175, and the bit lines BL may be formed on the interlayer insulating film. The bit lines BL may be electrically connected to the second impurity region 198 via contact plugs 199 penetrating the interlayer insulating film. The contact plugs 199 may include at least one of a metal, a conductive metal nitride, or a doped semiconductor material.

15 and 16, a semiconductor device according to a second embodiment of the present invention is described. FIG. 15 is a perspective view of a semiconductor device according to a second embodiment of the present invention, and FIG. 16 is an enlarged view of the channel structure of FIG. Some structures and forming methods of this embodiment are similar to those of the first embodiment. Thus, for brevity's sake, a description of overlapping technical features may be omitted below.

Referring to Figs. 15 and 16, a laminated structure is provided on a substrate 100. Fig. The stacked structure may include gate patterns and insulating patterns which are alternately stacked on the substrate 100 repeatedly. The gate patterns may include a lower select gate pattern 157L, cell gate patterns 157m and 157, and an upper select gate pattern 157U. The cell gate patterns may include an uppermost cell gate pattern 157m and cell gate patterns 157 below the uppermost cell gate pattern 157m. A buffer insulating layer 105 may be provided between the substrate 100 and the lower selection gate pattern 157L. The insulating patterns may include an uppermost insulating pattern 120Ua, a lowermost insulating pattern 120La and intermediate insulating patterns 120a between the uppermost insulating pattern 120Ua and the lowest insulating pattern 120La.

The channel structures 139 extending from the substrate 100 and passing through the gate patterns 157U, 157m, 157 and 157L and the insulating patterns 120Ua, 120a and 120La may be provided. The channel structures 139 may be provided in the first penetration areas 125 passing through the gate patterns 157U, 157m, 157 and 157L and the insulation patterns 120Ua, 120a and 120La.

The channel structures 139 may include a first region P1 including a first semiconductor layer 132 and a third region P3 including a second semiconductor layer 133. [ The first region may be an active region of the cell gate patterns 157m and 157 and the lower select gate pattern 157L and the third region P3 may be an active region of the upper select gate pattern 157U, Lt; / RTI > The third region P3 may be provided on the first region P1. A boundary between the first region P1 and the third region P3 may be provided between the upper select gate pattern 157U and the uppermost cell gate pattern 157m. The first and second semiconductor layers 132 and 133 may form part of the semiconductor pattern 136. The third region P3 may be adjacent to the upper select gate pattern 157U and the first region P1 may be adjacent to the cell gate patterns 157m and 157. [ That is, when the upper select gate pattern 157U is the gate electrode of the string select transistor, a part of the third region P3 may be a channel region of the string select transistor. If the cell gate patterns 157m and 157 are gate electrodes of the memory cell transistor, a part of the first region P1 may be a channel region of the memory cell transistor.

The grain size in the third region P3 may be greater than the grain size in the first region P1. For example, the crystal grains in the third region P3 may be arranged in a direction (z direction) perpendicular to the substrate 100 in a direction parallel to the surface of the substrate 100 (x direction or y direction) The length may be larger. For example, the aspect ratio of the grains in the third region P3 may be about 2-100. For example, the length in the z direction of the crystal grains in the third region P3 may be greater than the thickness of the upper select gate pattern 157U. That is, the string selection transistor may have a channel region having a relatively larger grain size than the memory cell transistors. Therefore, the area of the grain boundary in the channel region of the string selection transistor can be reduced. Thereby, it is possible to improve the electrical characteristics of the semiconductor element such as the leakage current which can be generated by the grain boundaries.

The channel structures 139 may further include a buried pattern 156 surrounded by the semiconductor pattern 136. For example, the semiconductor pattern 136 may be provided along the lower and inner sidewalls of the first through regions 125, and the buried pattern 156 may be filled in the semiconductor pattern 136. The embedded pattern 156 may be spaced apart from the substrate 100 by the semiconductor pattern 136. The upper surface of the buried pattern 156 may be higher than the upper surface of the upper select gate pattern 157U.

A device isolation pattern 175 extending between the channel structures 139 may be provided. A first impurity region 170 may be formed in the substrate 100 under the device isolation pattern 175. The first impurity region 170 may be in the form of a line extended in the y direction. The first impurity region 170 may be a region doped with a second conductive impurity. The second conductive type may be a conductive type different from the first conductive type.

The first and second information storage layers DA1 and DA2 may be provided between the gate patterns 157U, 157m, 157 and 157L and the channel structures 139. [ The first information storage layer DA1 may extend vertically along the sidewalls of the first through regions 125. The second data storage layer DA2 may extend along the top, bottom, and sidewalls of the gate patterns 157U, 157m, 157, and 157L. The structure of the data storage layers DA1 and DA2 will be described in more detail with reference to FIGS. 25 and 26. FIG.

A second impurity region 198 may be provided on the semiconductor pattern 136 adjacent to the uppermost insulating pattern 120Ua. The second impurity region 198 may be an impurity region having the same conductivity type as that of the first impurity region 170. Bit lines BL extending in a direction (for example, x direction) intersecting with the gate patterns 157U, 157m, 157, and 157L and electrically connected to the second impurity region 198 are provided . The bit lines BL may be connected to the channel structures 139 via contact plugs 199. The bit lines BL may include at least one selected from a metal, a conductive metal nitride, or a semiconductor material.

17 to 24 are cross-sectional views and a top view of the semiconductor device according to the second embodiment of the present invention.

Referring to Fig. 17, a laminated structure in which first material films and second material films are alternately and repeatedly laminated on a substrate 100 may be provided. The first material layers may be the sacrificial layers 110L, 110m, 110, and 110U. The second material films may be the insulating films 120L, 120, and 120U. The sacrificial layers may include an upper select gate sacrificial layer 110U, cell gate sacrificial layers 110m, 110, and a lower select gate sacrificial layer 110L. A buffer insulating layer 105 may be formed on the substrate 100 before forming the sacrificial layers 110L, 110m, 110 and 110U and the insulating layers 120L, 120 and 120U.

The buffer insulating layer 105, the insulating layers 120L, 120U and 120 and the sacrificial layers 110U, 110m, 110 and 110L are continuously patterned to form first through regions 125 may be formed. The first through regions 125 may be formed using an anisotropic etching process. The first through regions 125 may be two-dimensionally arranged along the x and y directions. The first through regions 125 may be circular, elliptical or polygonal in plan view.

The first information storage layer DA1 may be formed along the sidewalls and the bottom surface of the first through regions 125. [ The first information storage layer DA1 may include at least one insulating layer. The specific configuration of the first information storage film DA1 will be described in more detail below with reference to FIGS. 25 and 26. FIG.

Referring to FIG. 18, a first preliminary semiconductor layer 131 and a buried layer 155 may be sequentially formed in the first through regions 125. The first preliminary semiconductor layer 131 may be formed on the first data storage layer DA1. Before forming the first preliminary semiconductor layer 131, the bottom of the first data storage layer DA 1 may be etched to expose the substrate 100. Therefore, the first preliminary semiconductor layer 131 may be electrically connected to the substrate 100. The first information storage layer DA1 may be etched by forming a spacer (not shown) exposing a lower portion of the first information storage layer DA1 on the sidewall of the first through regions 125, The spacer may be performed as an etch mask. The spacer may comprise a silicon material. The spacer may form a part of the first preliminary semiconductor layer 131 without being removed or removed after the etching process. The formation of the first preliminary semiconductor layer 131 may include a recrystallization process by a first heat treatment process. The first preliminary semiconductor layer 131 may be a polysilicon film having a relatively small grain size by the recrystallization process. For example, the first heat treatment process may be a solid phase crystallization process. After the first preliminary semiconductor layer 131 and the buried layer 155 are deposited, the uppermost insulating layer 120U may be exposed by a planarization process. Alternatively, the planarization process may not be performed.

19 to 21, an upper portion of the first preliminary semiconductor layer 131 is etched to form a first semiconductor layer 132. FIG. 20 is an enlarged view of the first semiconductor layer 132 in FIG. 19, and FIG. 21 is a top view of the first semiconductor layer 132. The first semiconductor layer 132 may have a top surface exposed by the second through regions 126. The etch process may be performed at a depth between the top surface of the topmost cell gate sacrificial film 110m and the bottom surface of the top select gate sacrificial film 110U. That is, the lower surface of the second through regions 126 may be disposed between the upper surface of the uppermost cell gate sacrificial layer 110m and the lower surface of the upper select gate sacrificial layer 110U.

The upper portion of the buried layer 155 may be etched to form the buried pattern 156. [ For example, the upper surface of the buried pattern 156 may be higher than the upper surface of the upper select gate sacrificial layer 110U and lower than the upper surface of the uppermost insulating layer 120U. At the time of etching the buried layer 155, the upper portion of the first information storage layer DA1 may be etched together. Alternatively, the upper portion of the first information storage film DA1 may not be etched.

The upper surface of the first semiconductor layer 132 may be the lower surface of the second through regions 126. Therefore, the upper surface of the first semiconductor layer 132 may expose a relatively small number of crystal grains in the second through regions 126 compared to the case where the buried pattern 156 is not present.

The second through regions 126 may be formed by various etching processes such as dry etching, wet etching, or a combination thereof. In one embodiment, the etching for the formation of the first semiconductor layer 132 and the buried pattern 156 may proceed at the same time. In this case, the etching process may be performed with an etch recipe having a relatively high etch rate with respect to the first semiconductor layer 132. In another embodiment, the etching process for forming the first semiconductor layer 132 and the buried pattern 156 may be performed, respectively. In another embodiment, the buried pattern 156 may be formed after the formation of the second semiconductor layer 133, which will be described below.

Referring to FIGS. 22 and 23, a second semiconductor layer 133 filling the second through regions 126 may be formed. 22 is an enlarged view of the first and second semiconductor layers 132 and 133 of FIG. The top view of the second semiconductor layer 133 may be substantially the same as that of FIG. The second semiconductor layer 133 may include at least one of silicon or silicon-germanium. The second semiconductor layer 133 is formed through an epitaxial growth process in which the first semiconductor layer 132 exposed by the second penetration regions 126 is seeded . That is, the epitaxial process can be performed using the seeds of the crystal grains forming the upper surface of the first semiconductor layer 132 as a seed. The first semiconductor layer 132 exposes a relatively small number of crystal grains as compared with the case where the buried pattern 156 is absent. Therefore, when the second semiconductor layer 133 is grown with the seeds of the first semiconductor layer 132 as seeds, the second semiconductor layer 133 may have a relatively small number of crystal grains Lt; / RTI > Each of the grains grown by seeding the first semiconductor layer 132 may be in contact with each other on the buried pattern 156 to form a crystal grain boundary. During the growth process, some of the crystal grains may be combined with each other, one crystal grain may be divided into a plurality of crystal grains, or growth may be maintained until the process is completed in only some of the seed crystal grains. May be formed in a number similar to the number of the seed crystal grains. The crystal grains constituting the second semiconductor layer 133 may have a shape elongated in a direction perpendicular to the upper surface of the substrate 100. The second semiconductor layer 133 may be formed to be higher than the upper surface of the uppermost insulating layer 120U and then be substantially the same height as the uppermost insulating layer 120U through a planarization process. The second semiconductor layer 133 may be intrinsic or may be doped with a first type impurity.

Referring to FIG. 24, after the sacrificial films 110U, 110m, 110, and 110L are removed to form recessed regions (not shown), the second information storage film DA2 and the gate Electrodes 157L, 157m, 157, and 157U are formed. The lowermost pattern among the gate electrodes may be the lower select gate pattern 157L and the uppermost pattern may be the upper select gate pattern 157U. Cell gate patterns 157m and 157 may be provided between the lower selection gate pattern 157L and the upper selection gate pattern 157U. The cell gate patterns may include an uppermost cell gate pattern 157m and cell gate patterns 157 below the uppermost cell gate pattern 157m.

The first impurity region 170 may be formed in the substrate 100 under the bottom surface of the second trench 141. The first impurity region 170 may be formed by implanting dopant ions of the second type. A second impurity region 198 may be formed on the channel structures 139. The second impurity region 198 may be a region doped with the second type dopant. The lower surface of the second impurity region 198 may be higher than the upper surface of the upper select gate pattern 157U. For example, the second impurity region 198 may be formed simultaneously with the first impurity region 170. A device isolation pattern 175 filling the second trenches 141 may be formed.

Referring again to FIG. 15, bit lines BL which are electrically connected to the second impurity region 198 may be formed. The bit lines BL may extend in the x direction. The bit lines BL may be electrically connected to the second impurity region 198 via contact plugs 199 penetrating an interlayer insulating film (not shown). The contact plugs 199 may include at least one of a metal, a conductive metal nitride, or a doped semiconductor material.

25 and 26 are perspective views illustrating a structure of an information storage layer according to embodiments of the present invention.

25 is a perspective view illustrating an information storage layer 150 according to embodiments of the present invention. More specifically, the information storage film 150 of FIG. 25 may be the information storage film shown in the first embodiment of the present invention.

A buried pattern DP and a semiconductor pattern SP may be provided in the first penetration regions 125 and an information storage layer 150 may be provided on a sidewall of the semiconductor pattern SP. The information storage layer 150 may include a tunnel insulating layer TIL, a charge storage layer CL, and a blocking insulating layer BLL, which are sequentially stacked in the recessed regions 145. The films constituting the information storage film 150 may be formed using a deposition technique (for example, a chemical vapor deposition or atomic layer deposition technique) capable of providing excellent step coverage.

The charge storage film (CL) may be one of insulating films comprising trapping sites rich in insulating films and nanoparticles, and may be formed using one of chemical vapor deposition or atomic layer deposition techniques. For example, the charge storage film CL may include one of a trap insulating film, a floating gate electrode, or an insulating film including conductive nano dots. For example, the charge storage layer CL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a laminated trap layer . ≪ / RTI >

The tunnel insulating film TIL may be one of materials having a larger bandgap than the charge storage film CL and may be formed using one of chemical vapor deposition or atomic layer deposition techniques. For example, the tunnel insulating film TIL may be a silicon oxide film formed using one of the deposition techniques described above. In addition, a predetermined heat treatment step after the deposition process may be further performed on the tunnel insulating film TIL. The heat treatment step may be an annealing process performed in an atmosphere containing Rapid Thermal Nitridation (RTN) or at least one of nitrogen and oxygen.

The blocking insulating film BLL may be a single insulating film. Alternatively, the blocking insulating layer BLL may include first and second blocking insulating layers (not shown). The first and second blocking insulating films may be formed of different materials, and one of the first and second blocking insulating films may have a band gap smaller than the tunnel insulating film TIL and larger than the charge storage film CL Lt; / RTI > In addition, the first and second blocking insulating films may be formed using one of chemical vapor deposition or atomic layer deposition techniques, at least one of which may be formed through a wet oxidation process. According to one embodiment, the first blocking insulating layer is one of high-k films such as an aluminum oxide layer and a hafnium oxide layer, and the second blocking insulating layer may be a material having a lower dielectric constant than the first blocking insulating layer. According to another embodiment, the second blocking insulating film is one of the high-k films, and the first blocking insulating film may be a material having a smaller dielectric constant than the second blocking insulating film.

26 is a perspective view showing a structure of an information storage film according to another embodiment of the present invention. More specifically, the information storage layers DA1 and DA2 in FIG. 26 may be the information storage layers shown in the second embodiment of the present invention. The information storage layer according to this embodiment may include a first information storage layer DA1 and a second information storage layer DA2. The first information storage layer DA1 may be formed in the first through regions 125 and may extend along the sidewalls of the first through regions 125. [ The second information storage layer DA2 may be formed in the recessed regions 145. [ The first and second information storage layers DA1 and DA2 may include at least one of the blocking insulating layer BLL, the charge storage layer CL, and the tunnel insulating layer TIL.

27 is a schematic block diagram showing an example of a memory system including a semiconductor memory device manufactured according to the manufacturing method of the embodiments of the present invention.

27, the memory system 1100 may be a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, A memory card, or any device capable of transmitting and / or receiving information in a wireless environment.

The memory system 1100 includes an input / output device 1120 such as a controller 1110, a keypad, a keyboard and a display, a memory 1130, an interface 1140, and a bus 1150. Memory 1130 and interface 1140 are in communication with one another via bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other similar process device. Memory 1130 may be used to store instructions executed by the controller. The input / output device 1120 may receive data or signals from outside the memory system 1100, or may output data or signals to the outside of the memory system 1100. For example, the input / output device 1120 may include a keyboard, a keypad, or a display device.

Memory 1130 includes a non-volatile memory device in accordance with embodiments of the present invention. Memory 1130 may also include other types of memory, volatile memory that may be accessed at any time, and various other types of memory. The interface 1140 serves to transmit data to and receive data from the communication network.

28 is a schematic block diagram showing an example of a memory card having a semiconductor memory device manufactured according to the manufacturing method of the embodiments of the present invention.

Referring to FIG. 28, a memory card 1200 for supporting a high capacity data storage capability may be equipped with a flash memory device 1210 according to embodiments of the present invention. The memory card 1200 according to embodiments of the present invention includes a memory controller 1220 that controls exchange of data between a host and a flash memory device 1210. [

The SRAM 1221 is used as the operating memory of the processing unit 1222. The host interface 1223 has a data exchange protocol of a host connected to the memory card 1200. Error correction block 1224 detects and corrects errors contained in data read from multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs all control operations for data exchange of the memory controller 1220. Although it is not shown in the drawing, the memory card 1200 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned.

29 is a schematic block diagram showing an example of an information processing system for mounting a semiconductor memory device manufactured according to the manufacturing method of the embodiments of the present invention.

29, the memory system 1310 of the present invention is mounted in an information processing system such as a mobile device or a desktop computer. An information processing system 1300 according to the present invention includes a memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350, which are each electrically connected to the system bus 1360 . The memory system 1310 may be configured substantially the same as the memory system or memory system described above. The memory system 1310 stores data processed by the central processing unit 1330 or externally input data. The memory system 1310 described above may be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 may store a large amount of data reliably in the memory system 1310. As the reliability increases, the memory system 1310 can save resources required for error correction and provide a high-speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention can be provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. It is clear to those who have learned.

Further, the flash memory device or memory system according to the present invention can be mounted in various types of packages. For example, the flash memory device or the memory system according to the present invention may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

100: substrate 105: buffer insulating film
110: sacrificial film 120: insulating film
139: Channel structure 157: Gate patterns
156: buried pattern 175: device isolation pattern

Claims (10)

delete delete delete delete Laminating the first and second material layers alternately and repeatedly on the substrate;
Patterning the first and second material layers to form a first pass-through region exposing the substrate;
Forming a first semiconductor layer and a buried film in the first penetration region in order;
Etching a portion of the first semiconductor layer to form a second through region;
Forming a second semiconductor layer in the second through region; And
And replacing the second material film with gate electrodes,
Wherein the second semiconductor layer is formed by an epitaxial process in which the first semiconductor layer exposed by the second through region is a seed,
Wherein a grain size of the second semiconductor layer is larger than a grain size of the first semiconductor layer in a direction perpendicular to an upper surface of the substrate,
Wherein the gate electrodes comprise cell gate patterns and a select gate pattern on the cell gate patterns,
Wherein the etching of the first semiconductor layer is performed at a depth between the uppermost one of the cell gate patterns and the selected gate pattern. delete delete delete 6. The method of claim 5,
Forming the second through region further comprises etching an upper portion of the buried film,
Wherein the upper surface of the etched buried layer is lower than the lower surface of the select gate pattern. 6. The method of claim 5,
Forming the second through region further comprises etching an upper portion of the buried film,
Wherein the etching process of the buried film is performed at a depth higher than the top surface of the select gate pattern.

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