KR20120117612A - Flash memory device and memory system including the same - Google Patents

Abstract

PURPOSE: A flash memory device and a memory system including the same are provided to de-randomize the randomized data and randomize data to be programmed by applying seeds allocated in a page to access requested segments. CONSTITUTION: A page buffer circuit(400) reads or writes data from or in the selected page of a memory cell array. A randomizing and de-randomizing circuit(600) randomizes and de-randomizes data transmitted from the page buffer circuit based on a seed allocated in the selected page. The selected page is composed of a plurality of segments.

Description

Flash memory device and memory system including the same {FLASH MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME}

The present invention relates to a semiconductor memory device, and more particularly to a flash memory device.

A flash memory device is a kind of EEPROM in which a plurality of memory areas are erased or programmed in one program operation. A typical EEPROM allows only one memory area to be erased or programmable at a time, which allows a flash memory device to operate at a faster and more efficient speed than systems using flash memory devices can simultaneously read and write to other memory areas. It means that there is. All forms of flash memory and EEPROM are worn out after a certain number of erase operations due to degradation of the charge storage means used to store the data or wear of the insulating film surrounding the charge storage means.

A flash memory device stores information on a silicon chip in a manner that does not require power to maintain information stored on the silicon chip. This means that if the power to the chip is cut off, the information is maintained without consuming power. In addition, flash memory devices provide physical shock resistance and fast read access times. Because of these features, flash memory devices are commonly used as storage devices for devices powered by batteries.

An object of the present invention is to provide a flash memory device and a memory system including the same that can improve the reliability.

According to an exemplary embodiment of the present invention, there is provided an apparatus configured to randomize or de-randomize data to be transmitted. Such an apparatus would be configured such that the seed allocated to the memory space is repeatedly applied to the access requested segments of the memory space.

According to exemplary embodiments of the present invention, it is possible to de-randomize the randomized data and randomize the data to be programmed by applying the seed assigned to the page to each of the requested segments of the page.

1 is a block diagram schematically illustrating a flash memory device according to an exemplary embodiment of the present invention.
2A is a diagram for describing a randomization unit of a flash memory device according to an exemplary embodiment of the present invention.
FIG. 2B is a diagram illustrating an example of the segment illustrated in FIG. 2A.
FIG. 3 is a block diagram illustrating the randomization and de-randomization circuit shown in FIG. 1 in accordance with an exemplary embodiment of the present invention.
4 is a block diagram illustrating a pseudo-random sequence generator shown in FIG. 3 in accordance with an exemplary embodiment of the present invention.
5A is a block diagram illustrating the seed initializer illustrated in FIG. 3 according to an exemplary embodiment of the present invention.
5B and 5C are timing diagrams schematically illustrating a segment size setting method according to an exemplary embodiment of the present invention.
6A and 6B are timing diagrams for describing an operation of a randomization and de-randomization circuit according to an exemplary embodiment of the present invention.
7A and 7B are timing diagrams for explaining read and write operations of a flash memory device according to an exemplary embodiment of the present invention.
8 is a flowchart for describing a method of operating a flash memory device according to an exemplary embodiment of the present invention.
9A and 9B are diagrams for schematically describing a randomization region determined by setting of a randomization on / off function.
10 is a block diagram schematically illustrating a flash memory device according to another exemplary embodiment of the present invention.
11A is a block diagram schematically illustrating a flash memory device according to another embodiment of the present invention.
11B is a block diagram schematically illustrating a flash memory device according to another embodiment of the present invention.
FIG. 12 is a flowchart for describing an operation of a flash memory device having a randomization on / off function described with reference to FIGS. 10 and 11A.
FIG. 13 is a diagram illustrating an example of configuring the memory cell array shown in FIG. 1 into memory blocks for an all-bit line memory structure or an odd-even memory structure.
14 is a diagram illustrating a memory cell array according to another exemplary embodiment of the present invention.
FIG. 15 is a perspective view illustrating a portion of one of the memory blocks BLK1 to BLKz illustrated in FIG. 14 according to an embodiment of the present invention.
FIG. 16 is a cross-sectional view of the memory block shown in FIG. 15 taken along line II ′.
17 is a circuit diagram illustrating an equivalent circuit of the memory block illustrated in FIG. 16 in accordance with an exemplary embodiment of the present invention.
18A is a block diagram schematically illustrating a memory system according to an exemplary embodiment of the present invention.
18B is a block diagram schematically illustrating a memory system according to another exemplary embodiment of the present invention.
19 is a block diagram schematically illustrating a memory system according to another exemplary embodiment of the present invention.
20 is a block diagram schematically illustrating a semiconductor drive according to an exemplary embodiment of the present invention.
21 is a block diagram schematically illustrating a semiconductor drive according to another exemplary embodiment of the present invention.
FIG. 22 is a block diagram schematically illustrating storage using the semiconductor drive illustrated in FIG. 20 or 21.
FIG. 23 is a block diagram schematically illustrating a storage server using the semiconductor drive illustrated in FIG. 20 or 21.
24 to 26 are diagrams schematically showing systems according to exemplary embodiments of the present invention.
27 to 31 are schematic views illustrating other systems to which a nonvolatile memory device according to exemplary embodiments of the present invention is applied.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. In addition, parts denoted by the same reference numerals throughout the specification represent the same components.

The expression " and / or " is used herein to mean including at least one of the elements listed before and after. In addition, the expression “connected / combined” is used to include directly connected to or indirectly connected to other components. In this specification, the singular forms also include the plural unless specifically stated otherwise in the phrases. Also, as used herein, components, steps, operations, and elements referred to as "comprising" or "comprising" refer to the presence or addition of one or more other components, steps, operations, elements, and devices.

Exemplary embodiments will now be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the flash memory device is, for example, a NAND flash memory device. However, it will be appreciated that the present invention is not limited to flash memory devices. For example, the present invention provides a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric memory (FRAM), a resistance change memory (Resistance Random Access). Memory (RRAM), spin transfer torque random access memory (STT-RAM), and the like.

The flash memory device includes a memory cell array 100 having memory cells arranged in rows (word lines: WL) and columns (bit lines: BL). Each memory cell stores 1-bit data or M-bit (multi-bit) data, where M is an integer of 2 or greater. When each memory cell stores 1-bit data, memory cells belonging to each row of the memory cell array 100 may constitute a memory space. When each memory cell stores M-bit data, memory cells belonging to each row of the memory cell array 100 may configure memory spaces corresponding to a plurality of pages, respectively. Each memory cell may be implemented as a memory cell having a charge storage layer, such as a floating gate or a charge trap layer, or a memory cell having a variable resistance element. The memory cell array 100 may be a single-layer array structure (or referred to as a two-dimensional array structure) or a multi-layer array structure (or a vertical or stacked three-dimensional array structure). Will be implemented).

The row select circuit 200 is controlled by the control logic 300 and is configured to perform select and drive operations on the rows of the memory cell array 100. The control logic 300 is configured to control the overall operation of the flash memory device. The page buffer circuit 400 is controlled by the control logic 300 and operates as a sense amplifier or as a write driver depending on the operation mode. For example, during a read operation, page buffer circuit 400 operates as a sense amplifier that senses data from memory cells of a selected row. During the program operation, the page buffer circuit 400 operates as a write driver for driving the memory cells of the selected row in accordance with the program data. The page buffer circuit 400 includes page buffers corresponding to bit lines or to bit line pairs, respectively. If each of the memory cells stores multi-bit data, each page buffer of the page buffer circuit 400 will be configured to have two or more latches.

1, the column select circuit 500 is controlled by the control logic 300 and sequentially selects columns (or page buffers) according to a predetermined unit during a read / program operation. The randomization and de-randomization circuit 600 is controlled by the control logic 300 and is configured to randomize the data (i.e., data to be programmed or original data) passed through the input / output interface 700. The randomization and de-randomization circuit 600 is configured to de-randomize the data (ie, randomized data) of the page buffer circuit 400 delivered through the column selection circuit 500. The randomization and de-randomization circuit 600 according to an exemplary embodiment of the present invention may include not only full-page data but also quantitatively less random data (eg, data in a spare area, sector data, And randomize and de-randomize operations on data larger than sector data and smaller than page data, etc.). This will be explained in detail later.

The memory cell has either of 2 ^N threshold voltage distributions (N represents the number of data bits stored in the memory cell) depending on the amount of charges stored in the charge storage means. The threshold voltage (or threshold voltage distribution) of a memory cell will change due to coupling occurring between adjacent memory cells (called word line coupling). According to the data randomization of the present invention, it is possible to reduce the change in the threshold voltages of the memory cells caused by the word line coupling. In other words, since the states of the memory cells are uniformly distributed, the degree of word line coupling occurring between the memory cells will be relatively relaxed compared to before data randomization. That is, the change of the threshold voltages of the memory cells will be suppressed. This means an increase in read margin, that is, an increase in reliability.

In some embodiments, randomization and de-randomization operations may be performed selectively. For example, when access to specific data or access to a specific area is requested, the randomization and de-randomization circuit 600 may be configured not to perform randomization and de-randomization operations. The randomization and de-randomization circuit 600 may be configured to transfer data input through the input / output interface 700 to the page buffer circuit 400 without performing a randomization operation. Thereafter, randomization of the data loaded into the page buffer circuit 400 may be performed through the randomization and de-randomization circuit 600 under the control of the control logic 300.

FIG. 2A is a diagram illustrating a randomization unit of a flash memory device according to an exemplary embodiment of the present invention, and FIG. 2B is a diagram illustrating an example of a segment illustrated in FIG. 2A.

The flash memory device may be provided with a plurality of memory spaces. For convenience of explanation, only one memory space is shown in FIG. 2A. The memory space may correspond to one page, for example. The memory space, or page, is composed of segments having a size L (or called a length) defined by the user. The segment size L will be determined according to the size of the program data and the ECC data, for example. The segment will include program data to be stored in the memory space of the flash memory device, as shown in FIG. 2B. The segment will also include ECC parity generated based on the program data. Thus, one segment will contain program data and ECC parity. The segment size L will be determined according to the size of the program data, for example. Random read and write operations to the flash memory device may be performed based on program data (or segments). The size of the program data may be variously determined according to the definition of the user. In addition, the size of the ECC may also be variously determined according to the definition of the user. Therefore, the segment size L will vary depending on the application to which the flash memory device is applied. That is, the segment size L may vary according to the definition of the user.

According to an embodiment of the present invention, one seed is allocated to one page for data randomization / de-randomization. In addition, data randomization is not performed based on pages, but data randomization / de-randomization is performed based on segments. In this case, the seed assigned to one page will be applied repeatedly to each segment regardless of random access and sequential access. In other words, as shown in Fig. 2A, seed initialization is performed for each segment. According to seed initialization, the data of each segment will be randomized / de-randomized based on a random sequence generated according to the seed assigned to the corresponding page. That is, the seed assigned to one page will be repeatedly applied to each segment. The technique in which the seed assigned to one page is repeatedly applied to each segment will be described in detail later.

In an exemplary embodiment, the term sector may be used in place of the term segment having a size determined according to the definition of the user. However, it will be appreciated that data having a size determined according to a user's definition may be defined in various terms. The term 'segment' will also be used to indicate a data unit consisting of program data and ECC.

FIG. 3 is a block diagram illustrating the randomization and de-randomization circuit shown in FIG. 1 in accordance with an exemplary embodiment of the present invention.

Referring to FIG. 3, the randomization and de-randomization circuit 600 includes a seed table 610, a seed initializer 620, a pseudo-random sequence generator 630, and a mixer ( 640). The seed table 610 will be configured to store the seeds assigned to the rows (or pages), respectively. Seeds of the seed table 610 are selected by the address (eg, page address) of the page (or row) requested for access, and the selected seed will be loaded into the pseudo-random sequence generator 630. The operation in which the selected seed is loaded into the pseudo-random sequence generator 630 is referred to as a "seed initialization operation". The pseudo-random sequence generator 630 will be initialized with the selected seed of the seed table 610 through a seed initialization operation. The seed initializer 620 may generate an initialization signal INIT for initializing the pseudo-random sequence generator 630 to the selected seed. An initialization signal INIT will be generated upon access request and prior to randomization / de-randomization of each segment. The operation of generating the initialization signal INIT will be described in detail later. The initialization signal INIT will be generated, for example, in the form of a pulse. The pseudo-random sequence generator 630 is initialized with the seed provided from the seed table 610 in response to the initialization signal INIT and sequentially generates random sequence data RSD after the seed initialization operation. The random sequence data RSD will be provided to the mixer 640. A group of random sequence data (RSD) sequentially provided to the mixer 640 will constitute a random sequence. Here, the random sequence data RSD may be 1-bit data. However, it will be understood that the number of bits of random sequence data (RSD) is not limited to that disclosed herein. For example, random sequence data (RSD) with multi-states can be used. At this time, the value representing each multi-state is defined as one symbol, and the original symbol value is logically combined with random sequence symbol data to improve randomness among all symbol values.

The mixer 640 logically combines random sequence data (RSD) and transmission data (or data input to the random sequence data (RSD) and the mixer 640), as randomized / de-randomized data. Will output the combined data. For example, during a read operation, the mixer 640 logically combines randomized data and random sequence data (RSD) provided through the column selection circuit 500 shown in FIG. 1 and de-randomized. The combined data as data will be output to the input / output interface 700. During the write operation, the mixer 640 logically combines the data provided through the input / output interface 700 and the random sequence data RSD, and outputs the combined data as the randomized data to the column selection circuit 500. will be. When byte data is provided to the mixer 640, the random sequence data bits will be logically combined with the data bits to be read / programmed, respectively.

In an exemplary embodiment, the mixer 640 will be configured with XOR logic, for example. However, it will be understood that the configuration of the mixer 640 is not limited to that disclosed herein.

4 is a block diagram illustrating a pseudo-random sequence generator shown in FIG. 3 in accordance with an exemplary embodiment of the present invention.

Referring to FIG. 4, the pseudo-random sequence generator 630 may include flip-flops FF0, FF1, and FF2, multiplexers MUX0, MUX1, and MUX2, and an XOR logic gate. And 631, and are connected as shown in the figure. The pseudo-random sequence generator 630 may be implemented as a linear feedback shift register (LFSR) including one shift register and one XOR logic gate 631. It will be appreciated that the configuration of pseudo-random sequence generator 630 is not limited to that disclosed herein. However, it will be appreciated that pseudo-random sequence generator 630 may be implemented with a pseudo-random number (PN) sequence generator, a cyclic redundancy code (CRC) generator, or the like.

When the initialization signal INIT is activated in the form of a pulse, the seed S2S1S0 provided from the seed table 610 shown in FIG. 3 is flip-flops FF2 and FF1 through the multiplexers MUX2, MUX1, and MUX0. , FF0). For example, the seed value S2 is loaded into the flip-flop FF2 through the multiplexer MUX2, and the seed value S1 is loaded into the flip-flop FF1 through the multiplexer MUX1. S0 is loaded into the flip-flop FF0 through the multiplexer MUX0. That is, each time the initialization signal INIT is activated, a seed initialization operation will be performed in which the pseudo-random sequence generator 630 is set to the selected seed of the seed table 610. After the seed initialization operation is performed, the pseudo-random sequence generator 630 will sequentially generate random sequence data RSD in response to the clock signal CLK. Here, the clock signal CLK may be generated in synchronization with a signal that is toggled during data input / output (eg, a read enable signal / RE or a write enable signal / WE).

5A is a block diagram illustrating the seed initializer illustrated in FIG. 3 according to an exemplary embodiment of the present invention.

Referring to FIG. 5A, the seed initializer 620 may include first and second adders 621 and 622, a selector 623, a register 624, a comparator 625, and an OR gate 626. will be. The seed initializer 620 may generate an initialization signal INIT upon an access request. In addition, the seed initializer 620 may generate an initialization signal INIT before the randomization / de-randomization of data of the current segment is completed. According to the generation of the initialization signal INIT, the seed of the seed table 610 corresponding to the accessed page will be loaded into the pseudo-random sequence generator 630. That is, pseudo-random sequence generator 630 will be initialized with the seed of seed table 610 corresponding to the accessed page. Initialization of pseudo-random sequence generator 630 will be performed each time an initialization signal INIT occurs.

The first adder 621 adds inputs CURR_PB_PTR and SEG_L-1, and the second adder 622 adds inputs CURR_L_REG and SEG_L. Here, the input CURR_PB_PTR indicates a pointer for indicating a page buffer selected by the column selection circuit 500 of FIG. 1. In other words, the input CURR_PB_PTR indicates the current column address value. The input SEG_L represents the segment size defined by the user, and the input CURR_L_REG represents the output of the register 624.

The selector 623 selects one of the outputs AO and BO of the first and second adders 621 and 622 in response to the selection signal ACC_REQ. The selection signal ACC_REQ will be activated in the form of a pulse upon access request. The selector 623 selects the output AO of the first adder 621 when the selection signal ACC_REQ is activated, and selects the output BO of the second adder 622 when the selection signal ACC_REQ is inactive. . The register 624 will be used to store the value selected by the selector 623 in response to the initialization signal INIT output from the OR gate 626. The comparator 625 determines whether the output CURR_L_REG of the register 624 and the current column address CURR_PB_PTR coincide with each other, and generate a pulse signal PUL as a result of the determination. The OR gate 626 may generate an initialization signal INIT in response to the selection signal ACC_REQ and the pulse signal PUL. When either the selection signal ACC_REQ and the pulse signal PUL are activated, the initialization signal INIT will be activated in the form of a pulse. When the initialization signal INIT is activated, a seed initialization operation on the pseudo-random sequence generator 630 will be performed, while a value representing the last data of the next segment will be loaded into the register 624.

It will be appreciated that the seed initializer 620 according to an exemplary embodiment of the invention is not limited to that disclosed herein. For example, although not shown in the figure, one of the first and second adders 621, 622 may be removed. In this case, the selector 623 is located in front of the adder and will pass the inputs CURR_PB_PTR, SEG_L-1 or the inputs CURR_L_REG, SEG_L to the adder. The value added by the adder will be passed to register 624.

5B and 5B are timing diagrams schematically illustrating a segment size setting method according to an exemplary embodiment of the present invention.

The segment size SEG_L may be provided from the memory controller to which the flash memory device is applied using a specific command. For example, as shown in FIG. 5B, a parameter indicative of the segment size SEG_L may be sent from the memory controller to the flash memory device along with a set feature command. Here, the address will be used to indicate a location (eg, a register location) in which data D0 to Dn representing the segment size SEG_L are to be stored. The data D0-Dn representing the segment size SEG_L are stored in registers (eg, included in the control logic 300 of FIG. 1) of the flash memory device in synchronization with the falling and rising edges of the DQS signal, respectively. Will be. As shown in FIG. 5C, the data D0 to Dn indicating the segment size SEG_L may be input in a single data rate SDR method instead of the double data rate DRD method illustrated in FIG. 5B. It will be well understood. The operation of setting the segment size SEG_L may be accomplished by transmitting the value of the segment size SEG_L to the flash memory device with the set feature command after the power-up.

In the exemplary embodiment of the present invention, as shown in FIG. 5B, the command and the address toggle the WE signal and transmit, and during the write operation, the data is a toggle of the DQS signal as a data strobe signal. Will be input from outside. Similarly, in a read operation, data may be output to the outside according to the toggle of the DQS signal generated according to the RE signal input from the outside. Flash memory devices employing this data input / output method are referred to as "toggle DDR NAND flash memory devices" and are available on the web site (http://www.samsung.com/global/business/semiconductor/products/flash/Products_Toggle_DDR_NANDFlash.html). It is disclosed and will be included as a reference. In addition, the flash memory device may be configured as an Open NAND Flash Interface (ONFI) DDR NAND flash memory device, which is published on the website (http://onfi.org/specifications/) and will be incorporated by reference. Meanwhile, as shown in FIG. 5C, in the case of a read / write operation that follows the SDR (Single Data Rate) format, the RE / WE signal may be used instead of the DQS signal.

In an exemplary embodiment, only some of the data D0 to Dn provided with the set feature command may be used as data representing the segment size SEG_L. The remaining data can be used to specify segment size and other parameters. This will be explained in detail later. The test command may be used instead of the set feature command to set the segment size SEG_L.

In an exemplary embodiment, it will be appreciated that the operation of setting the segment size SEG_L is not limited to that disclosed herein. For example, a value of the segment size SEG_L may be stored as the nonvolatile trim information in the memory cell array 100 of the flash memory device. In this case, upon power-up, the value of the segment size SEG_L will be loaded into the randomization and de-randomization circuit 600 under the control of the control logic 300. As another example, the value of the segment size SEG_L may be set through the fuse option at the wafer level or at the package level.

6A is a timing diagram illustrating the operation of a randomization and de-randomization circuit in accordance with an exemplary embodiment of the present invention. Hereinafter, the operation of the randomization and de-randomization circuit according to an exemplary embodiment of the present invention will be described in detail based on the reference figures. Prior to the description, assume that the segment size L is 1084B (B represents bytes). Also assume that the column address entered in the access request is CA0. According to this assumption, the requested access will be sequential access to read the full-page data.

First, when a read / write operation is requested, an address corresponding to an access requested page will be sent to the flash memory device. One of the seeds of the seed table 610 will be selected according to the page address. The selected seed will be sent to the pseudo-random sequence generator 630. The access request will be completed after a specific command (eg, 30h) has been entered in the read operation and after an address has been entered in the write operation. Upon completion of the access request, the selection signal ACC_REQ will be activated in pulse form by the control logic 300.

As the selection signal ACC_REQ is activated, the OR gate 626 of the seed initialization unit 620 activates the initialization signal INIT in the form of a pulse in response to the activated selection signal ACC_REQ. As the initialization signal INIT is activated in pulse form, the pseudo-random sequence generator 630 will be initialized with the seed provided from the seed table 610. In other words, when the initialization signal INIT is activated, the seed S0-S2 is transferred to the flip-flops FF0-FF2 through the multiplexers MUX0-MUX2 of the pseudo-random sequence generator 630. . As a result, when the initialization signal INIT is activated, a seed initialization operation will be performed in which the pseudo-random sequence generator 630 is initialized with the seed provided from the seed table 610.

As the selection signal ACC_REQ is activated, the selector 623 of the seed initializer 620 transfers the output AO of the first adder 621 to the register 624. The register 624 may store the output AO of the first adder 621 according to the activation of the initialization signal INIT. The output AO of the first adder 621 has a sum of the value CURR_PB_PTR indicating the current column address CA0 and the value SEG_L-1 smaller than 1 by the segment size, that is, the value 1083. That is, register 624 will be set to a value of 1083. This means that the output CURR_L_REG of the register 624 has a value of 1083. The value stored in register 624 will be used to indicate the last data (or referred to as the last segment data) (eg, D1083) of the segment currently being transmitted. This is to perform a seed initialization operation for randomization / de-randomization of the first segment data (eg, D1084) belonging to the next segment.

After the seed initialization operation, data (eg, data randomized as read data or data to be programmed) will be sent to the randomization and de-randomization circuit 600. The mixer 640 will logically combine the data sent to the randomization and de-randomization circuit 600 with the random sequence data RSD from the pseudo-random sequence generator 630. That is, data sent to the randomization and de-randomization circuit 600 will be randomized or de-randomized. As data is sequentially sent to the randomization and de-randomization circuit 600, as shown in FIG. 6A, the column address CA will also increase sequentially. The value CURR_PB_PTR representing the current column address CA will be transmitted to the comparator 625 of the seed initializer 630. Comparator 625 will determine whether the output (CURR_L_REG) of the register 624 (which indicates the last segment data of the current segment) and the value (CURR_PB_PTR) that represents the current column address match.

If the output CURR_L_REG of the register 624 and the value CURR_PB_PTR indicating the current column address match, the output PUL of the comparator 625 will be activated in the form of a pulse. In other words, as shown in FIG. 6A, when the output CURR_L_REG of the register 624 is 1083 and the value CURR_PB_PTR indicating the current column address is 1083, the output PUL of the comparator 625 is in the form of a pulse. Will be activated. When the output of the comparator 625 is activated, it means that random sequence data RSD for the last segment data of the current segment is generated. As the output PUL of the comparator 625 is activated in pulse form, the initialization signal INIT will also be activated in pulse form. This means that the seed (corresponding to the access requested page) output from the seed table 610 is loaded into the flip-flops FF2-FF0 through the multiplexers MUX2-MUX0 of the pseudo-random sequence generator 630. do. That is, the seed initialization operation of the pseudo-random sequence generator 630 will be performed.

At this time, since the selection signal ACC_REQ is maintained in an inactive state, the output BO of the second adder 622 may be transmitted to the register 624 through the selector 623. When the initialization signal INIT is activated in the form of a pulse upon activation of the output PUL of the comparator 625, the output BO of the second adder 622 will be loaded in the register 624. Here, the output BO of the second adder 622 is the sum of the segment size SEG_L and the output CURR_L_REG of the register 624 and has a value of 2167. That is, register 624 will be set to a value of 2167 representing the last segment data D2167 of the second segment. This means that the output CURR_L_REG of the register 624 has a value of 2167.

Thereafter, the data randomization / de-randomization operation for the second segment and the seed initialization operation for the remaining segments are performed substantially the same as described above, and a description thereof will therefore be omitted.

As can be seen from the above description, the seed initialization operation will be performed before the first data D0, D1084, D2168, ... of each segment is randomized / de-randomized. Thus, the seed assigned to the page will be applied repeatedly to segments (belonging to one page) having a size defined by the user.

6B is a timing diagram illustrating the operation of a randomization and de-randomization circuit according to an exemplary embodiment of the present invention. Hereinafter, the operation of the randomization and de-randomization circuit according to an exemplary embodiment of the present invention will be described in detail based on the reference figures. Prior to the description, assume that the size of the segment is 1084B (B represents bytes). Also assume that the column address entered in the access request is CA1084. According to this assumption, the requested access will be random access for reading one or more segments belonging to full-page data (ie, one page).

First, when a read / write operation is requested, an address corresponding to an access requested page will be sent to the flash memory device. One of the seeds of the seed table 610 will be selected according to the page address. The selected seed will be sent to the pseudo-random sequence generator 630. The access request will be completed after a specific command (eg, 30h) has been entered in the read operation and after an address has been entered in the write operation. Upon completion of the access request, the selection signal ACC_REQ will be activated in pulse form by the control logic 300.

As the selection signal ACC_REQ is activated, the OR gate 626 of the seed initialization unit 620 activates the initialization signal INIT in the form of a pulse in response to the activated selection signal ACC_REQ. As the initialization signal INIT is activated in pulse form, the pseudo-random sequence generator 630 will be initialized with the seed provided from the seed table 610. In other words, when the initialization signal INIT is activated, the seed S0-S2 is transferred to the flip-flops FF0-FF2 through the multiplexers MUX0-MUX2 of the pseudo-random sequence generator 630. . As a result, when the initialization signal INIT is activated, a seed initialization operation will be performed in which the pseudo-random sequence generator 630 is initialized with the seed provided from the seed table 610.

As the selection signal ACC_REQ is activated, the selector 623 of the seed initializer 620 transfers the output AO of the first adder 621 to the register 624. The register 624 may store the output AO of the first adder 621 according to the activation of the initialization signal INIT. The output AO of the first adder 621 has a value of 2167, that is, the sum of the value CURR_PB_PTR indicating the current column address CA1084 and the value SEG_L-1 smaller than 1 by the segment size. That is, register 624 will be set to a value of 2167. This means that the output CURR_L_REG of the register 624 has a value of 2167. The value stored in register 624 will be used to indicate the last data (or referred to as the last segment data) of the currently transmitted segment (eg, D2167). This is to perform a seed initialization operation for randomization / de-randomization of the first segment data (eg, D2168) belonging to the next segment.

After the seed initialization operation, data (eg, data randomized as read data or data to be programmed) will be sent to the randomization and de-randomization circuit 600. The mixer 640 will logically combine the data sent to the randomization and de-randomization circuit 600 with the random sequence data RSD from the pseudo-random sequence generator 630. That is, data sent to the randomization and de-randomization circuit 600 will be randomized or de-randomized. As data is sequentially sent to the randomization and de-randomization circuit 600, as shown in FIG. 6B, the column address CA will also increase sequentially. The value CURR_PB_PTR representing the current column address CA will be transmitted to the comparator 625 of the seed initializer 630. Comparator 625 will determine whether the output (CURR_L_REG) of the register 624 (which indicates the last segment data of the current segment) and the value (CURR_PB_PTR) that represents the current column address match.

If the output CURR_L_REG of the register 624 and the value CURR_PB_PTR indicating the current column address match, the output PUL of the comparator 625 will be activated in the form of a pulse. In other words, as shown in FIG. 6B, when the output CURR_L_REG of the register 624 is 2167 and the value CURR_PB_PTR indicating the current column address is 2167, the output PUL of the comparator 625 is in the form of a pulse. Will be activated. When the output of the comparator 625 is activated, it means that random sequence data RSD for the last segment data of the current segment is generated. As the output PUL of the comparator 625 is activated in pulse form, the initialization signal INIT will also be activated in pulse form. This means that the seed (corresponding to the access requested page) output from the seed table 610 is loaded into the flip-flops FF2-FF0 through the multiplexers MUX2-MUX0 of the pseudo-random sequence generator 630. do. That is, the seed initialization operation of the pseudo-random sequence generator 630 will be performed.

At this time, since the selection signal ACC_REQ is maintained in an inactive state, the output BO of the second adder 622 may be transmitted to the register 624 through the selector 623. When the initialization signal INIT is activated in the form of a pulse upon activation of the output PUL of the comparator 625, the output BO of the second adder 622 will be loaded in the register 624. Here, the output BO of the second adder 622 is the sum of the segment size SEG_L and the output CURR_L_REG of the register 624 and has a value of 3251. That is, register 624 will be set to a value of 3251 representing the last segment data D3251 of the second segment. This means that the output CURR_L_REG of the register 624 has a value of 3251.

Thereafter, the data randomization / de-randomization operation for the second segment and the seed initialization operation for the remaining segments are performed substantially the same as described above, and a description thereof will therefore be omitted.

As can be seen from the above description, the seed initialization operation will be performed before the first data (D1084, D2168, ...) of each segment is randomized / de-randomized. Thus, the seed assigned to the page will be applied repeatedly to segments (belonging to one page) having a size defined by the user.

7A and 7B are timing diagrams for schematically describing read and write operations of a flash memory device according to an exemplary embodiment of the present invention.

)는 명령(10h)의 입력에 따라 로우 레벨로 천이한다. 프로그램 동작이 완료되면, 레디/비지 신호(

)는 하이 레벨로 천이한다. 즉, 쓰기 동작이 종료될 것이다.First, in a write operation, a series of segments SEG [0] to SEG [as data to be programmed following the input of an instruction 80h and an address C1C2R1R2R3 (C represents a column address and R represents a row address). i-1]) will be entered. Here, each of the segments SEG [0] to SEG [i-1] may be composed of program data and ECC. As shown in FIG. 7A, a seed initialization operation will be performed for each segment. The seed initialization operation is substantially the same as that described in FIGS. 6A and 6B, and a description thereof will therefore be omitted. After a series of segments (SEG [0] to SEG [i-1]) is input, the ready / busy signal (

) Transitions to the low level according to the input of the command 10h. When the program operation is completed, the ready / busy signal (

) Transitions to a high level. That is, the write operation will end.

)는 로우 레벨로 유지될 것이다. 이후, 읽혀진 데이터로서, 일련의 세그먼트들(Segment[0], Segment[1], 등)이 순차적으로 출력될 것이다. 여기서, 세그먼트들(Segment[0], Segment[1], 등) 각각은 프로그램 데이터와 ECC로 구성될 것이다. 도 7b에 도시된 바와 같이, 세그먼트 마다 시드 초기화 동작이 행해질 것이다. 시드 초기화 동작은 도 6a 및 도 6b에서 설명된 것과 실질적으로 동일하며, 그것에 대한 설명은 그러므로 생략될 것이다. 비록 도면에는 도시되지 않았지만, 도 6a 및 도 6b에서 설명된 바와 같이, 최초의 시드 초기화 동작은 실질적인 데이터 랜덤화/디-랜덤화 이전에 액세스 요청에 따라 행해질 것이다.As shown in FIG. 7B, the read operation will be performed in response to the input of the series of commands 00h, the address C1C2R1R2R3, and the command 30h. During the operation, the ready / busy signal (

) Will remain at the low level. Then, as read data, a series of segments (Segment [0], Segment [1], etc.) will be sequentially output. Here, each of the segments Segment [0], Segment [1], etc. may be composed of program data and ECC. As shown in FIG. 7B, a seed initialization operation will be performed for each segment. The seed initialization operation is substantially the same as that described in FIGS. 6A and 6B, and a description thereof will therefore be omitted. Although not shown in the figures, as described in FIGS. 6A and 6B, the initial seed initialization operation will be performed according to the access request prior to actual data randomization / de-randomization.

8 is a flowchart for describing a method of operating a flash memory device according to an exemplary embodiment of the present invention. Hereinafter, a method of operating a flash memory device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 8, the method of operating a flash memory device may include receiving an access request (S100); Selecting a seed corresponding to an access requested page (S200); Performing a seed initialization operation in which the pseudo-random sequence generator 630 is initialized with the selected seed (S300); Generating random sequence data to combine random sequence data and transmitted data (S400); And determining whether all segments have been transmitted (that is, whether all of the segments requested for access have been transmitted) (S500). If all segments are not transmitted, the operation method will proceed to step S300 for performing a seed initialization operation. In contrast, if it is determined that all segments have been transmitted, the method of operating the flash memory device will be terminated.

In an exemplary embodiment, the operation to define the segment size L will be done before the normal access request described in FIG. 8.

9A and 9B are diagrams for schematically describing a randomization region determined by setting of a randomization on / off function.

The data D0 to Dn provided with the set feature command (or test command) include parameter values for setting the segment size as well as parameter values indicating random on / off information and / or randomized off area information. will be. For example, as shown in FIG. 9A, data provided with a set feature command (or a test command) may include on / off flags indicating random on / off information and off area information indicating randomized off area information. It will include. Some areas of the segment (areas hatched in the drawing) by the randomization off start address (or pointer) and the randomization off end address (or pointer) as the randomization off area information (hereinafter referred to as randomization off area) Can be specified. In this case, the data of the remaining portions except the randomization off region will be randomized. The method of designating the randomization off region may be variously changed. For example, when only a randomization off start address (or pointer) is provided, the randomization off area will be determined from the access point specified by the randomization off start address to the end of the segment. That is, as illustrated in FIG. 9B, when a region corresponding to parity information of the segment is to be defined as a randomization off region, only the randomization off start address will be included in the parameter value. It will be appreciated that the randomization off area includes the area storing spare data and / or monitoring data. Here, the monitoring data will include a monitoring data pattern for MLC read level control. This is disclosed in Korean Patent Publication No. 2009-0066680 (corresponding US Patent Publication No. 2009-0164710) entitled "Semiconductor Memory System and Access Method thereof" and will be incorporated by reference.

In an exemplary embodiment, instead of three feature instructions, a randomize on / off instruction can be used separately.

In an exemplary embodiment, the unit of the randomization off region may be variously determined. For example, the unit of randomization off region may be any size in a segment, one or more segments, one or more pages, one or more memory blocks, one or more plans, It may consist of one or more channels, or a combination thereof.

In an exemplary embodiment, the randomization on / off function may be automatically set based on a wear index. For example, the wear index may include a program-erase cycle, program time (or program loop count), erase time (or erase loop count), read level shift (or charge loss), and the like. The memory controller will automatically set the random on / off function of the flash memory device based on the wear index.

Although not shown in the figure, it will be understood that the setting of the randomization on / off function is applied not only to randomization but also to de-randomization.

10 is a block diagram schematically illustrating a flash memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 10, a flash memory device may include a memory cell array 100a, a control logic 300a, a page buffer circuit 400a, a column select circuit 500a, a randomization and de-randomization circuit 600a, and And an input / output interface 700a. The memory cell array 100a, the page buffer circuit 400a, the column select circuit 500a, and the input / output interface 700a shown in FIG. 10 operate substantially the same as those shown in FIG. Therefore it will be omitted.

The control logic 300a will include a register 301 and a decoder 302. The register 301 will be set to a parameter value (eg, including randomized off region information and randomized on / off information) input with the set feature command. Decoder 302 will decode the parameter value stored in register 301 to generate a randomized off flag signal (RFS). The randomization off flag signal (RFS) will be activated upon access request (or read / write request) depending on whether the current column offset value belongs to the randomization off region stored in the register 301. Activation of the randomization off flag signal (RFS) means that the randomization function is turned off. The decoder 302 may be configured, for example, with a counter, a comparator for comparing the value of the counter with the start address of the random off region, and the like.

The randomization and de-randomization circuit 600a is located between the input / output interface 700a and the column selection circuitry 500a and will randomize / de-randomize the transmitted data (program data or read data). . The randomization and de-randomization circuit 600a will include a randomization and de-randomization unit 601 and a multiplexer / demultiplexer 602. The randomization and de-randomization unit 601 operates substantially the same as that shown in FIG. 3, and a description thereof will therefore be omitted.

The multiplexer / demultiplexer 602 operates in response to the randomization off flag signal (RFS), and selects one of data transmitted from the input / output interface 700a and data output from the randomization and de-randomization unit 601. will be. For example, when the randomization off flag signal (RFS) is activated (ie, when the randomization function is turned off), the multiplexer / demultiplexer 602 receives data (i.e., not randomized) from the input / output interface 700a. Not data). The multiplexer / demultiplexer 602 will select data output from the randomization and de-randomization unit 601 (ie, randomized data) in response to deactivation of the randomization off flag signal (RFS).

The multiplexer / demultiplexer 602 operates in response to the randomization off flag signal (RFS), and outputs data output from the column selection circuit 500a to the input / output interface 700a and the randomization and de-randomization unit 601. Will be delivered to either. For example, the multiplexer / demultiplexer 602 may transfer data output from the column select circuit 500a to the input / output interface 700a in response to the activation of the randomization off flag signal RFS. The multiplexer / demultiplexer 602 will pass the data output from the column select circuit 500a to the randomization and de-randomization unit 601 in response to deactivation of the randomization off flag signal (RFS).

In an exemplary embodiment, the randomization and de-randomization unit 601 may be configured to receive a randomization off flag signal (RFS), as shown by the dashed lines in FIG. 10. This is to allow the randomization and de-randomization unit 601 to operate selectively according to the size of the random off region. For example, if randomization on / off is performed on a segment basis, the randomization and de-randomization unit 601 will not be affected by the randomization off flag signal (RFS). When randomization on / off is performed on a page / block / plan basis, the randomization and de-randomization unit 601 does not operate while the data to which randomization off is applied is inputted. Will be affected).

As can be seen from the above description, it is possible to activate or deactivate the randomization / de-randomization function based on the parameter value set in the register 301.

11A is a block diagram schematically illustrating a flash memory device according to another embodiment of the present invention.

Referring to FIG. 11A, a flash memory device includes a memory cell array 100b, a control logic 300b, a page buffer circuit 400b, a column select circuit 500b, a randomization and de-randomization circuit 600b, and And an input / output interface 700b. The memory cell array 100b, the control logic 300b, the page buffer circuit 400b, the column select circuit 500b, and the input / output interface 700b shown in FIG. 11A operate substantially the same as that shown in FIG. The description thereof will therefore be omitted.

The randomization and de-randomization circuit 600b will include a random sequence data generation unit 603, an or gate 604, and first and second multiplexers 605 and 606. The random sequence data generation unit 603 will be configured the same as that shown in FIG. 3 except that the mixer 630 is removed. For example, the random sequence data generation unit 603 may include a seed table 610, a seed initializer 620, and a pseudo-random sequence generator 630. Random sequence data (eg, 1-bit random sequence data) sequentially generated by the random sequence data generation unit 603 may be provided to the or gate 604 through the inverter INV1. The OR gate 604 will output the selection signal SEL in response to the randomized off flag signal RFS and the inverted random sequence data.

The first multiplexer 605 operates in response to the selection signal SEL and selects one of the data Data_In output from the input / output interface 700b and the inverted data Data_In_b through the inverter INV2. For example, if the randomization off flag signal (RFS) is activated high, the randomization function will be turned off. In this case, the selection signal SEL has a logic high level regardless of the value of the random sequence data. If the selection signal SEL has a logic high level, the first multiplexer 605 will select the data Data_In rather than the inverted data Data_In_b. In other words, the data randomization function is bypassed. If the randomization off flag signal (RFS) is deactivated low, the randomization function will be on. In this case, the selection signal SEL is not fixed to the logic high level or the logic low level but has a logic high level and a logic low level according to the value of the random sequence data. As the selection signal SEL is set to a logic high level and a logic low level according to the value of the random sequence data, the first multiplexer 605 inverts the data Data_In and the data Data_In_b according to the value of the random sequence data. Will choose. That is, data randomization will be performed.

The second multiplexer 606 operates in response to the selection signal SEL and selects one of the data Data_Out output from the column selection circuit 500c and the inverted data Data_Out_b through the inverter INV3. If the select signal SEL has a logic high level, the second multiplexer 606 will select data Data_Out. That is, data de-randomization is bypassed. If the randomization off flag signal (RFS) is deactivated low, the de-randomization function will be on. In this case, the selection signal SEL has a logic high level and a logic low level according to the value of the random sequence data. As the selection signal SEL is set to a logic high level and a logic low level according to the value of the random sequence data, the second multiplexer 606 inverts the data Data_Out and the inverted data Data_Out_b according to the value of the random sequence data. Will choose. That is, data de-randomization will be done.

11B is a block diagram schematically illustrating a flash memory device according to another embodiment of the present invention.

Referring to FIG. 11B, a flash memory device may include a memory cell array 100c, a page buffer circuit 400c, a column select circuit 500c, a randomization and de-randomization circuit 600c, and an input / output interface 700c. Will include. The memory cell array 100c, the page buffer circuit 400c, the column select circuit 500c, and the input / output interface 700c shown in FIG. 11B operate substantially the same as those shown in FIG. Therefore it will be omitted.

The randomization and de-randomization circuit 600c shown in FIG. 11B shows that the output of the random sequence data generator 607, i.e., random sequence data, is used as the selection signal SEL of the multiplexers 608 and 609. FIG. Except for the substantially same as that shown in Fig. 11A, the description thereof will therefore be omitted.

FIG. 12 is a flowchart for describing an operation of a flash memory device having a randomization on / off function described with reference to FIGS. 10 and 11A. For convenience of explanation, assume that the randomization off area is set to a specific area of the segment (for example, an area corresponding to ECC / parity data in FIG. 9B).

As described above, the segment size SEG_L of the flash memory device will be set using the set feature command (or test command). A register (eg, 301) of the control logic 300a / b may be set as parameter information indicating the segment size SEG_L and region information for specifying randomization on / off information and randomization off region. This will be done in step S200. This operation (setting of segment size and / or setting of randomization on / off) may be performed after power-up or as needed.

Access to the flash memory device (read / write operation) will be requested in step S210. In step S220, it is determined whether the current offset address input at the time of the access request belongs to the randomization off area set in the register 301. This will be done by the control logic 300a / b. If it is determined that the current offset address does not belong to the randomization off region set in the register 301, data will be transmitted without randomization / de-randomization. The procedure will then proceed to S250. If it is determined that the current offset address belongs to the randomization off area set in the register 301, randomization / de-randomization of the transmitted data will be performed. This will be done substantially the same as described in FIGS. 10 and 11A. The procedure will then proceed to S250.

In step S250, it may be determined whether all data (eg, 512-bytes) corresponding to the unit of the randomization off area has been transmitted. For example, it will be determined whether all data corresponding to one segment (eg, 512-bytes) has been transmitted. If not, the procedure will proceed to step S220. If so, the procedure will proceed to step S260. In step S260, it will be determined whether all of the data requested for access has been transmitted. If not, the procedure will proceed to step S220. If so, the procedure will end.

FIG. 13 is a diagram illustrating an example of configuring the memory cell array shown in FIG. 1 into memory blocks for an all-bit line memory structure or an odd-even memory structure. Exemplary structures of the memory cell array 100 will be described. As an example, a NAND flash memory device in which the memory cell array 100 is divided into 1024 memory blocks will be described. Data stored in each memory block may be erased simultaneously or in units of memory subblocks. In one embodiment, the memory block or memory subblock is the smallest unit of storage elements that are simultaneously erased. In each memory block, for example, there are a plurality of columns respectively corresponding to bit lines (for example, 1 KB bit lines). In one embodiment, called an all bit line (ABL) structure, all bit lines of a memory block may be selected simultaneously during read and program operations. Storage elements belonging to the word line selected by the row select circuit 200 and connected to all the bit lines may be programmed simultaneously.

In an exemplary embodiment, a plurality of storage elements belonging to the same column are connected in series to form a NAND string. One terminal of the NAND string is connected to a corresponding bit line through a select transistor controlled by a string select line SSL, and the other terminal is connected to a common source line CSL through a select transistor controlled by a ground select line GSL. )

In another exemplary embodiment called the odd-even architecture, the bit lines are divided into even bit lines BLe and odd bit lines BLO. In an odd / even bit line structure, storage elements belonging to the selected word line and connected to the odd bit lines are programmed at a first time, while storage elements belonging to the selected word line and connected to the even bit lines are not present at a second time. Is programmed.

14 is a diagram illustrating a memory cell array according to another exemplary embodiment of the present invention. The memory cell array according to another exemplary embodiment of the present invention will be configured to have a vertical structure. The vertical structure means a structure in which a string is formed perpendicular to the substrate.

Referring to FIG. 14, the memory cell array 100a includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz has a three-dimensional structure (or a vertical structure). For example, each of the memory blocks BLK1 to BLKz includes structures extending along first to third directions. For example, each of the memory blocks BLK1 to BLKz includes a plurality of strings (or NAND strings) extending along the second direction. As another example, a plurality of NAND strings may be provided along the first or third direction. In exemplary embodiments, the memory blocks BLK1 to BLKz may be selected by the row selection circuit 200 shown in FIG. 1.

FIG. 15 is a perspective view illustrating a portion of one of the memory blocks BLK1 to BLKz illustrated in FIG. 14 according to an embodiment of the present invention. FIG. 16 is a cross-sectional view of the memory block shown in FIG. 15 taken along line II ′. 15 and 16, the memory block BLKa includes structures extending along first to third directions.

First, the substrate 111 is provided. In exemplary embodiments, the substrate 111 may be a well having a first type. For example, the substrate 111 may be a p well formed by implanting a Group 5 element such as boron (B). For example, the substrate 111 may be a pocket p well provided in an n well. In the following, it will be assumed that the substrate 111 is a p well. However, it will be appreciated that the substrate 111 is not limited to p wells.

On the substrate 111, a plurality of doped regions 311 ˜ 314 extending along the first direction are provided. For example, the plurality of doped regions 311 to 314 may have a second type different from that of the substrate 111. For convenience of illustration, only four doped regions 311-314 are shown in FIG. 15. However, it will be appreciated that more doped regions are provided along the third direction. The plurality of doped regions 311 ˜ 314 may have an n-type. Hereinafter, it will be assumed that the doped regions 311 to 314 have an n-type. However, it will be appreciated that the doped regions 311-314 are not limited to n-type.

On the substrate 111 between the doped regions 311 and 312, a plurality of insulating materials 112 extending along the first direction are sequentially provided along the second direction. For example, the plurality of insulating materials 112 may be provided along the second direction to be spaced apart by a predetermined distance. Illustratively, the insulating materials 112 will comprise an insulating material such as silicon oxide.

On the substrate 111 between the doped regions 311 and 312, a plurality of pillars 113 are provided which are sequentially disposed in the first direction and penetrate the insulating materials 112 along the second direction. . In some embodiments, the pillars 113 may be connected to the substrate 111 through the insulating materials 112. Illustratively, each pillar 113 will comprise a plurality of materials. For example, the surface layer 114 of each pillar 113 may comprise a silicon material having a first type. As another example, the surface layer 114 of each pillar 113 may comprise a silicon material having the same type as the substrate 111. In the following, assume that the surface layer 114 of each pillar 113 includes p-type silicon. However, the surface layer 114 of each pillar 113 is not limited to including p-type silicon. The inner layer 115 of each pillar 113 is comprised of an insulating material. For example, the inner layer 115 of each pillar 113 may include an insulating material such as silicon oxide. Alternatively, the inner layer 115 of each pillar 113 may include an air gap.

Referring to each structure disposed between adjacent doped regions, an insulating film 116 is provided along the exposed surfaces of the insulating materials 112, the pillars 113, and the substrate 111. In exemplary embodiments, the insulating layer 116 provided on the exposed surface of the last insulating material 112 provided in the second direction toward the second direction may be removed. The insulating film 116 may be composed of one or more material layers. First conductive materials 211 to 291 are provided on the exposed surface of the insulating layer 116. For example, a first conductive material 211 extending along the first direction is provided between the insulating material 112 and the substrate 111 adjacent to the substrate 111. In exemplary embodiments, the first conductive materials 211 to 291 may be metal materials. As another example, the first conductive materials 211 to 291 may be a conductive material such as polysilicon.

The structure disposed between the doped regions 312 and 313 will be configured the same as the structure disposed between the doped regions 311 and 312. Similarly, the structure disposed between the doped regions 313 and 314 will be configured identically to the structure disposed between the doped regions 311 and 312.

Plugs 320 are respectively provided on the plurality of pillars 113. As an example, the plugs 320 may be silicon materials doped with a second type. For example, the plugs 320 may be silicon material doped with n-type. In the following, it is assumed that the plugs 320 include n-type silicon. However, the plugs 320 are not limited to containing n-type silicon. In exemplary embodiments, the width of each plug 320 may be larger than the width of the corresponding pillar 113. For example, each plug 320 may be provided in the form of a pad on the top surface of the corresponding pillar 113. Second conductive materials 331 ˜ 333 extending in the third direction are provided to be electrically connected to the plugs 320. The second conductive materials 331 ˜ 333 are sequentially disposed along the first direction. In exemplary embodiments, the second conductive materials 331 to 333 may be metal materials. As another example, the second conductive materials 331 to 333 may be conductive materials such as polysilicon.

In FIG. 16, a structure disposed between adjacent doped regions (eg, 311, 312) is electrically connected to conductive materials (eg, 331, 332, 333) that act as bit lines, respectively. Pillars 113. Pillars 113 electrically connected to conductive materials (eg, 331, 332, 333) acting as bit lines will constitute a plan. This means that one memory block is composed of a plurality of plans. 15 and 16, the conductive materials 211, 212, and 213 serve as ground select lines, and the conductive materials 291, 292, and 293 serve as string select lines, and doped regions 311 ˜. 314 may serve as a common source line, and the conductive materials 221 to 281, 222 to 282, and 223 to 283 may serve as word lines.

17 is a circuit diagram illustrating an equivalent circuit of the memory block illustrated in FIG. 16 in accordance with an exemplary embodiment of the present invention.

Referring to FIG. 17, NAND strings are provided between the bit lines and the common source line CSL. For example, NAND strings NS11, NS21, and NS31 are provided between the bit line BL1 and the common source line CSL, and NAND strings between the bit line BL2 and the common source line CSL. NS12, NS22, NS32 are provided, and NAND strings NS13, NS23, NS33 are provided between the bit line BL3 and the common source line CSL. The bit lines BL1 to BL3 may correspond to the second conductive materials 331 to 333 (see FIG. 15) respectively extending in the third direction.

The string select transistor SST of each NAND string is connected to a corresponding bit line. The ground select transistor GST of each NAND string is connected to the common source line CSL. Memory cells MC are provided between the string select transistor SST and the ground select transistor GST of each NAND string.

NAND strings commonly connected to one bit line form one column. For example, the NAND strings NS11 to NS31 connected to the bit line BL1 may form a first column. The NAND strings NS12 to NS32 connected to the bit line BL2 will form a second column. The NAND strings NS13 to NS33 connected to the bit line BL3 form a third column. NAND strings connected to one string select line SSL form one row. For example, the NAND strings NS11 to NS13 connected to the string select line SSL1 form a first row. The NAND strings NS21 to NS23 connected to the string select line SSL2 form a second row. The NAND strings NS31 to NS33 connected to the string select line SSL3 form a third row.

As shown in FIG. 17, NAND strings arranged in rows and columns share a ground select line GSL. Memory cells belonging to each row (or each plan) share word lines WL1 to WL7 arranged in different layers, respectively. For example, memory cells MC1 belonging to plan PL1 and adjacent to ground select transistors GST share a word line WL1, and belong to plan PL1 and to string select transistors SST. Adjacent memory cells MC7 share the word line WL7.

NAND strings belonging to the same row / plan share a string select line. For example, the NAND strings NS11, NS12, NS13 belonging to the plan PL1 share the string select line SSL1, and the NAND strings NS21, NS22, NS23 belonging to the plan PL2 select the string. The line SSL2 is shared, and the NAND strings NS31, NS32, and NS33 belonging to the plan PL3 share the string select line SSL3. The string select lines SSL1, SSL2, and SSL3 are controlled independently, so that the NAND strings NS11, NS12, NS13 belonging to any plan / row (e.g., PL1) are connected to the bit lines BL1, And electrically connected to BL2 and BL3, respectively. NAND strings NS21, NS22, NS23, NS31, NS32, NS33 belonging to the remaining plans (eg, PL2, PL3) will be electrically separated from the bit lines BL1, BL2, BL3, respectively.

In an exemplary embodiment, during the program and read operations, any one of the string select lines SSL1-SSL3 will be selected by the row decoder circuit 200 (see FIG. 1). That is, program and read operations may be performed in row units (or plan units) of the NAND strings NS11 to NS13, NS21 to NS23, and NS31 to NS33. One page may be configured by, for example, one string select line and memory cells belonging to one plan (connected to one word line). However, it will be appreciated that the page is not limited to what is disclosed herein.

18A is a block diagram schematically illustrating a memory system according to an exemplary embodiment of the present invention.

Referring to FIG. 18A, the memory system 3000 may include at least one flash memory 1000 and a controller 2000. The flash memory 1000 operates under the control of the controller 2000 and will be used as a storage medium. The controller 2000 may be configured to control the flash memory 1000. Flash memory 1000 may include randomization and de-randomization circuitry 1100. The flash memory 1000 shown in FIG. 18A is configured substantially the same as that shown in FIG. 1, 10, or 11, and a description thereof will therefore be omitted. The randomization and de-randomization circuit 1100 will be configured to apply the same seed to each of the segments requested for access, as described above.

The controller 2000 may include a first interface 2100, a second interface 2200, a processing unit 2300, a buffer memory 2400, and an ECC block 2500. The first interface 2100 may be configured to interface with an external (eg, a host), and the second interface 2200 may be configured to interface with the flash memory 1000. The processing unit 2300 will be configured to control the overall operation of the controller 2000. The buffer memory 2400 may be configured to store data to be stored in the flash memory 1000 or data read from the flash memory 1000. The ECC block 2500 may generate ECC data based on data output from the buffer memory 2400. The ECC block 2500 may perform error detection and correction operations on data read from the flash memory 1000 based on the ECC data. The ECC data may be stored in the same page as the data to be stored in the flash memory 1000 or in an area different from the data to be stored in the flash memory 1000.

The controller 2000 will set the segment size SEG_L using the set feature command after power up, as described in FIG. 5B. In addition to the setting of the segment size SEG_L, the setting of the randomization on / off function and the randomization off region will be performed by the controller 2000. Alternatively, a value of the segment size SEG_L may be stored as the nonvolatile trim information in the memory cell array 100 of the flash memory device. In this case, upon power-up, the value of the segment size SEG_L will be loaded into the randomization and de-randomization circuit 600 under the control of the control logic 300 of the flash memory device. As another example, the value of the segment size SEG_L may be set through the fuse option at the wafer level or at the package level.

In an exemplary embodiment, the first interface 2100 may be configured with a combination of one or more of computer bus standards, storage bus standards, iFCPPeripheral bus standards, and the like. Computer bus standards include computer bus standards such as S-100 bus, Mbus, Smbus, Q-Bus, ISA, Zorro II, Zorro III, CAMAC, FASTBUS, LPC, EISA, VME, VXI, NuBus, TURBOchannel, , VLB, PCI, PXI, HP GSC bus, CoreConnect, InfiniBand, UPA, PCI-X, AGP, PCIe, Intel QuickPath Interconnect, Hyper Transport, Storage bus standards include ST-506, ESDI, SMD, Parallel ATA, DMA, SSA, HIPPI, USB MSC, FireWire (1394), Serial ATA, eSATA, SCSI, Parallel SCSI, Serial Attached SCSI, Fiber Channel, iSCSI, SAS, RapidIO, FCIP, and the like. The iFCPPeripheral bus standards include the Apple Desktop Bus, HIL, MIDI, Multibus, RS-232, DMX512-A, EIA / RS-422, IEEE-1284, UNI / O, 1-Wire, I2C, SPI, EIA / RS-485, USB, Camera Link, External PCIe, Light Peak, Multidrop Bus, etc.

18B is a block diagram schematically illustrating a memory system according to another exemplary embodiment of the present invention.

Referring to FIG. 18B, the memory system 3000 may include at least one flash memory 1000, a controller 2000, and a bonding option 3010. The flash memory 1000 and the controller 2000 shown in FIG. 18B are substantially the same as those shown in FIG. 18A except for the following differences, and a description thereof will therefore be omitted.

The bonding option 3010 may be used to provide a value of the segment size SEG_L to the nonvolatile memory device 1000. Bonding option 3010 may include, for example, fuses configured to set a value (eg, binary code value) of a particular segment size (SEG_L) and connected to the pads. Setting to a specific segment size (SEG_L) will be done at the package level. In this case, the operation of transmitting the set feature command from the controller 2000 to the flash memory 1000 after the power-up to set the segment size SEG_L will not be performed.

19 is a block diagram schematically illustrating a memory system according to another exemplary embodiment of the present invention.

Referring to FIG. 19, the memory system 3000a may include at least one flash memory 1000a and a controller 2000a. The flash memory 1000a operates under the control of the controller 2000a and will be used as a storage medium. The flash memory 1000a shown in FIG. 19 will not include the randomization and de-randomization circuits mentioned above. The controller 2000a may be configured to control the flash memory 1000a. The controller 2000a may be configured to randomize data to be stored in the flash memory 1000a and to add ECC data to the randomized data. The controller 2000a may be configured to perform detection and correction operations for errors in the randomized data read from the flash memory 1000a and to de-randomize the randomized data.

The controller 2000a controls the first interface 2100a, the second interface 2200a, the processing unit 2300a, the buffer memory 2400a, the ECC block 2500a, and the randomized / de-randomized block 2600. Will include. The components 2100a, 2200a, 2300a, 2400a, and 2500a shown in FIG. 19 are substantially the same as those shown in FIG. 18A except for the following differences, and a description thereof will therefore be omitted.

The randomization and de-randomization block 2600 may be configured to randomize data output from the buffer memory 2400a and to de-randomize the data (ie, randomized data) read from the flash memory 1000a. will be. Randomization and de-randomization block 2600 performs randomization and de-randomization operations on sequential data and random data according to the scheme described in FIGS. 1 to 12, and a description thereof will therefore be omitted. . The ECC block 2500a will generate ECC data based on the randomized data output from the randomized and de-randomized block 2600. The ECC block 2500a may also perform error detection and correction operations on the data read from the flash memory 1000a, that is, the randomized data, based on the ECC data. The ECC data may be stored in the same page as the data to be stored in the flash memory 1000a or in an area different from the data to be stored in the flash memory 1000a.

In the memory system illustrated in FIG. 19, a write operation randomizes data to be stored in the flash memory 1000a, generates ECC data based on the randomized data, and randomizes ECC data and random data to the flash memory 1000a. It will include storing the formatted data. Alternatively, the method may include randomly storing both data to be stored and ECC data . The read operation may include performing error detection and correction operations on the read data (ie, randomized data) based on the ECC data, and randomizing the read data.

20 is a block diagram schematically illustrating a semiconductor drive according to an exemplary embodiment of the present invention.

Referring to FIG. 20, the semiconductor drive 4000 (SSD) may include a storage medium 4100 and a controller 4200. The storage medium 4100 may be connected to the controller 4200 through a plurality of channels CH0-CHn-1. Each of the channels CH0-CHn-1 may have a plurality of nonvolatile memories NVM in common. Each nonvolatile memory will be comprised of the flash memory described in FIG. 1, 10, or 11. That is, each nonvolatile memory (NVM) will include randomization and de-randomization circuitry 4101. In this case, the controller 4200 will be configured substantially the same as shown in FIG. 18A. That is, data randomization and de-randomization are done in each nonvolatile memory, and error detection and correction will be done in controller 4200.

Nonvolatile memory devices connected to one channel (e.g., CH0) are used to store single-bit data (e.g., metadata, parity data, or the like), and the other channels (e.g., For example, nonvolatile memory devices connected to each of CH1 to CHn-1) may be used to store multi-bit data. In this case, the controller 4200 may turn off the randomization function of the nonvolatile memory devices of the channel CH0 using the set feature command. Similarly, the controller 4200 may set a randomization off area for the nonvolatile memory devices of the remaining channels CH1 to CHn-1 using the set feature command.

21 is a block diagram schematically illustrating a semiconductor drive according to another exemplary embodiment of the present invention.

Referring to FIG. 21, a semiconductor drive 4000a (SSD) may include a storage medium 4100a and a controller 4200a. The storage medium 4100a may be connected to the controller 4200a through a plurality of channels CH0-CHn-1. Each of the channels CH0-CHn-1 may have a plurality of nonvolatile memories NVM in common. Each nonvolatile memory (NVM) does not include randomization and de-randomization circuitry. In this case, each nonvolatile memory NVM will be configured substantially the same as that shown in FIG. Controller 4200a will include randomization and de-randomization circuitry 4102. In this case, the controller 4200a will be configured substantially the same as that shown in FIG. That is, data randomization and de-randomization and error detection and correction will be done within the controller 4200a.

FIG. 22 is a block diagram schematically illustrating storage using the semiconductor drive illustrated in FIG. 20 or 21, and FIG. 23 is a block diagram schematically illustrating a storage server using the semiconductor drive illustrated in FIG. 20 or 21.

The semiconductor drive 4000 according to an exemplary embodiment of the present invention may be used to configure storage. As shown in FIG. 22, the storage will include a plurality of semiconductor drives 4000 configured substantially the same as described in FIG. 20 or 21. The semiconductor drive 4000 according to an exemplary embodiment of the present invention may be used to configure a storage server. As shown in FIG. 23, the storage server includes a plurality of semiconductor drives 4000 configured substantially the same as those described with reference to FIGS. 20 and 21, and a server 4000A for controlling overall operations of the storage server. Will include. In addition, it will be appreciated that a RAID controller 4000B for parity management may be provided to the storage server according to a parity scheme applied to heal defects on data stored in the semiconductor drives 4000.

24 to 26 are diagrams schematically showing systems according to exemplary embodiments of the present invention.

When a semiconductor drive consisting of a memory controller and flash memory devices according to exemplary embodiments of the present invention is applied to storage, as illustrated in FIG. 24, the system 6000 may be connected to a host by wire and / or wirelessly. It will include storage 6100 in communication. When a semiconductor drive including a data storage device according to exemplary embodiments of the present invention is applied to a storage server, as shown in FIG. 25, the system 7000 may communicate with the host by wire and / or wirelessly. Ones 7100 and 7200. In addition, as shown in FIG. 26, the semiconductor drive including the data storage device according to the exemplary embodiment of the present invention may be applied to the mail server 8100. The mail server 8100 communicates with user mail programs through a mail daemon connected in POP and SMTP manners, and the mail servers 8100 will communicate via an internet network.

27 to 31 are schematic views illustrating other systems to which a nonvolatile memory device according to exemplary embodiments of the present invention is applied.

FIG. 27 is a block diagram schematically illustrating a cellular phone system in which a flash memory device according to an exemplary embodiment of the present invention is used.

Referring to FIG. 27, the mobile phone system time-divides the compression or decompression ADPCM codec circuit 9202, the speaker 9203, the microphone 9304, and the digital data. A multiplexing TDMA circuit 9206, a PLL circuit 9210 for setting a carrier frequency of a wireless signal, an RF circuit 9211 for transmitting or receiving a wireless signal, and the like may be included.

In addition, the mobile phone system may include various types of memory devices. For example, the mobile phone system may include a flash memory device 9207, a ROM 9008, and an SRAM 9209, which are nonvolatile memory devices. . As the memory device 9207 of the cellular phone system, for example, the flash memory device described in FIG. 1 will be used. That is, the memory device 9207 will be configured to apply the same seed to each of the segments requested for access. ROM 9308 can store programs, and SRAM 9209 serves as a work area for system control microcomputer 9212 or temporarily stores data. Here, the system control microcomputer 9212 is a processor and may control write and read operations of the flash memory device 9207.

28 is an exemplary diagram of a memory card in which a flash memory device according to an exemplary embodiment of the present invention is used. The memory card may be, for example, MMC card, SD card, multiuse card, micro SD card, memory stick, compact SD card, ID card, PCMCIA card, SSD card, chipcard, smartcard ), USB card, MCP-type embedded card storage, and the like. MCP-type embedded card storage will include eMMC (embedded MMC), Esd (embedded SD), eSSD (embedded SSD), Perfect Page NAND (PPN), and the like.

Referring to FIG. 28, a memory card includes an interface unit 9221 for performing an interface with an external device, a controller 9222 having a buffer memory to control an operation of the memory card, and a flash memory device 9207 according to an embodiment of the present invention. It may include at least one. Flash memory device 9207 will be configured to apply the same seed to each of the segments requested for access. The controller 9222 is a processor and may control write operations and read operations of the flash memory device 9207. In detail, the controller 9222 is coupled to the nonvolatile memory device 9207 and the interface unit 9221 through the data bus DATA and the address bus ADDRESS.

FIG. 29 is an exemplary diagram of a digital still camera using a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 29, the digital still camera includes a body 9301, a slot 9302, a lens 9303, a display 9308, a shutter button 9312, a strobe 9318, and the like. In particular, a memory card 9319 may be inserted into the slot 9302, and the memory card 9319 may be configured to apply the same seed to each of the segments requested for access, according to an embodiment of the present invention. It may include at least one. When the memory card 9331 is a contact type, when the memory card 931 is inserted into the slot 9302, the memory card 9311 and a specific electrical circuit on the circuit board are in electrical contact. If the memory card 9319 is of a non-contact type, the memory card 9319 will be accessed via a wireless signal.

30 is an exemplary diagram illustrating various systems in which the memory card of FIG. 29 is used.

Referring to FIG. 30, the memory card 2331 includes (a) a video camera, (b) a television, (c) an audio device, (d) a game device, (e) an electronic music device, (f) a mobile phone, and (g) Computer, (h) PDA (Personal Digital Assistant), (i) voice recorder, (j) PC card and so on.

FIG. 31 is an exemplary diagram of an image sensor system in which a flash memory device according to an exemplary embodiment of the present invention is used.

Referring to FIG. 31, an image sensor system includes an image sensor 9332, an input / output device 9336, a RAM 9348, a CPU 9344, a flash memory device 954 according to an exemplary embodiment of the present invention, and the like. can do. The flash memory device 9354 will be configured to apply the same seed to each of the segments requested for access. Each component, that is, the image sensor 9332, the input / output device 9336, the RAM 9348, the CPU 9344, and the flash memory device 9354 communicate with each other through the bus 9932. The image sensor 9332 may include a photo sensing device such as a photogate, a photodiode, or the like. Each component may be configured as a chip together with the processor, or may be configured as a separate chip from the processor.

In an exemplary embodiment of the present invention, the memory cells may be comprised of variable resistance memory cells, and an exemplary variable resistance memory cell and a memory device including the same are disclosed in US Pat. No. 7529124, which is incorporated herein by reference. Will be included.

In another exemplary embodiment of the present invention, memory cells may be implemented using one of a variety of cell structures having a charge storage layer. Cell structures having a charge storage layer may include a charge trap flash structure using a charge trap layer, a stack flash structure in which arrays are stacked in multiple layers, a flash structure without source-drain, a pin-type flash structure, and the like.

A memory device having a charge trap flash structure as a charge storage layer is disclosed in US Pat. No. 6,888,906, US Pat. . A source / drain free flash structure is disclosed in Korean Patent No. 673020 and will be incorporated by reference in this application.

The flash memory device and / or memory controller according to the present invention may be implemented using various types of packages. For example, the flash memory device and / or the memory controller according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in- Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), It can be implemented using packages such as Wafer-Level Processed Stack Package (WSP), or the like.

It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

100: memory cell array
200: row selection circuit
300: control logic
400: page buffer circuit
500: column selection circuit
600: randomized and de-randomized circuit
700: input / output interface

Claims (31)

A method of randomizing and de-randomizing data transmitted to / from a selected page of a nonvolatile memory device, the method comprising:
Randomly generating random sequence data based on the seed assigned to the selected page,
Logically combining one of the access-requested segments belonging to the selected memory space with the sequentially generated random sequence data,
Iteratively repeating the seed assigned to the selected page to the remaining access-requested segments by repeating the sequential occurrence and the logical combination until all remaining access-requested segments belonging to the selected page are transmitted. A method comprising applying. The method of claim 1,
And said logically combined data is stored in said selected page as randomized data or transmitted to a page buffer as de-randomized data. The method of claim 2,
And segments of the selected page have a variably defined size. The method of claim 3, wherein
Wherein each segment comprises program data and parity information associated with the program data. The method of claim 4, wherein
Access to the selected page is requested in units of segments. The method of claim 1,
Setting a randomization on / off function based on a set feature command. The method according to claim 6,
The randomization on / off function is set in units of segments, and the partial data of the segment corresponding to the off area information input together with the set feature command is not randomized. The method of claim 1,
Iterative application of the seed assigned to the selected page is carried out in units of segments or smaller than the page. Page buffer circuitry configured to read or write data to / from selected pages of the memory cell array; And
Randomized and de-randomized circuitry configured to randomize and de-randomize data transmitted to / from the page buffer circuit based on a seed assigned to the selected page,
The selected page is composed of a plurality of segments;
The randomization and de-randomization circuitry generates the random sequence for each of the access-requested segments of the selected page based on the seed assigned to the selected page and the random sequence generated repeatedly according to the seed. And randomize and de-randomize data in each of the access-requested segments based on the nonvolatile memory device. The method of claim 9,
The randomization and de-randomization circuit is
A seed table storing seeds corresponding to each of the pages;
A pseudo-random sequence generator provided from the seed table and generating a random sequence based on a seed corresponding to the selected page;
A mixer for logically combining the random sequence and data of an access-requested segment; And
The pseudo-random to the seed corresponding to the selected page to randomize and de-randomize the data of each of the accessed-requested segments according to the random sequence generated repeatedly according to the seed corresponding to the selected page. A nonvolatile memory device comprising a seed initializer for initializing a sequence generator. 11. The method of claim 10,
The seed initialization unit performs a seed initialization operation for initializing the pseudo-random sequence generator to a seed,
A seed initialization operation on data of a first access requested segment of the access requested segments is performed at an access request,
The seed initialization operation on the data of the remaining access requested segments is performed when the last segment data of the current access requested segment is processed. The method of claim 11,
The seed initialization unit
A register;
A first adder configured to add a value (SEG-1) smaller than the segment size and the value of the address indicating the data to be transmitted;
A second adder configured to add the output value of the register and the segment size;
A selector for selecting one of the output values of the first and second adders in response to a selection signal activated upon completion of an access request;
The output value selected by the selector is sent to the register;
A comparator for discriminating whether or not the output value of the register coincides with the value of the address representing the data to be transmitted and generating a pulse signal as a result of the determination; And
A logic gate configured to generate an initialization signal in response to the selection signal and the pulse signal,
And the register stores an output value selected by the selector in response to the initialization signal, wherein the pseudo-random sequence generator is initialized with the seed corresponding to the selected page in response to the initialization signal. 13. The method of claim 12,
And the value representing the segment size is provided from an external device with a set feature command. The method of claim 9,
And control logic for storing random on / off information and random off area information input according to a specific command, wherein the control logic is nonvolatile that generates a randomized off flag signal based on the random off area information upon an access request. Memory device. 15. The method of claim 14,
The off area defined by the random off area information is determined in units of data, a segment, a page, a block, a plan, or a chip having a smaller size than the segment. 15. The method of claim 14,
The randomization and de-randomization circuit is
A seed table storing seeds corresponding to each of the pages;
A pseudo-random sequence generator provided from the seed table and generating a random sequence based on a seed corresponding to the selected page;
A mixer for logically combining the random sequence and data of an access-requested segment;
The pseudo-random to the seed corresponding to the selected page to randomize and de-randomize the data of each of the accessed-requested segments according to the random sequence generated repeatedly according to the seed corresponding to the selected page. A seed initializer for initializing the sequence generator; And
And a multiplexer for selecting one of an output of the mixer and data of the access-requested segment in response to a write request. 17. The method of claim 16,
And the multiplexer transfers data of an access-requested segment to the mixer or to an input / output interface unit in response to the randomization off flag signal. A memory cell array;
A random sequence data generator configured to sequentially generate random sequence data; And
And a first multiplexer configured to receive program data to be stored in the memory cell array and inverted data of the program data, and select the program data or the inverted data in response to the random sequence data as a selection signal. The data selected by the first multiplexer is stored in the memory cell array as randomized data. The method of claim 18,
And a second multiplexer which receives the read data and the inverted data of the read data from the memory cell array and selects the read data or the inverted data of the read data in response to the random sequence data as the selection signal. And the data selected by the second multiplexer is output to the external device as de-randomized data. The method of claim 19,
And a control logic for storing random on / off information and random off area information input according to a set feature command, wherein the control logic is configured to generate a randomized off flag signal based on the random off area information upon an access request. Volatile memory device. 21. The method of claim 20,
And the first and second multiplexers operate in response to the selection signal generated by logically combining the randomization off flag signal and the random sequence data. A memory cell array;
A register for storing a parameter value input according to the set feature command;
A random sequence data generator configured to sequentially generate random sequence data;
A selection signal generator for generating a selection signal in response to a parameter value stored in the register and the random sequence data; And
And a first multiplexer configured to receive program data to be stored in the memory cell array and inverted data of the program data, and select the program data or the inverted data in response to the selection signal. The method of claim 22,
And a page buffer circuit arranged between the first multiplexer and the memory cell array. 24. The method of claim 23,
The data selected by the first multiplexer is transferred to the page buffer circuit as randomized data. 25. The method of claim 24,
A second multiplexer configured to receive data read from the memory cell array and inverted data of the read data through the page buffer circuit, and select the read data or the inverted data of the read data in response to the selection signal; And the data selected by the second multiplexer is output to an external device as de-randomized data. 25. The method of claim 24,
The parameter value includes random on / off information and random off region information. The method of claim 26,
And the selection signal generator generates the selection signal by logically combining the random off region information and the random sequence data when an access request is made. The method of claim 27,
When the random on / off information indicates a randomization off state, only program data is transmitted to the page buffer circuit through the first multiplexer, and only the read data is transmitted externally through the second multiplexer Device. A nonvolatile memory device including a plurality of pages; And
A controller including a buffer, the controller controlling the nonvolatile memory device,
The controller further comprises randomization and de-randomization circuitry configured to randomize and de-randomize data transmitted to / from the nonvolatile memory device based on a seed assigned to a selected page,
The randomization and de-randomization circuit is
A seed table storing seeds corresponding to each of the pages;
A pseudo-random sequence generator provided from the seed table and generating a random sequence based on a seed corresponding to the selected page;
A mixer for logically combining the random sequence and data of an access-requested segment; And
The pseudo-random to the seed corresponding to the selected page to randomize and de-randomize the data of each of the accessed-requested segments according to the random sequence generated repeatedly according to the seed corresponding to the selected page. And a seed initializer for initializing the sequence generator. 30. The method of claim 29,
The seed initialization unit performs a seed initialization operation for initializing the pseudo-random sequence generator to a seed,
A seed initialization operation on data of a first access requested segment of the access requested segments is performed at an access request,
The seed initialization operation on the data of the remaining access requested segments is performed when the last segment data of the current access requested segment is processed. A storage medium comprising a plurality of memory spaces;
A plurality of channels; And
A controller coupled to the storage medium via the plurality of channels and configured to control the storage medium,
The controller
Random sequence data is generated sequentially based on the seed assigned to the selected page,
Logically combining one of the access-requested segments belonging to the selected page with the sequentially generated random sequence data,
The logical combination with the sequentially occurring until all the remaining access-requested segments belonging to the selected page have been transmitted so that the seed assigned to the selected page is repeatedly applied to the remaining access-requested segments. By repeating
And randomize and de-randomize data transmitted to and from the storage medium.

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