KR101733567B1 - Initial seed generating method and flash memory device and memory system using the same - Google Patents

Abstract

The memory control method of the present invention includes the steps of determining whether data access is random, generating first random sequence data based on a first seed if the data access is not random, Synthesizing the read data or data to be written to the memory, generating a second seed from the first seed if the data access is random, generating second random sequence data based on the second seed And combining the second random sequence data with data read from the memory or data to be written to the memory.

Description

FIELD OF THE INVENTION [0001] The present invention relates to an initial seed generation method and a flash memory device and a memory system using the same.

The present invention relates to semiconductor memory devices, and more particularly, to flash memory devices.

A flash memory device is a kind of EEPROM in which a plurality of memory areas are erased or programmed by a single program operation. A typical EEPROM allows only one memory area to be erased or programmed at a time, which allows the flash memory device to operate at a faster and more efficient rate than systems using the flash memory device to read and write to different memory areas simultaneously . All forms of flash memory and EEPROM are worn out after a certain number of erase operations due to deterioration of the charge storage means used to store data or wear of the insulating film surrounding the charge storage means.

A flash memory device stores information on a silicon chip in a manner that does not require power to maintain information stored on the silicon chip. This means that if the power to the chip is interrupted, the information is retained without consuming power. In addition, the flash memory device provides physical impact resistance and fast read access time. Because of these features, flash memory devices are commonly used as storage devices for devices powered by batteries.

An object of the present invention is to provide a flash memory device capable of improving reliability and a memory system including the same.

The memory control method of the present invention includes the steps of determining whether data access is random, generating first random sequence data based on a first seed if the data access is not random, Synthesizing the read data or data to be written to the memory, generating a second seed from the first seed if the data access is random, generating second random sequence data based on the second seed And combining the second random sequence data with data read from the memory or data to be written to the memory.

According to exemplary embodiments of the present invention, it is possible to de-randomize randomized data by generating an initial seed (or initial random sequence data), even if access to random data is requested, and to randomize the data to be programmed It is possible.

1 is a block diagram that schematically illustrates a flash memory device in accordance with an exemplary embodiment of the present invention.
FIG. 2 is a view showing an example of configuring the memory cell array shown in FIG. 1 as memory blocks for an all-bit line memory structure or an odd-even memory structure.
3 is a block diagram that schematically illustrates the randomization and de-randomization circuitry shown in FIG. 1 in accordance with one embodiment of the present invention.
4 is a timing diagram schematically illustrating a read operation of a flash memory device according to an exemplary embodiment of the present invention.
5 is a timing diagram schematically illustrating a read operation of a flash memory device according to another exemplary embodiment of the present invention.
6 is a timing diagram schematically illustrating a write operation of a flash memory device according to an exemplary embodiment of the present invention.
Figure 7 is a block diagram that schematically illustrates the randomization and de-randomization circuitry shown in Figure 1 according to another embodiment of the present invention.
8 is a block diagram schematically illustrating the pseudo-random sequence generator shown in FIG.
FIG. 9 is a diagram showing initial seed values generated using the polynomial equation of the pseudo-random sequence generator shown in FIG.
10 is a block diagram that schematically illustrates the randomization and de-randomization circuitry shown in FIG. 1 in accordance with another embodiment of the present invention.
11A is a flowchart illustrating a randomization and de-randomization method of a flash memory device according to an exemplary embodiment of the present invention.
11B schematically illustrates a randomization and de-randomization scheme of a flash memory device according to an exemplary embodiment of the present invention.
12 is a block diagram that schematically illustrates a memory system in accordance with an exemplary embodiment of the present invention.
Figure 13 is a block diagram that schematically illustrates a memory system according to another exemplary embodiment of the present invention.
14 is a block diagram schematically illustrating a semiconductor drive according to an exemplary embodiment of the present invention.
15 is a block diagram schematically showing storage using the semiconductor drive shown in FIG.
16 is a block diagram schematically showing a storage server using the semiconductor drive shown in FIG.
Figures 17-19 are diagrams schematically illustrating systems according to exemplary embodiments of the present invention.
20 to 24 are diagrams schematically showing other systems to which a nonvolatile memory device according to exemplary embodiments of the present invention is applied.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. In addition, like reference numerals designate like elements throughout the specification.

The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Also, the expression " coupled / connected " is used to mean either directly connected to another component or indirectly connected through another component. The singular forms herein include plural forms unless the context clearly dictates otherwise. Also, components, steps, operations and elements referred to in the specification as " comprises " or " comprising " mean the presence or addition of one or more other components, steps, operations, elements and devices.

Hereinafter, exemplary embodiments will be described in detail with reference to the drawings.

1 is a block diagram that schematically illustrates a flash memory device in accordance with an exemplary embodiment of the present invention.

1, the flash memory device is, for example, a NAND flash memory device. However, it will be appreciated that the invention is not limited to flash memory devices. For example, the present invention can be applied to a PRAM (Phase Change Random Access Memory), a MRAM (Magnetoresistive Random Access Memory), a Ferroelectric Random Access Memory (FRAM), a Resistance Random Access Memory: RRAM, Spin Transfer Torque Random Access Memory (STT-RAM), and the like.

The flash memory device includes a memory cell array 100 having memory cells arranged in rows (word lines: WL) and columns (bit lines: BL). Each memory cell stores 1-bit data or M-bit (multi-bit) data (M is an integer of 2 or greater). When each memory cell stores 1-bit data, the memory cells belonging to each row of the memory cell array 100 will constitute a memory space. When each memory cell stores M-bit data, the memory cells belonging to each row of the memory cell array 100 will constitute memory spaces corresponding to a plurality of pages, respectively. Each memory cell may be implemented as a memory cell having a charge storage layer, such as a floating gate or charge trap layer, or a memory cell having a variable resistive element. The memory cell array 100 may be a single-layer array structure (also referred to as a two-dimensional array structure) or a multi-layer array structure (or a vertical or stacked three- Quot;).

The row select circuit 200 is controlled by the control logic 300 and is configured to perform select and drive operations on the rows of the memory cell array 100. [ The control logic 300 is configured to generally control the operation of the flash memory device. The page buffer circuit 400 is controlled by the control logic 300 and operates as a sense amplifier or as a write driver depending on the mode of operation. For example, during a read operation, the page buffer circuit 400 operates as a sense amplifier that senses data from the memory cells of the selected row. During a program operation, the page buffer circuit 400 operates as a write driver that drives memory cells of a selected row according to program data. The page buffer circuit 400 includes page buffers that correspond to bit lines or to bit line pairs, respectively. When each of the memory cells stores multi-bit data, each page buffer of the page buffer circuit 400 will be configured to have two or more latches.

1, the column select circuit 500 is controlled by the control logic 300 and sequentially selects the columns (or page buffers) in a predetermined unit during a read / program operation. The randomizing and derandomizing circuit 600 is configured to randomize data (i.e., data to be programmed or original data) to be transferred through the input / output interface 700 under the control of the control logic 300. The randomizing and derandomizing circuit 600 supplies the data (i.e., randomized data) of the page buffer circuit 400, which is transmitted through the column selecting circuit 500 under the control of the control logic 300, . The randomizing and de-randomizing circuit 600 according to the exemplary embodiment of the present invention is capable of storing not only full-page data but also random data (e.g., spare area data, sector data, Data smaller than the page data, data smaller than the sector data, etc.), for example, to perform randomization and de-randomization operations. This will be described in detail later.

The memory cell has either of 2 ^N threshold voltage distributions (N representing the number of data bits stored in the memory cell) depending on the amount of charges stored in the charge storage means. The threshold voltage (or threshold voltage distribution) of a memory cell will change due to the coupling between adjacent memory cells, which is referred to as word line coupling. The data randomization of the present invention makes it possible to reduce variations in the threshold voltages of memory cells caused by word line coupling. In other words, since the states of the memory cells are uniformly distributed, the degree of word line coupling between the memory cells will be relatively relaxed as compared to before data randomization. That is, a change in the threshold voltages of the memory cells will be suppressed. This means improvement of reading margin, that is, improvement of reliability.

In some embodiments, randomization and de-randomization operations may be performed selectively. For example, when access to specific data or access to a particular area is requested, the randomization and de-randomization circuitry 600 may be configured not to perform randomization and de-randomization operations. The randomizing and de-randomizing circuit 600 may be configured to transmit the data input through the input / output interface 700 to the page buffer circuit 400 without performing the randomizing operation. Randomization of the data loaded into the page buffer circuit 400 may then be performed via the randomization and de-randomization circuit 600 under the control of the control logic 300. [

FIG. 2 is a view showing an example of configuring the memory cell array shown in FIG. 1 as memory blocks for an all-bit line memory structure or an odd-even memory structure. Exemplary structures of the memory cell array 100 will now be described. As an example, a NAND flash memory device in which the memory cell array 100 is divided into 1024 memory blocks will be described. The data stored in each memory block can be erased simultaneously or erased in units of memory sub-blocks. In one embodiment, the memory block or memory sub-block is the smallest unit of storage elements that are simultaneously erased. Each memory block has a plurality of columns each corresponding to, for example, bit lines (e.g., 1 KB of bit lines). In one embodiment, referred to as an all bit line (ABL) structure, all bit lines of a memory block may be selected simultaneously during read and program operations. The storage elements belonging to the word line selected by the row selection circuit 200 and connected to all the bit lines can be programmed simultaneously.

In an exemplary embodiment, a plurality of storage elements in the same column are serially connected to form a NAND string. One terminal of the NAND string is connected to the corresponding bit line through the selection transistor controlled by the string selection line SSL and the other terminal is connected to the common source line CSL through the selection transistor controlled by the ground selection line GSL. .

In another exemplary embodiment, referred to as an odd-even architecture, the bit lines are divided into even bit lines BLe and odd bit lines BLo. In the odd / even bit line structure, the storage elements belonging to the selected word line and connected to the odd bit lines are programmed at the first time, while the storage elements connected to the even bit lines belong to the common word line, Lt; / RTI >

3 is a block diagram that schematically illustrates the randomization and de-randomization circuitry shown in FIG. 1 in accordance with one embodiment of the present invention.

3, a randomizing and de-randomizing circuit 600 according to an embodiment of the present invention includes a clock generator 610, a selector 620, a pseudo-random sequence generator 630, a free-run detector 640, and a mixer 650. In this case, the clock generator 610, the selector 620, the pseudo-random sequence generator 630, and the pre-run detector 630 may generate the random sequence data RSD sequentially provided to the mixer 650 A sequence generation block 660 will be constructed. The group of sequentially generated random sequence data will constitute a random sequence (RS).

Clock generator 610 may be configured to generate a clock signal CLK. The selector 620 selects one of the input signals CLK, RE / WE in response to the pre-run signal FRS output from the pre-run detector 640 as a selection signal. For example, when the pre-run signal FRS is activated, the selector 620 will select the clock signal CLK from the clock generator 610 as the output signal. When the pre-run signal FRS is deactivated, the selector 620 will select the read / write enable signal RE / WE to be toggled upon data input / output of the read / write operation as the output signal. The signal (CLK or RE / WE) selected by the selector 620 will be provided to the pseudo-random sequence generator 630 as the random sequence clock signal CLK_RS. The pseudo-random sequence generator 630 operates in response to the random sequence clock signal CLK_RS and sequentially generates random sequence data RSD using a predetermined seed. The random sequence RS may, for example, consist of a series of data bits. Each data bit of the random sequence RS will be provided to the mixer 650 as random sequence data. As another example, the random sequence RS may be comprised of a series of data bit groups, where each data bit group may be composed of two or more data bits.

Here, the predetermined seed may be determined based on, for example, a page address. In other words, the seed will be determined on a page-by-page basis. However, it will be appreciated that the seed may be determined on a block-by-block basis. That is, the seed will have a unique value assigned to each page. Alternatively, constants corresponding respectively to pages may be used as seeds, respectively. Alternatively, the predetermined seed may be determined on a sector-by-sector basis of a page. However, it will be appreciated that the seed determination scheme is not limited to that disclosed herein. When access to any page is requested, the seed will be provided to the pseudo-random sequence generator 630 based on the page address. This means that a seed having a constant value is provided to the pseudo-random sequence generator 630 when access to any page is requested. Hereinafter, the random sequence data RSD for substantially randomizing the first data provided to the mixer 650 will be referred to as 'initial random sequence data' (initial RSD). The seed necessary for the actual randomization of the first data provided to the mixer 650 or for generating the initial random sequence data is called an " initial seed ".

In an exemplary embodiment, the pseudo-random sequence generator 630 may be implemented with a linear feedback shift register (LFSR) comprised of one shift register and one or more XOR logic gates. However, it will be appreciated that pseudo-random sequence generator 630 may be implemented as a pseudo-random number (PN) sequence generator, a cyclic redundancy code (CRC) generator, or the like.

3, the pre-run detector 640 generates a free-run signal (FRS) based on the column offset value. In an exemplary embodiment, the column offset value will be the value of the column address provided in the access request. The column offset value will depend on whether the requested access is associated with full-page data or not with random data. For example, when a read / write operation to full-page data is required, the column offset value will be '0'. When a read / write operation for random data is required, the column offset value will be larger than '0'. In the case of the present invention, the location at which data will be read according to an access request, i.e., the access point, will be variously determined through the column address. For example, the first access point of the page data may be determined by a column address having a value of '0', and the remaining access points of the page data may be determined by a column address having a value greater than '0'. Here, the position at which the data is to be read may include the column position of the page buffer circuit 400 or the column position of one page. Likewise, the location at which data will be stored in response to an access request, i. E. The access point, will be variously determined via the column address. For example, the first access point of the page data may be determined by a column address having a value of '0', and the remaining access points of the page data may be determined by a column address having a value greater than '0'. The column offset value is also referred to as an 'offset address'.

The pre-run detector 640 will include a counter 641 and a comparator 642. The counter 641 will operate in synchronization with, for example, the clock signal CLK generated by the clock generator 610. The comparator 642 compares the count value of the counter 641 with the column offset value and generates the pre-run signal FRS according to the comparison result. For example, the pre-run signal FRS will be inactive when the initial value of the counter 641 and the column offset value match each other. The pre-run signal FRS will be activated when the initial value of the counter 641 and the column offset value are different. In the latter case, the comparator 642 will deactivate the pre-run signal FRS when the count value of the counter 641 reaches the column offset value. At this time, the counter 641 will not operate according to the deactivation of the pre-run signal FRS.

The counter 641 does not operate when the column offset value is '0' in a read / write operation. That is, when the column offset value of '0' coincides with the initial value ('0') of the counter 641, the operation of the counter 640 will not be performed. At this time, the comparator 642 of the pre-run detector 640 deactivates the pre-run signal FRS. Deactivation of the pre-run signal (FRS) implies that the requested access is associated with full-page data. In this case, the read / write enable signal RE / WE, which is toggled upon data input / output, will be provided to the pseudo-random sequence generator 630 via the selector 620 as the random sequence clock signal CLK_RS. The read / write enable signal RE / WE will be toggled to provide data to the mixer 650 upon a read / write request.

The counter 641 will perform a count operation when the column offset value is not '0' in a read / write operation. That is, when the column offset value does not match the initial value of the counter 641, the counter 640 will perform the counting operation in synchronization with the clock signal CLK. At this time, the comparator 642 of the pre-run detector 640 activates the pre-run signal FRS. Activation of the pre-run signal (FRS) implies that the requested access is associated with random data. In this case, the clock signal CLK generated by the clock generator 610 will be provided to the pseudo-random sequence generator 630 via the selector 620 as the random sequence clock signal CLK_RS. While the clock signal CLK generated by the clock generator 610 is provided to the pseudo-random sequence generator 630 via the selector 620 as the random sequence clock signal CLK_RS, the mixer 650 is provided with data . The pseudo-random sequence generator 630 will sequentially generate the random sequence data in synchronization with the clock signal CLK provided from the clock generator 610, even though no data is provided to the mixer 650. [ An operation for generating initial random sequence data for substantial randomization of the first data is referred to as a pre-run operation. The pre-run detector 640 deactivates the pre-run signal FRS when the count value reaches the column offset value. When the state of the pre-run signal FRS transitions from the active state to the inactive state, the read / write enable signal RE / WE at the data input / output outputs the random sequence clock signal CLK_RS to the selector 620 Random sequence generator 630 through the pseudo-random sequence generator 630. At this time, the operation of the counter will stop according to the deactivation of the pre-run signal FRS.

The mixer 650 logically combines the random sequence data RSD and the data (or the data input to the random sequence and the mixer 650), and outputs the combined data as randomized / de-randomized data something to do. For example, in a read operation, the mixer 650 logically combines the randomized data and the random sequence data RSD provided through the column selection circuit 500, and outputs the combined data as the de-randomized data To the input / output interface 700. In the write operation, the mixer 650 logically combines the data provided through the input / output interface 700 with the random sequence data (RSD), and outputs the combined data as the randomized data to the column selection circuit 500 will be. When data is provided in byte units by the mixer 650, the random sequence data bits will be logically combined with the data bits to be read / programmed, respectively.

Here, the pre-run signal FRS has one of an active-high level and an active-low level depending on whether the requested access is a random data access.

In an exemplary embodiment, the mixer 650 may comprise, for example, XOR logic. However, it will be appreciated that the configuration of the mixer 650 is not limited to that disclosed herein. It will also be appreciated that the configuration of the pre-run detector 640 is not limited to what is disclosed herein.

4 is a timing diagram schematically illustrating a read operation of a flash memory device according to an exemplary embodiment of the present invention. Hereinafter, a read operation of a flash memory device according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.

The read operation will be performed according to the input of a series of instructions and addresses. For example, as shown in Fig. 4, the first instruction 00h, the address C1C2R1R2R3, and the second instruction 30h will be sequentially provided to the flash memory device. The provided address C1C2R1R2R3 will include column address C1C2 and row address R1R2R3. Assume that the column offset value that is the value of the column address C1C2 is not '0'. Since the column offset value is not '0', the initial seed necessary for generating the initial random sequence data is a random sequence (ie, a seed assigned to the row address R1R2R3) determined according to the row address R1R2R3 Run operation of the generation block 650. [ More specifically, it is as follows. However, when the randomization is applied in units smaller than one page, the column address may be referred to.

)는 tR 시간 동안 로우 레벨로 유지될 것이다. 이와 동시에, 프리-런 검출기(640)는 열 오프셋 값이 '0'가 아니기 때문에 프리-런 신호(FRS)를 활성화시킨다. 즉, 열 오프셋 값이 카운터(641)의 초기값과 일치하지 않을 때, 프리-런 검출기(640)는 프리-런 신호(FRS)를 활성화시킨다. 이는 선택기(620)를 통해 클록 발생기(610)에 의해서 생성된 클록 신호(CLK)가 선택됨을 의미한다. 클록 신호(CLK)는 랜덤 시퀀스 클록 신호(CLK_RS)로서 유사-랜덤 시퀀스 발생기(630)로 제공될 것이다. 유사-랜덤 시퀀스 발생기(630)는 행 어드레스(R1R2R3)에 따라 결정되는 시드를 이용하여 랜덤 시퀀스 데이터를 생성할 것이다. 즉, 초기 랜덤 시퀀스 데이터(또는, 초기 시드)를 생성하기 위한 프리-런 동작이 수행될 것이다. 카운터(641)는 제 2 명령(30h)의 입력시 클록 신호(CLK)에 따라 카운트하기 시작할 것이다.When the second instruction 30h is provided to the flash memory device, the page buffer circuit 400 reads data from the memory cell array 100 in response to the control of the control logic 300, for tR time. As shown in Fig. 4, the register / busy signal

) Will remain at the low level for tR time. At the same time, the pre-run detector 640 activates the pre-run signal FRS since the column offset value is not '0'. That is, when the column offset value does not match the initial value of the counter 641, the pre-run detector 640 activates the pre-run signal FRS. This means that the clock signal CLK generated by the clock generator 610 via the selector 620 is selected. The clock signal CLK will be provided to the pseudo-random sequence generator 630 as the random sequence clock signal CLK_RS. The pseudo-random sequence generator 630 will generate random sequence data using a seed determined according to the row address R1R2R3. That is, a pre-run operation for generating initial random sequence data (or initial seed) will be performed. The counter 641 will start counting according to the clock signal CLK upon input of the second instruction 30h.

When the count value of the counter 641 reaches the column offset value, the pre-run detector 640 deactivates the pre-run signal FRS. As the pre-run signal (FRS) is deactivated, the supply of the clock signal to the pseudo-random sequence generator 630 will be stopped. That is, the pre-run operation will be stopped. At this time, the pseudo-random sequence generator 630 will be set to the initial seed necessary for randomizing the first data. After the tR time has elapsed, the data (i.e., the randomized data) of the page buffer circuit 400 is randomized through the column selection circuit 500 according to the toggle of the read / write enable signal RE / To the de-randomization circuit 600. At this time, the pseudo-random sequence generator 630 will sequentially generate the random sequence data RSD in synchronization with the toggle of the read / write enable signal RE / WE. The mixer 650 logically combines the initial random sequence data RSD with the data selected by the column address C1C2 as an access pointer and the combined data is de-randomized through the input / . The de-randomization operation will be performed until all of the access-requested data is output.

)는 tR 시간 동안 하이 레벨로 유지될 것이다. 예를 들면, 제 1 명령(05h), 어드레스(C1C2), 그리고 제 2 명령(E0h)이 플래시 메모리 장치로 순차적으로 제공될 것이다. 이때, 제공된 어드레스(C1C2)는 단지 열 어드레스(C1C2)만을 포함할 것이다. 열 어드레스(C1C2)의 값인 열 오프셋 값이 '0'이 아니라고 가정하자. 열 오프셋 값이 '0'가 아니기 때문에, 초기 랜덤 시퀀스 데이터를 생성하는 데 필요한 초기 시드는 이전에 입력된 행 어드레스(R1R2R3)에 따라 결정되는 시드를 이용하여 랜덤 시퀀스 발생 블록(650)의 프리-런 동작을 통해 생성될 것이다. 프리-런 동작을 통해 초기 랜덤 시퀀스 데이터(또는, 초기 시드)를 생성하는 동작과 디-랜덤화 동작은 앞서 설명된 것과 실질적으로 동일하며, 그것에 대한 설명은 그러므로 생략될 것이다.The data stored in the page buffer circuit 400 may be additionally externally provided using a series of instructions and addresses. In this case, as shown in Fig. 4, the register / busy signal

) Will remain at the high level for tR time. For example, the first instruction 05h, the address C1C2, and the second instruction E0h will be sequentially provided to the flash memory device. At this time, the provided address C1C2 will contain only the column address C1C2. Assume that the column offset value that is the value of the column address C1C2 is not '0'. Since the column offset value is not " 0 ", the initial seed necessary for generating the initial random sequence data is a pre-run of the random sequence generating block 650 using the seed determined according to the previously input row address R1R2R3 Operation. The operation of generating the initial random sequence data (or the initial seed) through the pre-run operation and the de-randomizing operation are substantially the same as those described above, and the description thereof will be omitted.

As shown in Fig. 4, after the second instruction E0h is input and the predetermined time required to generate the initial seed has elapsed, the data will be output. The time it takes to generate the initial seed (e.g., 13us) is shorter than the tR time (e.g., 30us).

As described above, even if access to random data (or random data access) is requested, random data is generated by generating an initial seed (or initial random sequence data) using an offset value (or an offset address) It is possible to de-randomize.

5 is a timing diagram schematically illustrating a read operation of a flash memory device according to another exemplary embodiment of the present invention. Hereinafter, a read operation of a flash memory device according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.

The read operation will be performed according to the input of a series of instructions and addresses. For example, as shown in Fig. 5, the first instruction 00h, the address C1C2R1R2R3, and the second instruction 30h will be sequentially provided to the flash memory device. The address C1C2R1R2R3 will include column address C1C2 and row address R1R2R3. And a column offset value that is a value of the column address C1C2 is '0'. Since the column offset value is '0', the pre-run operation for generating the initial seed is not performed.

)는 tR 시간 동안 하이 레벨로 유지될 것이다. 랜덤화 및 디-랜덤화 회로(600)는 입력된 행 어드레스(R1R2R3)에 따라 결정된 시드(즉, 초기 시드)를 이용하여 랜덤 시퀀스 데이터(RSD)를 순차적으로 생성하고, 랜덤 시퀀스 데이터(RSD)와 페이지 버퍼 회로(400)에 의해서 읽혀진 데이터를 논리적으로 조합할 것이다. 조합된 데이터는 디-랜덤화된 데이터로서 입출력 회로(700)를 통해 외부로 출력될 것이다.When the second instruction 30h is provided to the flash memory device, the page buffer circuit 400 reads data from the memory cell array 100 in response to the control of the control logic 300, for tR time. As shown in Fig. 5, the register / busy signal

) Will remain at the high level for tR time. The randomizing and de-randomizing circuit 600 sequentially generates the random sequence data RSD using the seed determined according to the inputted row address R1R2R3 (i.e., the initial seed), and outputs the random sequence data RSD, And the data read by the page buffer circuit 400 will be logically combined. The combined data will be output to the outside through the input / output circuit 700 as the de-randomized data.

6 is a timing diagram schematically illustrating a write operation of a flash memory device according to an exemplary embodiment of the present invention. Hereinafter, a writing operation of a flash memory device according to an exemplary embodiment of the invention will be described in detail with reference to the drawings.

The write operation will be performed according to the input of a series of instructions, data, and address. For example, as shown in Fig. 6, the first instruction 80h, the address C1C2R1R2R3, the data, and the second instruction 10h will be sequentially provided to the flash memory device. The address C1C2R1R2R3 will include column address C1C2 and row address R1R2R3. Assume that the column offset value that is the value of the column address C1C2 is not '0'. Since the column offset value is not '0', the initial seed necessary for generating the initial random sequence data is generated through the pre-run operation of the random sequence generation block 650 using a seed determined according to the row address R1R2R3 Will be. More specifically, it is as follows.

When the input of the address is completed, the pre-run detector 640 will generate the pre-run signal FRS according to the column offset value. Since the column offset value is not '0', the pre-run detector 640 activates the pre-run signal FRS. This means that the clock signal CLK generated by the clock generator 610 via the selector 620 is selected. The clock signal CLK will be provided to the pseudo-random sequence generator 630 as the random sequence clock signal CLK_RS. The pseudo-random sequence generator 630 will sequentially generate the random sequence data RSD using a seed determined according to the row address R1R2R3. That is, a pre-run operation for generating initial random sequence data (or initial seed) will be performed. When the count value of the counter 641 reaches the column offset value, the pre-run detector 640 deactivates the pre-run signal FRS. As the pre-run signal (FRS) is deactivated, the supply of the clock signal to the pseudo-random sequence generator 630 will be stopped. That is, the pre-run operation will be stopped. At this time, the pseudo-random sequence generator 630 will be set to the initial seed necessary for randomizing the first data.

In an exemplary embodiment, during a write operation, the counter 641 will begin counting following the address input.

)는 하이 레벨에서 로우 레벨로 천이할 것이다. 레지/비지 신호(

)의 로우-레벨 구간 동안, 즉, tPGM 시간 동안, 페이지 버퍼 회로(400)에 저장된 데이터(즉, 랜덤화된 데이터)는 메모리 셀 어레이(100)에 저장될 것이다.When generation of the initial seed is completed, the data to be programmed is transferred to the randomizing and de-randomizing circuit 600 through the input / output interface 700 of the flash memory device according to the toggle of the read / write enable signal RE / WE Will be provided sequentially. At this time, the pseudo-random sequence generator 630 will sequentially generate the random sequence data RSD in synchronization with the toggle of the read / write enable signal RE / WE. The mixer 650 logically combines the initial random sequence data and the data provided through the input / output interface circuit 700, and the combined data is randomized by the page buffer circuit 400 through the column selection circuit 500, Lt; / RTI > The randomizing operation will be performed until all of the data to be programmed is transferred to the page buffer circuit 400. [ Then, when the second instruction 10h is provided to the flash memory device, as shown in Fig. 6, the register / busy signal

Will transition from a high level to a low level. Register / busy signal

(I.e., randomized data) stored in the page buffer circuit 400 will be stored in the memory cell array 100 during a low-level period of the memory cell array 100, i.e., during the tPGM time.

As described above, even if access to random data (i.e., random data access) is requested, randomizing random data to be programmed by generating an initial seed (or initial random sequence data) using the offset address as a column offset value It is possible.

Although not shown in the figure, when the thermal offset value is '0' in a write operation, a pre-run operation for generating an initial seed will not be performed. In this case, the data and the second instruction 10h will be continuously provided to the flash memory device following the address input.

In an exemplary embodiment, the time taken to create the initial seed will depend on the column offset value. Therefore, the point of taking data in the read operation described in FIG. 4 and the point of providing data in the write operation described in FIG. 6 can be set based on the maximum time taken to generate the initial seed.

Figure 7 is a block diagram that schematically illustrates the randomization and de-randomization circuitry shown in Figure 1 according to another embodiment of the present invention.

Referring to FIG. 7, the randomizing and de-randomizing circuit 600a according to another embodiment of the present invention includes a clock generator 610, a selector 620, a pseudo-random sequence generator 630 a, a free-run detector 640 a, and a mixer 650. Here, the clock generator 610, the selector 620, and the mixer 650 are substantially the same as those shown in FIG. 3, and the description thereof will therefore be omitted.

The pseudo-random binary sequence 630a of the randomizing and de-randomizing circuit 600a will operate in either an acceleration mode or a normal mode according to the flag signal ACC_EN indicating the acceleration mode. For example, when the flag signal ACC_EN is activated, the pseudo-random binary sequence 630a will operate in the acceleration mode. When the flag signal ACC_EN is deactivated, the pseudo-random binary sequence 630a will operate in the normal mode. In the acceleration mode, random sequence data generated over a plurality of clock cycles will be generated over one clock cycle. This means that the time to generate the initial seed is shortened when the column offset value is not " 0 ".

Here, activation and deactivation of the flag signal ACC_EN indicating the acceleration mode can be determined based on the trim information of the flash memory device. Alternatively, activation and deactivation of the flag signal ACC_EN indicating the acceleration mode may be determined by the controller controlling the flash memory device. However, it will be appreciated that the activation and deactivation of the flag signal ACC_EN is not limited to what is disclosed herein. With the activation of the flag signal, the speed information will also be determined.

The pre-run detector 640a includes a counter 641a, a comparator 642a, and a divider 643a. The counter 641a will be configured to operate in synchronization with the clock signal CLK. The frequency divider 643a operates in response to the flag signal ACC_EN indicating the acceleration mode and transfers the value of the column offset to the comparator 642a as it is or the value obtained by dividing the column offset value by the speed information N by a comparator 642a ). For example, when the flag signal ACC_EN indicates normal mode, the divider 643a will deliver the column offset value to the divider 643a without modification. When the flag signal ACC_EN indicates the acceleration mode, the divider 643a divides the column offset value into the multiplication information N and transmits the resultant value to the comparator 642a. For example, when the column offset value is '1000' and the speed information indicates N-times speed, the output of the frequency divider 643a will be a value of 1000 / N.

The comparator 642a compares the count value of the counter 641a with the output of the divider 643a and generates the pre-run signal FRS according to the comparison result. For example, the pre-run signal FRS will be deactivated when the initial value of the counter 641 and the output of the divider 643 match each other. The pre-run signal FRS will be activated when the initial value of the counter 641a and the output of the divider 643a are different. In the latter case, the comparator 642a will deactivate the pre-run signal FRS when the count value of the counter 641a reaches the output value of the divider 643a. At this time, the counter 641a will not operate according to the deactivation of the pre-run signal FRS.

FIG. 8 is a block diagram schematically showing the pseudo-random sequence generator shown in FIG. 7, and FIG. 9 is a diagram showing initial seed values generated using polynomials of the pseudo-random sequence generator shown in FIG.

8, the pseudo-random sequence generator 630a includes a plurality of flip-flops (FF0 to FF10) operating in response to a random sequence clock signal (CLK_RS), a plurality SEL0 to SEL10, and a plurality of XOR logic 631, 632, 633, and 634, and are coupled as shown. The pseudo-random sequence generator 630a shown in FIG. 8 is configured to satisfy a polynomial such as (X ¹¹ + X ¹⁰ +1), and operates in the normal mode or the acceleration mode according to the flag signal ACC_EN. When the flag signal ACC_EN is a low-level signal indicative of a normal mode, the inputs D of the flip-flops FF0 to FF10 are supplied with normal-mode values ( X ¹⁰ ^ X ⁰ , X ¹⁰ ~ X ¹ ), respectively. In this case, in Fig. 9, when the column offset value increases according to the toggle of the clock signal CLK, the initial seed will also be generated sequentially. For example, assume that the column offset value is '9'. Under this assumption, when the clock signal CLK is toggled 9 times, the comparator 642a compares the output of the divider 643a, i.e., the non-divided column offset value, with the count value of the counter 641a, (FRS). At this time, an initial seed (X ¹⁰ ^ X ⁰ ^ X ¹ ^ X ² ^ X ³ ^ X ⁴ ^ X ⁵ ^ X ⁶ ^ X ⁷ ^ X ⁸ , X ¹⁰ ^ X ⁰ ^ ^{^ X 1 ^ X 2 ^ X} 3 ^ X 4 ^ X 5 ^ X 6 ^ X 7, X 10 ^ X 0 ^ X 1 ^ X 2 ^ X 3 ^ X 4 ^ X 5 ^ X 6, X 10 ^ X ^{0 ^ X 1 ^ X 2 ^} X 3 ^ X 4 ^ X 5, X 10 ^ X 0 ^ X 1 ^ X 2 ^ X 3 ^ X 4, X 10 ^ X 0 ^ X 1 ^ X 2 ^ X 3, X ¹⁰ ^ X ⁰ ^ X ¹ ^ X ² , X ¹⁰ ^ X ⁰ ^ X ¹ , X ¹⁰ ^ X ⁰ , X ¹⁰ , X ⁹ will be set in the pseudo-random sequence generator 630.

When the flag signal ACC_EN is a high-level signal indicative of the acceleration mode, the inputs D of the flip-flops FF0 to FF10 are supplied with the acceleration-mode values ( X ¹⁰ ^ X ⁰ ^ X ¹ ^ X ² , X ¹⁰ ^ X ⁰ ^ X ¹ , X ¹⁰ ^ X ⁰ , and X ¹⁰ ~X ³ , respectively. In this case, when the column offset value increases by three times according to the toggle of the clock signal CLK, the initial seeds indicated by arrows in Fig. 9 will be sequentially generated. For example, assume that the column offset value is '9'. Under this assumption, if the clock signal CLK is toggled three times, the comparator 642a will compare the output of the divider 643a, i.e., the divided value 9/3 = 3, with the count value of the counter 641a Deactivates the pre-run signal (FRS). At this time, an initial seed (X ¹⁰ ^ X ⁰ ^ X ¹ ^ X ² ^ X ³ ^ X ⁴ ^ X ⁵ ^ X ⁶ ^ X ⁷ ^ X ⁸ , X ¹⁰ ^ X ⁰ ^ ^{^ X 1 ^ X 2 ^ X} 3 ^ X 4 ^ X 5 ^ X 6 ^ X 7, X 10 ^ X 0 ^ X 1 ^ X 2 ^ X 3 ^ X 4 ^ X 5 ^ X 6, X 10 ^ X ^{0 ^ X 1 ^ X 2 ^} X 3 ^ X 4 ^ X 5, X 10 ^ X 0 ^ X 1 ^ X 2 ^ X 3 ^ X 4, X 10 ^ X 0 ^ X 1 ^ X 2 ^ X 3, X ¹⁰ ^ X ⁰ ^ X ¹ ^ X ² , X ¹⁰ ^ X ⁰ ^ X ¹ , X ¹⁰ ^ X ⁰ , X ¹⁰ , X ⁹ will be set in the pseudo-random sequence generator 630.

It will be appreciated that the configuration of the pseudo-random sequence generator 630a shown in FIG. 8 can be variously changed depending on the speed. In the case of the random sequence generation block shown in Fig. 8, the time required to generate the initial seed (or the initial random sequence data) can be shortened.

10 is a block diagram schematically illustrating a pseudo-random sequence generator according to another embodiment of the present invention.

Prior to the description, in the randomizing and de-randomizing circuit 600b shown in FIG. 10, components having the same functions as those shown in FIG. 3 are denoted by the same reference numerals, Will be.

Referring to FIG. 10, the randomizing and de-randomizing circuit 600b will include an initial seed generator 670. The initial seed generator 670 will generate an initial seed based on the thermal offset value. Assume that the pseudo-random sequence generator 630 is implemented according to the polynomial (X ¹¹ + X ¹⁰ +1) for generating the initial seeds shown in FIG. According to this assumption, it is possible to calculate / predict the initial seed values of the pseudo-random sequence generator 630 according to the column offset value, as can be seen in Fig. Thus, the initial seed generator 670 will be implemented in hardware so that the calculated / predicted initial seed values are generated according to the terms shown in FIG. The pseudo-random sequence generator 630 and the initial seed generator 670 will constitute a block that generates a random sequence. In the case of the random sequence generation block shown in FIG. 10, it is possible to shorten the time required to generate an initial seed corresponding to each column offset value or to generate initial random sequence data (initial RSD).

The randomizing and de-randomizing circuit 600b shown in FIG. 10 operates substantially the same as that described in FIGS. 4 to 6 except for the differences described above, and the description thereof will therefore be omitted.

In an exemplary embodiment, the random sequence clock signal CLK_RS applied to the quasi-random sequence generator 630 may be a read / write enable signal that is toggled upon data input / output. Alternatively, the random sequence clock signal CLK_RS applied to the quasi-random sequence generator 630 may be a clock signal generated upon data input / output.

FIG. 11A is a flowchart for explaining a randomizing and de-randomizing method of a flash memory device according to an exemplary embodiment of the present invention, FIG. 11B is a flowchart illustrating a randomizing and flashing of a flash memory device according to an exemplary embodiment of the present invention, And schematically illustrates a de-randomization scheme.

First, in step S100, it is determined whether or not the requested access is a random data access. In other words, it will be determined whether or not the data is stored as an access pointer from the starting point of the memory space (for example, composed of memory cells constituting one page). If the requested access is determined to be a random data access (or if it is determined that the data is stored from one of the remaining access points except for the starting point of the memory space as an access point), the procedure will proceed to step SlO. In step S110, an initial seed (or initial random sequence data RSD) corresponding to the random data will be generated using the seed. For example, as shown in FIG. 11B, when the column offset value of the requested access is not '0', that is, when the randomization / de-randomization is performed from the i-th data Di, An initial seed will be generated through the initial seed generation operation described in 10. After the initial seed is generated, a random sequence (RSDi to RSDn + 1) is generated using the thus generated initial seed in step S120, and randomization / de-randomization is performed using the random sequences RSDi to RSDn + The operation will be performed. The randomized data will be stored in the array 100 via the page buffer circuit 400. The de-randomized data will be provided to the outside (for example, a controller) through the input / output interface 700. Then the procedure will end.

In an exemplary embodiment, steps S100 and S110 may constitute a method for generating an initial seed for randomizing data to be stored in a memory space. In addition, steps S100 and S110 may constitute a method for generating an initial seed for de-randomizing data to be read from the memory space.

If it is determined that the requested access is not a random data access, the procedure will proceed to step S130. For example, as shown in FIG. 11B, when the column offset value of the requested access is '0', that is, when the randomization / de-randomization is performed from the first data D0, (RSD0 to RSDn + 1) are generated based on the seed determined according to the page address without the initial seed generation operation described in the above description. The random sequence (RSD0 to RSDn + 1) A randomizing operation will be performed. The randomized data will be stored in the array 100 via the page buffer circuit 400. The de-randomized data will be provided to the outside (for example, a controller) through the input / output interface 700. Then the procedure will end.

In the exemplary embodiment, the randomization / de-randomization performed through the mixer 650 is performed in binary units, as well as in a multi-value state (not shown) via a bit-wise XOR operation Lt; / RTI >

12 is a block diagram that schematically illustrates a memory system in accordance with an exemplary embodiment of the present invention.

Referring to FIG. 12, the memory system 3000 will include at least one flash memory 1000 and a controller 2000. The flash memory 1000 operates under the control of the controller 2000 and will be used as a storage medium. The controller 2000 will be configured to control the flash memory 1000. The flash memory 1000 will include a randomization and de-randomization circuit 1100. The flash memory 1000 shown in FIG. 12 is configured substantially the same as that shown in FIG. 1, and the description thereof will therefore be omitted. The controller 2000 will be configured to randomize the data to be stored in the flash memory 1000 and to add ECC data to the randomized data.

The controller 2000 will include a first interface 2100, a second interface 2200, a processing unit 2300, a buffer memory 2400, and an ECC block 2500. The first interface 2100 is configured to interface with an external (e.g., host), and the second interface 2200 may be configured to interface with a flash memory 2200. The processing unit 2300 may be configured to control the overall operation of the controller 2000. The buffer memory 2400 may be configured to store data to be stored in the flash memory 1000 or data read from the flash memory 1000. The ECC block 2500 will generate ECC data based on the data output from the buffer memory 2400. The ECC block 2600 will perform error detection and correction operations on the data read from the flash memory 1000 based on the ECC data. The ECC data may be stored in the same page as the data to be stored in the flash memory 1000 or in an area different from the data to be stored in the flash memory 1000. [

In the case of the memory system shown in FIG. 12, the write operation will include generating ECC data based on data to be stored in the flash memory 1000, and randomizing data to be stored in the flash memory 1000. The read operation will include de-randomizing the read data and performing an error detection and correction operation on the de-randomized data based on the ECC data. Randomization / de-randomization for ECC may optionally be performed.

In an exemplary embodiment, the first interface 2100 may be comprised of a combination of one or more of computer bus standards, storage bus standards, iFCPPeripheral bus standards, and the like. Computer bus standards include computer bus standards such as S-100 bus, Mbus, Smbus, Q-Bus, ISA, Zorro II, Zorro III, CAMAC, FASTBUS, LPC, EISA, VME, VXI, NuBus, TURBOchannel, , VLB, PCI, PXI, HP GSC bus, CoreConnect, InfiniBand, UPA, PCI-X, AGP, PCIe, Intel QuickPath Interconnect, Hyper Transport, Storage bus standards include ST-506, ESDI, SMD, Parallel ATA, DMA, SSA, HIPPI, USB MSC, FireWire (1394), Serial ATA, eSATA, SCSI, Parallel SCSI, Serial Attached SCSI, Fiber Channel, iSCSI, SAS, RapidIO, FCIP, and the like. The iFCPPeripheral bus standards include the Apple Desktop Bus, HIL, MIDI, Multibus, RS-232, DMX512-A, EIA / RS-422, IEEE-1284, UNI / O, 1-Wire, I2C, SPI, EIA / RS-485, USB, Camera Link, External PCIe, Light Peak, Multidrop Bus, etc.

13 is a block diagram schematically illustrating a memory system according to another exemplary embodiment of the present invention.

Referring to FIG. 13, the memory system 3000a will include at least one flash memory 1000a and a controller 2000a. The flash memory 1000a operates under the control of the controller 2000a and will be used as a storage medium. The flash memory 1000a shown in Fig. 13 will not include the above-mentioned randomizing and de-randomizing circuit. The controller 2000a will be configured to control the flash memory 1000a. The controller 2000a will be configured to randomize the data to be stored in the flash memory 1000a and to add ECC data to the randomized data. The controller 2000a will be configured to detect and correct errors in the randomized data read from the flash memory 1000a and to de-randomize the randomized data.

The controller 2000a includes a first interface 2100a, a second interface 2200a, a processing unit 2300a, a buffer memory 2400a, an ECC block 2500a, and a randomization / de-randomization block 2600 . The components 2100a, 2200a, 2300a, 2400a, and 2500a shown in Figure 13 are substantially the same as those shown in Figure 12 except for the following differences, and the description thereof will therefore be omitted.

The randomization and de-randomization block 2600 is configured to randomize data output from the buffer memory 2400a and de-randomize the data (i.e., randomized data) read from the flash memory 1000a will be. The randomization and de-randomization block 2600 performs randomization and de-randomization operations on random data according to one of the schemes described in Figures 3 to 10, the description of which will therefore be omitted . The ECC block 2600 will generate ECC data based on the randomized data output from the randomizing and de-randomizing block 2500. [ The ECC block 2500a will also perform error detection and correction operations on the data read from the flash memory 1000a, that is, the randomized data, based on the ECC data. The ECC data may be stored in the same page as the data to be stored in the flash memory 1000a or in an area different from the data to be stored in the flash memory 1000a.

In the case of the memory system shown in FIG. 13, the write operation randomizes data to be stored in the flash memory 1000a, generates ECC data based on the randomized data, Lt; RTI ID = 0.0 > data. ≪ / RTI > Or randomizing and storing both the data to be stored and the ECC data . The read operation may include performing error detection and correction operations on the data (i.e., randomized data) read based on the ECC data, and randomizing the read data.

14 is a block diagram schematically illustrating a semiconductor drive according to an exemplary embodiment of the present invention.

Referring to FIG. 14, the semiconductor drive 4000 (SSD) will include a storage medium 4100 and a controller 4200. The storage medium 4100 may be coupled to the controller 4200 via a plurality of channels. A plurality of nonvolatile memories will be commonly connected to each channel. Each non-volatile memory will consist of the flash memory described in FIG. In this case, the controller 4200 will be configured substantially the same as that shown in Fig. That is, data randomization and de-randomization are performed in each non-volatile memory, and error detection and correction will be performed in the controller 4200.

Alternatively, the controller 4200 will be configured the same as that described in Fig. In such a case, data randomization and de-randomization and error detection and correction will be performed in controller 4200. Thus, it is possible to generate an initial seed for random data with reference to an offset address.

FIG. 15 is a block diagram schematically showing the storage using the semiconductor drive shown in FIG. 14, and FIG. 16 is a block diagram schematically showing a storage server using the semiconductor drive shown in FIG.

A semiconductor drive 4000 in accordance with an exemplary embodiment of the present invention may be used to configure storage. As shown in FIG. 15, the storage will include a plurality of semiconductor drives configured substantially the same as those described in FIG. A semiconductor drive 4000 in accordance with an exemplary embodiment of the present invention may be used to configure a storage server. As shown in FIG. 16, the storage server will include a plurality of semiconductor drives 4000 configured substantially the same as those described in FIG. 14, and a server 4000A for controlling the overall operation of the storage server . It will also be appreciated that a RAID controller 4000B for parity management according to a parity scheme applied to heal defects for data stored in semiconductor drives 4000 may be provided to the storage server.

Figures 17-19 are diagrams schematically illustrating systems according to exemplary embodiments of the present invention.

In the case where a semiconductor drive comprising memory controller and flash memory devices according to exemplary embodiments of the present invention is applied to the storage, as shown in FIG. 17, system 6000 may be wired and / And a storage 6100 that communicates. When a semiconductor drive including a data storage device according to exemplary embodiments of the present invention is applied to a storage server, as shown in FIG. 18, the system 7000 may include a storage server Lt; RTI ID = 0.0 > 7100 < / RTI > 19, the semiconductor drive including the data storage device according to the exemplary embodiment of the present invention may also be applied to the mail server 8100. [ The mail server 8100 communicates with the user mail programs through the mail daemon connected by the POP and SMTP methods, and the mail servers 8100 communicate with the internet network.

20 to 24 are diagrams schematically showing other systems to which a nonvolatile memory device according to exemplary embodiments of the present invention is applied.

20 is a block diagram schematically illustrating a cellular phone system in which a flash memory device according to an exemplary embodiment of the present invention is used.

20, the mobile phone system includes an ADPCM codec circuit 9202, a speaker 9203, a microphone 9204, a compression or decompression circuit for compressing or decompressing a sound, A TDMA circuit 9206 for multiplexing, a PLL circuit 9210 for setting a carrier frequency of a radio signal, an RF circuit 9211 for transmitting or receiving a radio signal, and the like.

The cellular phone system may also include various types of memory devices, for example, a cellular phone system may include a flash memory device 9207, a non-volatile memory device, ROM 9208, SRAM 9209 . As the memory device 9207 of the mobile phone system, for example, the flash volatile memory device described in Fig. 1 will be used. That is, it is possible to generate an initial seed for random data. ROM 9208 can store a program and SRAM 9209 acts as a work area for system control microcomputer 9212 or temporarily stores data. Here, the system control microcomputer 9212, as a processor, can control the write operation and the read operation of the flash memory device 9207. [

21 is an exemplary diagram of a memory card in which a flash memory device according to an exemplary embodiment of the present invention is used. The memory card may be, for example, an MMC card, an SD card, a multiuse card, a micro SD card, a memory stick, a compact SD card, an ID card, a PCMCIA card, an SSD card, a chip card, ), A USB card, and the like.

21, the memory card includes an interface unit 9221 for performing an interface with the outside, a controller 9222 having a buffer memory and controlling the operation of the memory card, a flash memory device 9207 according to an embodiment of the present invention ). ≪ / RTI > The flash memory device 9207 will be configured as a flash memory device configured to generate an initial seed for random data. The controller 9222, as a processor, can control the write operation and the read operation of the flash memory device 9207. [ Specifically, the controller 9222 is coupled to the nonvolatile memory device 9207 and the interface portion 9221 via a data bus (DATA) and an address bus (ADDRESS).

22 is an exemplary diagram of a digital still camera in which a flash memory device according to an exemplary embodiment of the present invention is used.

22, a digital still camera includes a body 9301, a slot 9302, a lens 9303, a display portion 9308, a shutter button 9312, a strobe 9318, and the like. Particularly, a memory card 9331 can be inserted in the slot 9308 and a memory card 9331 can be inserted into the flash memory device 9207 according to an embodiment of the present invention configured to be able to generate an initial seed for random data, May be included. When the memory card 9331 is in the contact type, the memory card 9331 and the specific electric circuit on the circuit board are brought into electrical contact when the memory card 9331 is inserted into the slot 9308. [ If the memory card 9331 is a non-contact type, the memory card 9331 will be accessed via the wireless signal.

23 is an exemplary diagram illustrating various systems in which the memory card of Fig. 22 is used.

23, the memory card 2331 includes a video camera, a television, an audio device, a game device, an electronic music device, a mobile phone, (H) a PDA (Personal Digital Assistant), (i) a voice recorder, (j) a PC card, and the like.

Figure 24 is an exemplary diagram of an image sensor system in which a flash memory device according to an exemplary embodiment of the invention is used.

24, the image sensor system includes an image sensor 9332, an input / output device 9336, a RAM 9348, a CPU 9344, a flash memory device 9354, etc. according to an exemplary embodiment of the present invention can do. Flash memory device 9354 may be configured to be capable of generating an initial seed for random data. Each component, namely, the image sensor 9332, the input / output device 9336, the RAM 9348, the CPU 9344, and the flash memory device 9354 communicate with each other via the bus 9352. The image sensor 9332 may include a photo sensing device such as a photogate, a photodiode, or the like. Each component may be composed of one chip together with the processor, or may be formed of chips separate from the processor.

In an exemplary embodiment of the present invention, the memory cells may be comprised of variable resistance memory cells, and exemplary variable resistance memory cells and memory devices containing the same are disclosed in U.S. Patent No. 7529124, Will be included.

In another exemplary embodiment of the present invention, the memory cells may be implemented using one of various cell structures having a charge storage layer. The cell structure with the charge storage layer will include a charge trap flash structure using a charge trap layer, a stack flash structure in which the arrays are stacked in multiple layers, a flash structure without a source-drain, a pin-type flash structure, and the like.

A memory device having a charge trap flash structure as the charge storage layer is disclosed in U.S. Patent No. 6858906, U.S. Patent Publication No. 2004-0169238, and U.S. Patent Publication No. 2006-0180851, each of which is incorporated herein by reference . A flash structure without a source / drain is disclosed in Korean Patent No. 673020, which will be incorporated by reference in this application.

The flash memory device and / or memory controller according to the present invention may be implemented using various types of packages. For example, the flash memory device and / or the memory controller according to the present invention can be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) Linear Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Wafer-Level Processed Stack Package (WSP), and the like.

It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

100: memory cell array
200: row selection circuit
300: control logic
400: page buffer circuit
500: Thermal select circuit
600: randomization and de-randomization circuit
700: Input / output interface circuit

Claims (10)

Determining if the data access is random;
If the data access is not random, generating first random sequence data based on the first seed;
Synthesizing the first random sequence data with data read from the memory or data to be written into the memory;
If the data access is random, generating a second seed from the first seed;
Generating second random sequence data based on the second seed; And
And combining the second random sequence data with data read from the memory or data to be written to the memory. The method according to claim 1,
Wherein the first seed is generated based on one of a column address, a page address, a block unit, or a sector unit. The method according to claim 1,
And if the column offset value of the data access is not zero, the data access is determined at random. The method according to claim 1,
And if the column offset value of the data access is zero, the data access is determined not to be random. The method according to claim 1,
Wherein the data to be written is received through an input / output interface, and the data to be written and the first or second random sequence data are combined is output to a page buffer. The method according to claim 1,
Wherein the data read from the memory and the first or second random sequence data are combined through an input / output interface. A memory cell array;
A random sequence data generator for generating at least one random sequence data string based on the first seed;
A mixer for de-randomizing data read from the memory cell array; And
A control circuit for controlling access to the memory cell array and activating the random sequence data generator based on a memory access mode,
In the first mode, a portion of the memory address is used as the first seed,
In a second mode, a second seed is generated by the random sequence data generator. 8. The method of claim 7,
Wherein the mixer randomizes random sequence data and data to be written to the memory cell array. 8. The method of claim 7,
Wherein the control circuit generates an intermediate seed based on the first seed and generates random sequence data based on the intermediate seed. 8. The method of claim 7,
Wherein the mixer synthesizes multi-valued data by a bit-wise XOR operation.

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