TW201232261A - Memory control method, memory device and memory system - Google Patents

Abstract

A method of controlling a memory, a memory device and a memory system are provided, the provided method includes determining whether data access is random; generating a first random sequence (RS) data based on a first seed if data access is not random (column offset=0); mixing the first RS data with data read from the memory or data to be written to the memory; generating a second seed from a first seed if data access is random (column offset not=0); generating a second RS data based on the second seed; and mixing the second RS data with data read from the memory or data to be written to the memory.

Description

201232261 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor memory, and more particularly to a flash memory device. [Prior Art] A flash memory device is an Electrically-Erasable Programmable Read-Only Memory (EEPROM), and multiple memory areas can be erased or programmed by a program operation. . Traditional EEPROM - only erases or stylizes a memory area. If different memory areas can be written at the same time, the flash memory device can be operated more quickly. After the predetermined number of erasing operations, 'all kinds of flash memory and EEpR〇M may be due to the loss or retreat of the storage _ stored data _ stored data charge; and the loss of 0 flash memory (four) device by not needing The electricity is stored in a manner that stores the shell of the tree core (4) the material stored on the material 4. = The physical factor provides the group (4) physical material, and relatively accelerates the storage characteristics. The flash memory device is usually used for battery power supply. [Inventive content] The method for generating the function of the offset address and the invention - The embodiment is a randomizable method for performing initial data for the initial seed. The present invention proposes a memory control method, and the method for controlling the memory includes determining whether the data access is random. If the data access is not random, the first random sequence data is generated based on the first seed. Hybrid: Random sequence data and data read from memory or data written to memory. If the data access is random, a second seed is generated from the first seed. The second random sequence data is generated according to a child. And mixing the second random sequence data with the data read from the memory or the data written to the memory, in an embodiment of the invention, the first seed is based on a column address, a page address, One of a block unit or a sector unit. When the row address is not zero, the data access is random access. In an embodiment of the invention, the second random sequence data includes random sequence data satisfying a l+X^+xk polynomial. In one embodiment of the invention, said K = ll. In an embodiment of the present invention, the method for controlling the memory further includes using the first seed as the first segment 'the second seed generated according to the first seed as the intermediate segment' and according to the first or second seed The resulting third seed acts as a third segment that produces a random sequence. In one embodiment of the invention, the data being written is received from the input/output pins and the mixed material is output to the page buffer. The present invention proposes a method of controlling a memory, comprising receiving an offset address value Ν and Ν being a line portion of an access address. The random sequence data is generated before the first read data is randomly decoded according to the access address, where ν is the maximum value of 201232261 Μ. And decomposing the first read data by mixing the nth random sequence data with the first read data. In one embodiment of the invention, the stated M = N. In one embodiment of the invention, the memory control method includes accelerating the generation of the 随机 random sequence data by selecting a random sequence data string path including the pre-shifted output. The present invention proposes a method of controlling a memory, comprising receiving a partial migration, and Ν is a line portion of an access address. The random sequence data is generated prior to randomizing the first-read data according to the access address, where Μ is the range from i to the end of the line portion that is smaller than the access address. And N random sequence data is used to solve the randomized first read data. The present invention proposes a memory device comprising a flash memory cell array, a P-on-the-sequence gastric material generator, a random circuit, a de-random circuit, and a control circuit. The random sequence data generator is configured to generate at least one random, column-behaved string according to the first seed. Random circuit (4) mixed random sequence data and write flash. The random circuit (4) solves the randomization of the data read from the flash memory = column. The control circuit is configured to control the flash memory cell array and start the random sequence data generation according to the memory access mode. The two circuit: the machine circuit and the de-random circuit are disposed between the page buffer and the input/output pin. In the embodiment, in the mode, one of the memory addresses is: the second seed is the first seed, and in the second mode, the second seed is generated and the random sequence data generator is used to generate the 1+ Random sequence data for the x + x polynomial. 6 201232261 In an embodiment of the invention, the random sequence data generator is configured to output at least one predetermined random sequence data according to the reply of the acceleration signal. The present invention provides a memory system including a memory device and a memory controller. The memory device includes a flash memory cell array, a random sequence circuit, and a mixer. A random sequence circuit is used to generate random sequence data. The mixer is used to mix random sequence data with data written to the flash memory cell array and to de-randomize the data read from the flash memory cell array. The memory controller includes control circuitry ' to control writing and reading data from the flash memory array through the mixer. In one embodiment of the invention, the 'memory system further includes at least one remaining memory device and a random sequence circuit. The at least one remaining memory device includes a flash memory cell array. The random sequence circuit is used to mix the random sequence data with the data to be written to the flash memory cell array and to de-randomize the data read from the flash memory cell array. In an embodiment of the invention, the memory controller further includes an error control circuit for performing an error correction function when reading data from the flash memory cell array. In one embodiment of the invention, the flash memory cell array is a multi-level cell type. θ In one embodiment of the invention, the memory device is embedded in a solid state hard disk card. In one embodiment of the invention, both the memory device and the memory controller are embedded in a solid state hard disk card. 201232261 More Leica and at least one remaining solid state hard drive card. * In the case of the month of the month, the memory system includes the word service number == redundant array controller. The server is used to control the solid state hard disk card = the disk redundant array controller is used to control other solid state hard disk cards, 14 corresponding management functions. I have invented the implementation of the memory, and the memory line further includes means for communicating with a plurality of solid state hard disk cards. Communication. In the embodiment of the present invention, the memory system further includes a pirate for providing between the line processing device and the multi-state hard disk card. In the embodiment of the present invention, the memory system further includes a network connection. Multiple processing devices and multiple solid state hard disk cards. In one embodiment of the invention, the 'memory system further includes a cellular transmitter for communicating with a cellular network. In an embodiment of the invention, the image is captured. The memory system further includes image sensing. The present invention provides a memory device comprising a flash memory cell array, a random sequence data generator, a mixer, and a control circuit. The random sequence data generator is configured to generate at least one random sequence data string based on the first seed. The mixer is used to de-randomize the data read from the flash memory cell array. The control circuit is configured to control access to the flash memory cell array and start the random sequence data generator according to the memory access mode, wherein in a mode, the memory 8 201232261 -----Γ -1 address The portion is used as the first seed and in the second mode the second seed is generated by the random sequence data generator. In one embodiment of the invention, the mixer is further configured to randomize data to be written to the flash memory cell array in a random sequence of data. In one embodiment of the invention, the mixer is configured to receive data read from the flash memory cell array through the page buffer, and the randomized data is output through the input/output pin. In one embodiment of the invention, the control circuit is operative to generate an intermediate seed' based on the first seed' and to generate random sequence data based on the intermediate seed. In one embodiment of the invention, the flash memory cell array includes a flash of a multi-layer cell type, and the mixer is configured to mix multi-value data by bitwise XOR operation. [Embodiment] Hereinafter, the present invention will be described in more detail with reference to the embodiments of the present invention and the accompanying drawings. However, the invention may be embodied in different forms, and the invention is not limited to the embodiments. These embodiments are provided to provide a thorough and complete disclosure of the present invention and the prior art in the field to which the invention pertains. In the 34 illustrations, the size and relative size of each level and region may be exaggerated for convenience of explanation. The same number always corresponds to the same component. / It must be understood that although the first, second or third terms are used to describe different elements, components, regions, layers or parts, these elements, components, regions, classes or parts are not limit. These terms are only used to distinguish one element, component, region, layer, or portion with another element, 201232261, u, and a region, hierarchy, or portion. Thus, a first element, or a portion, or a portion, or a portion, may be referred to as a second element, component, region, layer, or portion that does not depart from the scope of the invention. 1 is a functional block diagram of a flash memory device in accordance with an embodiment of the present invention. Please refer to ®1 1. The memory device includes a memory cell array 100. The memory cell array 1GG has a column (_, whose corresponding word line is: WL) and a row (column whose corresponding bit line is: BL). Memory cell. Each memory cell stores 1 bit of data or 1 bit (multi bi〇 data (M is a positive integer greater than 2). Each memory cell can be in the form of a memory cell with a charge storage layer, such as floating a flip-ring gate, a charge trap layer or a memory cell having a variable resistive element. The form of the memory cell array 100 may be a single-layer (2-dimensional) array structure or a multi-layer array structure. It may also be a 3-dimensional array structure of a vertical type or a stacked type. The memory device may be a flash memory of the (N AND) type. The column selection circuit 200 is controlled by the control circuit 300 and is used for selection. And a driving operation on the column of the memory cell array 100. The control circuit 300 is used to control the overall operation of the flash memory device. The page buffer circuit 400 is controlled by the control circuit 300 and acts like a sense amplifier or write The write driver operates according to the mode of operation. For example, during a read operation, the page buffer circuit 4 is like a sense amplifier, sensing from the selected column connected to the memory cell. Memory cell data. During the stylization, the page buffer circuit 400 can be used as a write driver to drive data into the memory cell connected to the selected column. Page buffer cry 201232261 111 Corresponding seam line or bit churn buffer The memory cell stores multi-bit data, and each page of the page buffer circuit 400 may have more than two latches. (4) Continued * Refer to FIG. 1 'The row selection circuit 500 is controlled by the logic 300. 'Hundred-type molds and wipes through the pre-fresh elements to select row two. Random generator circuit _ (T abbreviated as random; tunneling through the wheel input / output interface 7 〇〇 transmission (example ^ ', to the input /= Output of the output pin or received from the input/output pin. The downtime generator circuit_ is also used to receive and pass through the page buffer circuit 400 in accordance with the control logic. According to the present embodiment, the input/output interface output of the input/output pin is included and the memory is placed. In the embodiment of the present invention, the k machine The generator circuit _ is not only used for the entire page (fuiipage) #料# (for example, domain data, sector data, more than sector data, and less than sector data, etc.), the material is ^^^; In the following, the charge amount of the electric valve device is turned to a voltage of two, == cloth because the adjacent charge "the charge loss is fine (referred to as the word m electric ^ correct access (10) will be subject to riding - track. ^ 1) When '11 201232261^ Poor. Randomization of data (such as 'mixing data with random sequences) will reduce the number of cells that are caused by the line 33. In other words, the heart is cryptic. The state of the distribution is more uniform, and the occurrence of word line coupling is reduced relative to the data (1). In an embodiment of the invention, the operation of the random generator can be selectively performed. For example, the random generator circuit _ is subjected to the operation of its random generator when requested to access the (four) or specific region. 2 is a diagram showing an example of a memory cell array of FIG. 1 composed of all (iv) blocks of all bit line (ABL) memory architectures or odd-even memory architectures. The architecture of the memory cell array is shown in the following example. The NAND (four) memory device includes a memory cell array that is cut into 1024 blocks. The data stored in each block can be erased by (4) or erased by the memory block unit. In the real paste +, the texture block or the memory sub-block is the smallest element of the storage component, and the memory block or the memory sub-block is simultaneously erased. Each memory block, for example, has a column corresponding to a bit line (e.g., a 1 KB bit line). In an embodiment with reference to all bit line architectures, all bit lines of the memory block can be simultaneously selected in the 4-word line selected by the column selection circuit and connected to all during read or program operations. The storage elements of the bit lines can be programmed at the same time. In an embodiment, a plurality of storage elements in the same row are concatenated to form a NAND string. One end of the NAND string is connected to the corresponding bit line through the selection transistor controlled by the word selection line SSL, and 12 201232261 • The X-* controlled selection transistor is connected to the other end. The ground selection line GSL is connected to the universal source line CSL. In another embodiment of the embodiment, the bit lines are divided into even bits, uBLe, and odd bit lines BLg. In the parity bit line, the storage elements on the pass line are programmed at the first time and the storage time in the line and connected to the even lines is programmed. 3 is a functional block diagram of the random generator circuit of FIG. i in accordance with an exemplary embodiment of the present invention. Referring to Figure 3, an exemplary embodiment of the present invention includes a timing generator (10), a selector 62, a virtual random sequence ff (four), a free running cigarette _, and a mixer (4). The resource 庠 包括 包括 、 includes the timing generator 610, the selector 62°, the virtual random sequence generator 630, and the free ;;, 丨 „„ 汉 由 汉 仃 640 640 640 640 640 640 640 640 640 640 640 640 640 640 Preface to Zhao random phase data (4). —Sakiji sequence data with the sequence RS. Mixing 11 (4) is also used to extract data from the _sequence; the data of the port is read, for example, from the memory cell array (10) to generate data for de-randomizing the data. The mixer (4) is used to mix binary units of (4) memory suitable for a single-level (quad) state, and can also be used to transmit multi-bit values by bit (blMV1Se) operation, for example, by bitwise exclusive OR (XOR) operation. , Lina ▲ Shengyi 610 is used to generate the timing signal CLK. The selector 620 G goes into the L number CLK and the read/write enable signal RE/WE - in response to the selection signal (freewheel 13 201232261 line signal) FRS received from the free running detector 64. For example, when the free running signal FRS is activated, the selection 620 will select the timing signal clk from the timing generator 610 as its output L 5 tiger. When the free running signal FRS is prevented from starting, the selection 620 selects the read/write enable signal RE/WE. The signal CLK or RE/WE selected by the selector 62 is supplied to the virtual random sequence generator 63 as a random sequence timing signal CLK_RS to sequentially generate random sequence data RSD in accordance with a predetermined seed. In an exemplary embodiment, the predetermined seed may be comprised of one of a column address, a page address, a block unit, an address, or a sector unit. However, it should be understood that the predetermined method of seeding is not limited to the above. In accordance with a consistent embodiment of the present invention, when requested to access any page, the page address bits are supplied by k to the virtual random sequence generator 630 as a seed. This seed is provided to the virtual random sequence generator 630 as a constant value. The seed used to randomize the first data provided to the mixer 650 or to generate the initial random sequence data is referred to as the first seed. According to an embodiment of the present invention, the column address and row address of the sector unit of the reference page can also be used as an initial seed. In an exemplary embodiment, the virtual random sequence generator 63() can be paired with a shift register and one or more x〇R logic gates. ) to implement. ^ Yes, it is to be understood that the virtual random sequence generator 63 can be composed of a virtual random number (or random number) sequence generator, a cyclic redundancy code (CRC) generator or the like. With continued reference to Figure 3, the free running detector 640 generates a free running signal based on the line offset value! ?!^. In an exemplary embodiment, the row offset value may be 201232261 x i 疋 access the value of the row address provided in the request. According to an embodiment, the row offset value may be zero when requested for a full page material read or write operation. When it is turned into a 7-return, the row address or offset value is not zero. For example, the first access point of the 'page data is determined by the row bit with the address value of zero and the spine of the (4) is determined by the lamp address having a value greater than zero. Here, the material readout position may include the row position of the page buffer circuit 400 or the row position of the page. Similarly, the location where the data is stored according to the access request (or 'access point') can be determined to be different by the row address. Here, the line offset value or the offset address can be used interchangeably. The free running detector 640 includes a counter 641 and a comparator 642. The counter 641 can synchronously operate the timing finger CKL generated by the timing generator 61. The comparator 642 compares the count value of the counter 641 with the line offset value and generates a free running money FRS based on the comparison result. For example, when the initial value of the counter 641 is the same as the line offset value, the free running signal FRS is prevented from starting. When the initial value of the counter (4) is different from the line offset value, the free running signal FRS is activated. In the latter case described above, when the count value of the counter 641 reaches the line offset value, the comparator 642 blocks the start of the free running signal FRS. When a read or write operation and the line offset value is zero, the counter 641 does not operate and the free running signal FRS is prevented from starting. The free running signal FRS is mixed with the instructions - access request and full page wealth. In this condition, the read/write enable signal RE/WE will be selected and the RE/WE switched on the data input/output will be provided to the 15 through the selector 62. 201232261 r Γ Virtual, machine sequence generation 63〇. Under the read/write request, the read/write enable ^ number RE/WE will be provided by (4) to the mixer 65〇. In the case of a read/write operation and the line offset value is not zero, the counter 641 performs "ten number." That is, when the line offset value is different from the first two values of the count ^ 641, the free running detector 64 〇 synchronizes the counting operation with the timing signal clk and starts the free running signal chat. Start free running b Tiger FRS indicates that the access request is related to random data. In this case, the timing generator όΐ 产生 generated timing signal CKL is selected by the selector 62 且 and the timing signal CKL is supplied to the virtual random sequence to generate a cry (four) ' and the virtual random sequence generator (4) is synchronized using the timing sequence Generate random order materials. The operation of generating the initial random sequence data for the randomization of the first bait material is called a free running operation. When the count value reaches the volume offset value, the free running detector _ blocks the free running signal FRS. When the state of the free running signal FRS transitions from the start-up cancer to the start-up prevention state, the input/output (4) read/write enable money RE/WE will change (4), and the read 35 = E will pass through. Selector 63. The virtual random sequence generation j mixer 650 is provided to perform a randomization and de-randomization function. For example, during a read operation, the hybrid 〇 65 〇 logically combines the _ phase data coffee with the randomized data read from the memory cell array through the page buffer _ and the row selection circuit 500 to output the derandomized data to the input. / Output two-sided period. In the write operation, the mixer 650 logically combines the random sequence data RSD with the data provided through the input/output interface, and uses the data of round=201232261 as the randomized data to the row selection circuit 5〇〇, and makes this The combined data is written to the memory cell array 100. Mixer 650 can include logic circuitry, such as XOR gates, to implement additional logic functionality. In the case where byte-unit data is supplied to the mixer 65, the 'random sequence data bits can be logically combined with each of the read or programmed data bits. Free Run ##FRS can have one of active_high level and active-low level depending on whether the requested access is random data access. 4 is a timing diagram illustrating the read operation of a flash memory device in accordance with an exemplary embodiment of the present invention. Read operations can be performed based on the input instructions and the combination of addresses. For example, as shown in FIG. 4, the first instruction 〇〇h, the address C1C2R1R2R3, and the second instruction 3〇h may be sequentially supplied to the flash memory device. The provided address C1C2R1R2R3 may include a row address C1C2 and a column address R1R2R3. Since the row offset value is the row address C1C2 and the row address C1C2 is not zero', the data access is random, and the column address R1R2R3 is used as a seed to generate the initial random sequence data. In addition, when the randomized unit is less than one page, the row address or the sector address can be used as a starting seed to generate an intermediate seed, which is used to generate random sequence data in reverse to de-randomize from the flash memory cell. The data read by the array. After the second instruction 3〇11 is supplied to the flash memory device, the page buffer circuit 400 reads the material from the memory cell array 100 17 201232261 as a response to the control of the control logic 300 in the time interval tR. As shown in Fig. 4, in the time interval tR, the ready/busy signal can be maintained at a low level. Since the line offset value is not zero and is different from the initial value of the counter 641, the free running detector 640 starts the free running signal FRS. That is, the timing CLK No. 5 is selected by the selector 620 and supplied to the virtual random sequence generator 630. The virtual random sequence generator 63 uses the column address R1R2R3 as a seed to generate initial random sequence data. The counter 641 starts counting in accordance with the timing signal CLK after the second command 30h is input. The row address and row offset values are read into comparator 642. When the count value of the counter 641 reaches the line offset value, the comparator 642 blocks the activation of the free running signal FRS. When the free running signal FRS is prevented from being activated, the timing signal CLK is not selected by the selector 620 and the free running operation is stopped. At this time, the virtual random sequence generator 630 is supplied with the initial random sequence data as a seed for randomizing the first data. After the time interval tR, the data of the page buffer circuit 400 (i.e., the randomized data) can be supplied to the random generator circuit through the row selection circuit 500 according to the switching of the read/write enable signal RE/WE. 600. At this time, the virtual random sequence generator 630 synchronizes with the switching of the read/write enable signal RE/WE and sequentially generates the random sequence data RSD. The mixer 650 logically combines the random sequence data RSD with the data selected from the row address C1C2, and the combined data is used as the derandomized data and supplied to the external device through the input/output interface 700. The operation of de-randomization can be repeated until all the data requested to be accessed is output. 201232261

-v *· «· f-I The data stored in the page buffer circuit 400 can be additionally supplied to the external device by using the instruction and the address group. In this case, the : ready/busy signal can be maintained at a high level as indicated by ^4. For example, the first instruction 05h, the address C1C2, and the second instruction EOh may be sequentially provided to the flash memory device. At this time, the provided address includes only the row address C1C2, and the row address C1C2 is not zero. The initial random sequence data rsd is generated by the free-running operation of the random sequence generating block 650 and using the seed determined according to the previously provided column address R1R2R3, which is essentially the same as described above. As shown in Fig. 4, after the second instruction E〇h is received and the time interval in which the initial seed is generated, the data is output. The time interval (e.g., 13 microseconds) taken to prepare the initial seed will be shorter than the time interval tR (e.g., '30 microseconds). FIG. 5 is a timing diagram illustrating a read operation of a flash CMOS device according to another exemplary embodiment of the present invention. Read operations can be performed based on the input instructions and the combination of addresses. For example, as shown in FIG. 5, the first instruction (9)h, the address C1C2R1R2R3, and the second instruction 3〇h may be sequentially supplied to the flash memory device. The provided address C1C2R1R2R3 may include a row address cic2 and a column address leg. In the present embodiment, the row address ac2 is zero' and the row offset value is zero. Since the row offset value is zero, the data is not randomly accessed' and the free-running operation is not performed. After the first instruction 3〇h is supplied to the flash memory device, the page buffer circuit 4 读出 reads the data from the memory cell array 1〇〇201232261ir as the control of the control logic 300 in the time interval tR + '. Respond. As shown in Fig. 5, in the time interval tR, the ready/busy signal can be maintained at a low level. The machine generator circuit 6 sequentially uses the received column address rir2R3 as a seed to generate a random sequence data RSD, and logically combines the random sequence data RSD with the data read from the page buffer circuit 4A. The combined data can be provided to the external splicing through the input/output circuit 700 as de-randomized data. FIG. 6 is a timing diagram illustrating a write operation of a flash memory device according to an exemplary embodiment of the invention. ^Write operations can be performed based on the input instructions and the combination of addresses. For example, as shown in FIG. 5, the first instruction 8〇h, the address C1C2R1R2R3, and the second instruction 1〇h may be sequentially provided to the flash memory device. The provided address C1C2R1R2R3 may include a row address C1C2 and a column address R1R2R3. In the present embodiment, the row address C1C2 = zero, and the row offset value is not zero for the row address ccl2. Therefore, the poor material access is random, and the initial address data is generated by using the column address R1R2R3 as a seed. Since the line offset value is not zero, the free running detector 640 activates the free signal FRS. That is, the timing signal CKL generated by the timing generation H 610 is selected by the selector 62. And the timing signal cKL is supplied to the virtual, random sequence to generate n (four) to generate the random sequence data RSD. When the tens value of the counter 641 reaches the column offset value, the 'free running debt detector' ο prevents the start of the free running signal FRS. At this time, the virtual random sequence generator 63〇20 201232261 * Λ. Λ. ^ is provided as The initial random sequence data of the initial seed of the first data is randomized. In an exemplary embodiment, at the time of the write operation, the counter 641 picks up after the address is input. If the initial seed is generated, the program is to be executed. The data is switched according to the capture/write enable signal RE/WE and sequentially supplied to the random generator circuit 600 through the input/output interface 700 of the flash memory device. At this time, the virtual random sequence is generated. The device 63 is synchronized with the switching of the read/write enable signal RE/WE and sequentially generates the random sequence data RSD. The mixer 650 logically combines the random sequence data RSD with the data provided through the input/output interface circuit 700. And the combined data is transmitted to the page buffer circuit 400 through the row selection circuit 5 as the randomized data. The randomized operation can be repeatedly performed. All data to be programmed is passed to the page buffer circuit 4. After that, if the second instruction 10h is supplied to the flash memory device, as shown in FIG. 6, the ready/busy signal is lowered from a high level. To the low level, during the time when the ready/busy signal _ is low, that is, in the time interval tpGM, the data stored in the page buffer circuit 400 (that is, the randomized data) is stored in the memory cell array. 100. ^ As stated above, although it is required to access the random data access (or data access), the Lexmark offset is purely used as the row offset value to prepare the initial seed (or 'initial random sequence data') to be random. It is still feasible to implement the above random data. 21 201232261 Although Figure 6 does not show the case where the line offset value is zero during the write operation, the free operation operation for generating the initial seed is performed at this time. In the case, the 'data and the second instruction 10h are sequentially supplied to the flash memory device along with the input of the address. In an exemplary embodiment, the time interval for generating the initial seed is based on the line offset value. Therefore, in Fig. 4, at the time point when the data is acquired under the reading operation, and in Fig. 6, at the time point when the data is supplied under the writing operation, the initial seed is generated. Figure 7 is a functional block diagram of the random generator circuit of Figure 1 in accordance with an exemplary embodiment of the present invention. Referring to Figure 7, another embodiment of the present invention is shown. For example, the random generator circuit includes a timing generator 610, a selector 620, a virtual random sequence generator 630a, a free running detector 640a, and a mixer 650. The timing generator 610, the selector 620, and the mixer 65 are both The description is the same and will not be described here. Referring to Fig. 7 to Fig. 9', the virtual sequence generator 630a of the random generator circuit 6Aa operates in the acceleration mode or the normal mode according to the flag signal ACC_E indicating the acceleration mode. In the acceleration mode; :Select: The pre-shifted random sequence data will be fined according to the preset polynomial: multiplex input 埠 shown in ΐ 8, which will generate the initial random sequence in the more accelerated mode. The time required* will be reduced. When the #flag money ACC E is not activated, the random generator gas Ga will operate in the normal mode.

201232261 The activation or non-activation of the flag signal ACC_EN indicating the acceleration mode is determined based on the adjustment data of the flash memory device. In addition, the activation or non-activation of the flag signal acc_en indicating the acceleration mode is determined by the controller controlling the flash memory device. However, it can be apparent from the prior art that the activation or "starting" of the flag signal ACC_EN of the acceleration mode is not limited to the above disclosed method. Speed information can also be determined by the launch of the flag 4 § §. The free running detector 640a includes a counter 641a, a comparator 642a, and a divider 643a. The counter 641a is used to operate in synchronization with the timing signal CLK. The divider 643a is made in the acceleration mode based on the flag signal ACC_EN. Divider 643a may pass the line offset value directly to comparator 642a or provide a value obtained by dividing the line offset value by speed information N to comparator 642a. For example, when the flag signal Α (χ-EN is indicated as the normal mode, the divider 643a transmits the unmodified line offset value to the divider 643a. When the flag signal ACC-EN is indicated as the acceleration mode, The divider 643a adds the value obtained by dividing the line offset line by the velocity and extracting the line to the comparator 642a. For example, when the line offset value is 1 〇〇〇 and the fast-tracking information is expressed as N-speed, the division is performed. The value output by the unit 643a is 1〇〇_two comparator 642a compares the count value of the counter 641a with the value of the divider 643& and according to the comparison result to generate a free running signal yang. For example, when the counter 64U is initialized When the value is the same as that output by the divider 643a, the free running signal FRS is prevented from being activated, and when the initial value of the counter is different from the value output by the divider 643a, the free FRS is activated. In the latter case, When the counter (4) & = 23 201232261 value reaches the value output by the divider 643a, the comparator 642a blocks the start of the free running signal FRS. Then the counter 641a also stops counting. Fig. 8 is a diagram showing the virtual random sequence in Fig. 7. A schematic diagram of the generator 630a, and FIG. 9 is a schematic diagram of a lookup table list of initial virtual random sequence data (or virtual seed values) generated by the virtual random sequence generator 630a of FIG. 7. Referring to FIG. 8 'virtual randomization The sequence generator 630a includes a plurality of flip-flops FF0 FFFF10 for operating in response to the random sequence timing signal CLK_RS, a plurality of selectors SEL0 SELSEL10 for operating in response to the acceleration flag signal ACC_EN, and a coupling condition A plurality of XOR logic gates 631 to 634 as shown in Fig. 8. In the present embodiment, as shown in Fig. 8, the virtual random sequence generator 630a satisfies the polynomial xu + χι〇+1 and is based on the flag No. 4 ACC_EN. It is determined to operate in the normal mode or the acceleration mode. When the level of the flag signal ACC-EN is expressed as the normal mode (e.g., low level), the input of the input port of the selector SELxx is selected and output to the flip-flop FF0. ~FF10 input 埠D. When the flag signal acc_en is at the level of the acceleration mode (eg, high level), the input of the input 埠1 of the selector seLxx is selected to pre-shift the random sequence data to positive The input 埠D of the inverters FF0 to FF10. For example, the selected χ1()Λχ〇Α Χ"Χ2' χ1〇Λχ〇Λχ1' χ1〇Αχ〇Λ^ x10~x3 selectors SEL0 to SEL10. In the embodiment of the invention, as shown in FIG. 8 , FIG. 9 shows that the row offset value is advanced or is outputted, for example, by the input device SEU and the flip-flop FF 〇 1 , thereby eliminating two The block loops to output pre-shifted random sequence data. ', 24 201232261 * V» * Figure 9 is an example of a column generated by a virtual random sequence generator with an offset value (vertical axis) and an order with a predetermined polynomial random sequence data (horizontal axis) For example, the real: 歹 polynomial is ΧΠ + Χΐ ° +1. As shown in FIG. 9, in the normal mode (the degree of addition is 1), the random sequence output according to the polynomial of 舦 corresponds to each row offset value of the sequence order, for example, the third column / the second 歹J and the 3 columns. In the acceleration mode (acceleration greater than j), the row offset value of the random sequence is further, for example, by inputting the input 埠i of the selector in FIG. 8 to output the pre-shift random sequence data by using the third column. And reduce the time used to set the initial seed. When the line offset value is increased according to the switching of the timing 彳§ CLK, the initial seeds are also sequentially generated. Although the accelerator described in this embodiment is characterized by two block loops to accelerate the generation of random sequences, other ways similar to the configuration of the present embodiment to change the accelerator parameters can be apparent in the prior art. For example, when the speed information is expressed as 4_speed, the initial seeds corresponding to the line offset values (e.g., 4, 8, 12, etc.) are sequentially generated. It should be noted here that, like FIG. 8, in FIG. 9, the symbol "Λ" indicates an XOR operation. Although various embodiments of the invention described herein generate random sequence data corresponding to an offset value, for example, The random sequence data generated in sequence is mixed with the data corresponding to the second offset value, and the random sequence data and the offset value are changed. In an embodiment of the present invention, the random sequence data is generated. Wherein, Μ may be a value smaller than Ν. For example, a random sequence data of 2012 25 201232261 ----- Γιτ 4 may be applied to the offset value 5. Therefore, the maximum value of Μ is Ν. According to another aspect of the present invention In an embodiment, the random sequence data is generated after the random first read data is solved according to the access address, wherein Μ is a range from 1 to the end of the line portion of the access address. A functional block diagram of the random generator circuit of FIG. 1 is shown in yet another embodiment of the present invention. Before starting the description, in the random generator circuit 6〇〇b of FIG. 1A, and the random generator of FIG. Components in circuit 6〇〇 The components having the same index number have the same function, and will not be described again here. Referring to FIG. 10, the random generator circuit 6〇〇b includes an initial seed generator 670 for generating an initial seed according to the row offset value. The random sequence generator 630 is implemented according to a polynomial χΐ 1+ χΐ〇 + 1 (shown in Figure 9) for generating an initial seed. As described above, the virtual random sequence generator 630 generates an initial according to predetermined conditions. The value of the seed. Thus, the initial seed generator 670 can be implemented on a hardware as shown in Figure 8. The virtual random sequence generator 630 and the initial seed generator 67 can form a block that produces a random sequence. In the example, the random sequence timing signal CLK_RS transmitted to the virtual random sequence generator may be a read/write enable ss number at the data input/output. In addition, the random sequence transmitted to the virtual random sequence generator 630 The timing signal CLK_RS may also be a timing signal generated at the time of data input/output. 26 201232261 FIG. 11A is a green display of the second virtual machine according to an embodiment of the present invention. Schematic diagram of the process of the method. Figure UB is a schematic diagram of the randomization of the flash memory device according to the consistent = Lin shown in the present invention. In the heartbeat S1〇(), the access starts and determines whether the requested access is broken. === = = row address or offset value. If you are fed to take the level of the machine, for example, after the offset, continue to perform the step test, by accessing his -, legacy, live. After the initial seed is generated, the step is: Step I: The machine sequence RSI^RSDn+l is randomized or derandomized by the prepared initial seed by '' and using the random sequence RSDiARSDn+1. New' has been randomized (4) The page buffer circuit 400 is stored in the array_. The decomposed data is supplied to an external device (e.g., controller) through the input/output interface. If the requested access action is determined to be a non-random data access (the row offset value is 0), then step S130 is followed by the step data, and the randomization or de-randomization operation is performed from the first data D〇. And according to various addresses (for example, page address, block address or sector address, etc., the starting seed determines a random sequence. It should be noted that in this step (S130), it is not required to use The operation of generating the initial seed is illustrated in Figures 3 to 。. Then, the randomized data can be stored in the array through the page buffer circuit 1 and the data descrambled through the input/output. Interface 700 is provided to the outside (eg, controller). ° 27 201232261, and the offset value to explain random access (routine address to μ leave c" "Minimum M and write to flash memory minimum The access can be a sector, such as a combination of program data and error correction codes, and a start seed and row address for the sector other than the first sector. In the case, by randomizing randomization or de-randomization, It can be composed of binary units, and can also be mixed by multi-valued operation by operation. Figure 12 is a functional block diagram of the memory system according to the present invention - Fig. 12, the memory system 3 The 〇〇 includes at least one flash memory 1000 and a controller 2000. The flash memory 1000 operates under the control of the controller 2000 and is used as a storage medium. The controller 2000 can be used to control the flash memory. The flash memory 1〇〇〇 may include a random generator circuit 11〇〇. It should be noted here that in FIG. 12, the flash memory 1000 is the same as the flash memory device of FIG. In addition, the controller 2 can be used to increase the error control code data stored in the flash memory 1000. The controller 2000 can include a first interface 21 〇〇, a second interface 2200, and a processing unit. 2300, buffer memory 2400 and error control circuit 2500. The first interface 2100 is used to communicate with an external device (eg, a host device). The second interface 2200 is used to communicate with the flash memory 2200. 2300 28 201232261 uiypif is used to control the overall operation of (4) device 2_. Slow = stored in flash memory data or == 1_ read trace error pure machine path test based on buffer data = body data to generate Error correction code data. In addition, ^ a = misfiguration of the data read by the decent face and correction of the error. The error correction code data can be stored in the same page as the data to be stored in the chatter. Or stored in an area different from the data of the fast memory 1000. In the memory system of FIG. 12, the writing operation may include generating an error correction code according to the data to be stored in the flash memory surface. Data and randomized data to be stored in the flash memory. The read operation may include de-randomizing the read data and performing error detection and correction operations on the de-randomized data. In addition, randomization of error correction code data is randomized to be optional. - In an embodiment of the present invention, the first interface 2 i 〇〇 of the controller 2000 may be in the form of a computer bus standard, a storage bus standard, and one of the Internet Fibre Channel protocol peripheral bus standards. Or combine the above two or more standards. Computer bus standards include s_1 bus (S-100 bus), Meter-Bus, Smbus, Q-bus, Industrial Standard Architecture (ISA), Zorro II, Zorro III, Computer Automated Measurement and Control (CAMAC), FASTBUS, LPC, Extended Industry Standard Architecture (EISA), VME, VXI, NuBus, TURBOcharmel, MCA, Sbus, VLB, PCI, PXI, HP Gecko System Connection Bus (HP GSC bus),

CoreConnect, InfiniBand, UPA, PCI-X, AGP, PCIe, English 29 201232261π • 1. Standards such as Intel QuickPath Interconnect and Hyper Transport. Storage bus standards can include ST-506, ESDI, SMD, Parallel 高, Parallel S, DMA, SSA, HIPPI, USB MSC, FireWire (1394), Serial ATA (Serial ΑΤΑ), eSΑΤΑ, small computer systems Standards for Interface (SCSI), Parallel SCSI, Serial Attached SCSI, Fibre Channel, iSCSI, SAS, RapidIO, and Fibre Channel over IP Address (FCIP). Internet Fibre Channel Protocol Peripheral Bus Standards can include Apple Desktop Bus, Hardware Loop (HIL), Instrument Digital Interface (MIDI), Multibus, RS-232, DMX512-A, EIA/RS -422, IEEE-1284, UNI/O, 1-Wire, I2C, SPI, EIA/RS-485, USB, Camera Link, External PCIe, Light Peak, and Multidrop Bus. Figure 13 is a functional block diagram of a memory system in accordance with another embodiment of the present invention. Referring to Figure 13, the memory system 3000a includes at least one flash memory 1000a and a controller 2000a. The flash memory i〇〇〇a operates under the control of the controller 2000a and is used as a storage medium. As shown in FIG. 13, the flash memory 10a does not include the random generator circuit described above. The controller 2000a can be used to control the flash memory i〇〇〇a. The controller 2000a is also used to randomize the data to be stored in the flash memory l〇〇〇a and to add the error correction code data to the randomized data. The controller 2000a is also used to perform error detection and correction operations on the error of the 30 201232261 -ri data read from the flash memory 1000a and randomize and randomize the randomized data. The controller 2000a may include a first interface 21a, a second interface 2200a, a processing unit 2300a, a buffer memory 2400a, an error control circuit 2500a, and a random generator block 2600. It should be noted here that the constituent elements 21a, 2200a, 2300a, 2400a, and 2500a in this embodiment are respectively associated with the constituent elements 21A, 2200a, 2300a, 2400a in the embodiment of FIG. 2500a is the same, so it will not be described here.

The Ik machine generator block 2600 is used to randomize the data read from the buffer memory 24A and to de-randomize the data read from the flash memory 1a (i.e., randomized) data of). The random generator block 26 can also perform randomization operations on the random data according to one of the methods illustrated in the various embodiments of FIG. 3 to FIG. 10, and details are not described herein again. The error control circuit 2600 can generate error correction code data based on the randomized data in the random generator block 25A. Further, the error control circuit 25 may perform error detection and correction operations on the data read from the flash memory 1A (i.e., the randomized data) based on the error correction code data. The error correction code data can be stored in the same page as the data to be stored in the flash memory 1000a or stored in an area different from the data to be stored in the flash memory 1000. In the present embodiment, the 'writing operation may include randomizing the data to be stored in the flash memory 1000a, generating error correction code data based on the randomized data, and storing the randomized data and the error correction code. The talent is in the flash memory 1000. In addition, the write operation can also include random second desire 31 201232261 - "= = = = = = = that is, 'randomized data" to perform error detection and = shake (also function ^ according to her - embodiment) The solid state hard disk = reference to Fig. 14 'solid state hard disk 4_ includes the storage medium side and the controller 4 ·. The storage side passes through the recorder 4200', wherein each channel is also connected to a plurality of non-volatile = body. The non-volatile memory age can be installed by the figure. In this embodiment, the controller 4 is the same as the figure J = control benefit 2000. That is, the randomization of the data can be performed in each non-= towel. The controller may be the same as the controller 2A shown in Figure π. At this time, the randomization of the data and the error_and corrections are performed in the controller 4200. It is feasible to generate an initial seed for use according to the offset address. Figure 15 is a functional block diagram of the storage device using the solid state hard disk in Figure 14. Figure 16 is a solid state hard disk using a solid state hard disk. A functional block diagram of a storage device. One embodiment of the present invention The solid state hard disk 4 is used to embody the storage device. Referring to Figure 15, the storage device includes a plurality of solid state hard disks 4000 identical to the solid state hard disk 4000 shown in Figure 14. In one embodiment of the present invention The solid hard disk 4000 can also be used to represent the storage server. Please refer to Figure 32 201232261 16 'Storage servo ϋ includes multiple marriages 14 (four) off the same hard disk side, state hard disk 4_, and can control the storage word processor The overall operation of the division, the device 4000A. Further into the 'storage server, including the independent disk redundant array control 1 4GGGB, the open disk redundant face switch 4〇 _ used to make the parity based on damage repair (parity The method performs the parity management on the data stored in the solid state hard disk 4000. Figure 19 to Figure 19 is an illustration of the system according to an embodiment of the present invention.

Referring to Figure 17 and in accordance with the above-described embodiments, a solid state hard disk embodying a storage device includes a memory controller and a flash memory device, and the system 6 includes a storage device 6100 that communicates with the host via a wired or wireless means. Referring to FIG. 18 and according to the above embodiment, the solid state hard disk embodying the storage server includes a data storage device, and the system 7 includes a storage server 71〇〇 and 72〇〇 communicating with the host through a wired or wireless manner. . Still further, referring to Figure 19 and in accordance with the above-described embodiment, the solid state drive embodying mail server 8100 includes a data storage device. The mail server 8100 can communicate with the mail program through the mail resident program by mail protocol (p〇st 〇ffice pr〇t〇c〇l, POP) and the Simple Mail Transfer Protocol (SMTP), and the mail server 81〇〇 Communicate with each other through the Internet. 20 through 24 are schematic diagrams of other systems using non-volatile memory devices, in accordance with an embodiment of the present invention. Figure 20 is a functional block diagram of a peak-to-cell telephone system suitable for use in a flash memory device in accordance with an embodiment of the present invention. Please refer to Figure 2〇, peak-chamber type electricity 33 201232261 H-lUiypif system includes adaptive poor arterial code modulation and decoding mother circuit 9202, speaker 9203, microphone 9204, time-multiplexed circuit 92〇6, phase-locked loop circuit 9210 and RF circuit 9211. The adaptive poor arterial codec codec circuit 9202 is used to compress the sound and decompress the compressed sound. Time-sharing The multiplex circuit 9206 is used to process digital data in a time-multiplexed manner. The phase locked loop circuit 9210 is used to set the carrier frequency of the radio frequency signal. Radio frequency circuit 9211 is used to transmit and receive radio frequency signals. In addition, the peak-to-chassis telephone system can also include a variety of types of memory, such as non-volatile memory devices 92〇7, read-only memory 92& and static access memory 9209. The non-volatile memory device 9207 can be composed of the flash memory device shown in Fig. 1 and performs the randomization and de-randomization operations shown in Figs. 3 to 1B. Read-only memory 92〇8 is used to store program data. The quiescent memory 9209 is used as a system to control the working area of the microcomputer 9212 or as a temporary storage material. System Control The microcomputer 9212 is a processor for controlling the writing and reading operations of the non-volatile memory devices 92A. Figure 21 is a functional block diagram of a memory card of a flash memory device suitable for use in an embodiment of the present invention. For example, the memory card may be a multimedia memory card (MMC), a secure digital memory card (SD card), a multi-purpose card (multiuse card),

From micro-SD card, micro-SD card, memory, memory card Computer 34 201232261 Personal Computer Memory Card International Association card (PCMCIA card), Solid State Disk card (SSD card), chip card (Chip-Card), smart card and USB card. Referring to Figure 21, in accordance with an embodiment of the present invention, a memory card includes a interface circuit 9221, a controller 9222, and at least one flash memory device 9207. The interface circuit 9221 is used as an interface for communicating with an external device. Control Benefit 9222 includes buffer memory for controlling the operation of the memory card. The flash memory device 9207 can be comprised of a flash memory device for generating an initial seed for use with random data. The controller 9222 can also be used as a writer of the flash memory device 9207 and a processor for reading operations. The controller 9222 can be lightly connected to the non-volatile through the data bus DATA and the address bus ADDRE SS. Memory shows £92〇7 with interface circuit 9221. '+ The functional block diagram of the digital still camera of the flash memory of her case. Please refer to Figure 22. The machine includes the body gamma, slot 9302, and so on. In particular, the initial seed used is _==;== into slot 9308. In order to be inserted, when the memory card 9331 is inserted into the plug, it can be electrically connected to the memory card 9331. If the memory card 9331 is in contact type, the slot is on the circuit board 35 201232261. If the memory card 931 A is not in contact type, the electronic circuit on the circuit board can communicate with the memory card 9331 via radio frequency. ^ 23 is a schematic diagram of the multi-aged memory card of Figure 22. Please refer to ^® 23 'memory card 9331 for (4) video camera, (b) television, (c) video device, (4) game console, (4) electronic music device, (1) peak nest phone, (g) computer, (h ) Personal Digital Assistant (PDA), (1) Recorder, and (1) Personal Computer Card International Union Card. Figure 24 is a functional block diagram of an image sensing system suitable for use in a flash memory device in accordance with an embodiment of the present invention. Referring to FIG. 24, the image sensing system includes an image sensor 9332, an input/output device 9336, a random access memory 9348, a central processing unit 9344, and a flash memory device 9354 as shown in one embodiment of the present invention. . The components in FIG. 24, that is, the image sensor 9332, the input/output device 9336, the random access memory 9348, the central processing unit 9344, and the flash memory device 9354 all communicate with each other through the bus bar 9352. . Wherein, each component may also be comprised of a single wafer that is embedded in or external to the processor. ° In one embodiment of the invention, the memory cells may be composed of memory cells of variable group resistance. Examples of the memory cells of the variable group resistance and the memory device are disclosed in U.S. Patent No. 7,529,124, the entire disclosure of which is incorporated herein by reference. In another embodiment of the invention, the memory cell is comprised of one of a plurality of cell structures having a charge storage layer. The cell architecture 36 with the charge storage layer 201232261 HlUiypif includes a charge trap flash structure using a charge trap layer, a stack flash structure stacked by a plurality of layers, and a source free structure. (s〇urcedrain structure) and pin-type flash architecture (pin_typeflashstmcture). A memory device having a charge trapping flash structure as a charge storage layer has been disclosed in U.S. Patent No. 6,685,906, and U.S. Patent Nos. 20040169238 and No. 20040169238, the entireties of each of each of The source-free architecture has been disclosed in Korean Patent No. 673〇2, so it is hereby incorporated by reference in its entirety. The flash memory device or the recorder controller of the present invention can be packaged in a variety of package types. For example, the flash memory device or the n-body controller of the present invention may use, for example, a package package (PoP), a ball gate array (BGA), a wafer size package ( Chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip 〇n B〇ard (c〇B), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Square Package (Plastic Metric Quad Flat Pack, MQFP), Thin Quad Flatpack (tqfp), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Shape package 37 201232261. (Thin Small Outline, TSOP), Thin Quad Flatpack (TQFP), System in package (SIP), Multi-chip package (Multi Chip Package, MCP), Wafer-level Fabricated Package (WFP), and Wafer-Level Processed Stack Package (Package Type). Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any of the skilled artisan (4) may be modified and retouched within the scope of the invention, and thus the scope of the present invention is This is subject to the definition of the scope of the patent application. ° [Simple description of the drawings] and the layers Γίί, the above and other features will become easier to see, and /, in the drawings, the same components will always be the same unless otherwise specified. The flash memory device shown in one embodiment of the present invention is shown in FIG. 2 as a memory cell array composed of all the bit line memory memory blocks of FIG. FIG. 1 is a diagram of an embodiment of the present invention. FIG. 6 is a diagram showing a flashing green display, which is fast. 38 201232261 ~r χ \/ λ FIG. 6 is a diagram showing an embodiment of the present invention. A timing diagram for explaining the write operation of the flash memory device. FIG. 7 is a functional block diagram of the random generator circuit of FIG. 1 according to another embodiment of the present invention. Figure 8 is a schematic illustration of a virtual random sequence generator in accordance with an embodiment of the present invention. 9 is a schematic diagram showing a lookup table list of initial virtual random sequence data generated by the virtual random sequence generator of FIG. 7. FIG. 10 is a functional block diagram of the random generator circuit of FIG. 1 according to yet another embodiment of the present invention. FIG. 11A is a flow chart of a method for randomizing a flash memory device according to an embodiment of the invention. Figure 11B is a schematic illustration of the randomized conception of a flash memory device as shown in an embodiment of the present invention. Figure 12 is a functional block diagram of a memory system as illustrated by one example of the present invention. Figure 13 is a functional block diagram of a memory system in accordance with another embodiment of the present invention. FIG. 14 is a functional block diagram of a solid state hard disk according to an embodiment of the invention. Figure 15 is a functional block diagram showing the storage device using the solid state hard disk of Figure 14. Figure 16 is a block diagram showing the storage server using the solid state drive of Figure 14. ° 39 201232261. *1-IUl^pif Figures 17 through 19 are schematic views of a system in accordance with an embodiment of the present invention. 20 through 24 are schematic views showing other systems of a non-volatile memory device to which an embodiment of the present invention is applied. [Description of main component symbols] 00h, 05h, 10h, 30h, EOh: Command 100: Memory cell array 200: Column selection circuit 300: Control circuit 400: Page buffer circuit 500: Row selection circuit 600, 600a: Random generator circuit 610: timing generator 620: selectors 630, 630a: virtual random sequence generators 631 to 634: exclusive OR logic gates 640, 640a: free running detectors 641, 641a: counters 642, 642a: comparators 643a: dividers 650: Mixer 670: initial seed generator 700: input/output interface 1000, 1000a: flash memory 201232261 • Λ. Λ ^ 1100, 2600a: 2000, 2000a, 2100 ' 2100a: 2200, 2000a: 2300, 2300a: Random generator circuit 9222: controller first interface second interface processing unit 2400, 2400a: buffer memory 2500, 2500a: error control circuit 3000, 3000a: memory system 4000: solid state hard disk 4000A: server 4000B: independent magnetic Disk Redundant Array Controller 6000, 7000, 8000: System 6100, 4100: Storage Device 7100, 7200 · Storage Server 8100: Mail Server 9201: Liquid Crystal Display Module 9202: Adaptability Arterial code modulation codec circuit 9203: speaker 9204: microphone 9205: keyboard 9206: time division multiplexing circuit 9207: non-volatile memory device 9208: read only memory 9209: static access memory 41 201232261 -τ XV 1 ^jjif 9210 : Phase-locked loop circuit 9211 : RF circuit 9212 : System control microcomputer 9221 : Interface circuit 9301 : Body 9302 · · Slot 9303 : Lens 9308 : Display circuit 9312 : Shutter button 9318 : Flash control 9331 : Memory card 9332: Image sensor 9336: Input/output device 9344: Central processing unit 9348: Random access memory 9352: Bus 8354: Flash memory device ACC_EN: Flag signal ADDRESS: Address bus bar BL, BL0~ BL (ml): bit line BLe, BLeO ~ BLe (nl): even bit line BLo, BLoO ~ BLo (nl): odd bit line Cl, C2: row address CLK: timing signal 42 201232261 CLK_RS: random Sequence timing signal CSL: general source line D0~Dn+2: data DATA: data bus FF0~FF10: flip-flop FRS: free running signal GSL: ground selection line and: ready/busy signal

Rl, R2, R3 ··column address RE/WE: read/write enable signal RS: random sequence RSD, RSD0~RSDn+2: random sequence data S100~S130: steps SEL0~SEL10: selector SSL: String selection line tPGM, tR: time interval WL, WL0 WLWL-1: word line 43

Claims (1)

201232261 VII. Application for Patent Park: The control party of the 6-remembered body = whether the material access is random: including. - Random order mussel 5: Take is not random, according to - the first seed is generated - the first is written: data And if the data read from the memory or if the data access is random, the child generates a second 3=two seed from the first seed to generate a second random sequence data; and is written two times and from the memory One of the data or the element read by the body „only the address, the block is 7G or the sector is one of the funds. _ The random 4. The method of controlling the memory as described in (4) Patent Area 1 When the data access-line offset value is zero, it is judged that the data is stored randomly. 疋5. The control of the memory described in the first paragraph of the patent application, wherein the second random sequence data includes the _ polynomial f , random sequence data. X 20^32261., more i & m1 round-field method, the middle zone π °, the seed as a first section, the second seed as: species; The seed or the first seed produced by the second seed acts as a third segment. In the control method of the patent application described in Item 1, the data is received from a round-in/out-out chat and the mixed Beko is rotated to a page buffer. The control method of the second, the memory is read and the data of the second random sequence data is output to a round-in/output pin. 9. A memory control method, comprising: receiving an offset bit An address value Ν, and Ν is a row portion of an access address; generating a Μ random sequence data 'where Ν is the maximum value of Μ before denormalizing a first read data according to the access address address; and by And mixing the first random data with the first read data to de-randomize the first read data. 10. The method for controlling a memory according to claim 9, wherein Μ = Ν. The method for controlling a memory according to claim 9, wherein the generated random sequence data includes random sequence data satisfying a polynomial l+x^+xk. 12·as described in claim 9 Memory control method, where K= 11. The control method of the memory described in the item of claim 2012. 13. The method of claim 5, further comprising: a random sequence data path to generate random sequence data by selecting acceleration including pre-shift output. 14. A memory control method, comprising: receiving a partial migration ν, ν is a line portion of an access address; generating Μ random sequence data before randomizing the first read data according to the access address solution, wherein Μ is a range from 1 to the end of the line portion of the access address; and the second random sequence data is used to de-randomize the first read data. 15. The method of controlling a memory according to the item [51] of the patent application, further comprising outputting the first data that has been de-randomized through an input/output pin. 16. A method of controlling a memory, comprising: receiving a row of offset values Ν; generating at least one random sequence of data from a start seed until a count is incremented from a predetermined value to Ν; determining at least one of the random sequence data One of the data is an initial random sequence data; the data read from the memory or randomized by the initial random sequence data is written into the memory data. 46 201232261 17. The method of controlling a memory as described in claim 16 wherein the seed is based on one of a column address, a page address, a block unit, or a sector unit. 18. The method of controlling a memory as described in claim 16 wherein the predetermined value is zero. 19. The method of controlling a memory according to claim 16, wherein the at least one random sequence data comprises random sequence data satisfying a plurality of l+xK_1+xk. 20. The method of controlling a memory according to claim 18, wherein the determining comprises determining the last generated random sequence data as the initial random sequence data. 2L is a method of controlling a memory as described in claim 18, wherein the de-randomized data is output to a round-in/output pin. 22. The method of controlling a memory according to claim 18, wherein the data written to the memory is output from a round-in/round-out and the randomized data is output to a page buffer. Funeral 23. The method of claim 6, further comprising selecting a pre-shifted output-random sequence path to accelerate the generation of the at least one random sequence of data. 24. A memory device comprising: a flash memory cell array; a random sequence data generator having a random sequence data string; for generating a random circuit based on a first seed to 20123226lu' to mix the random Sequence data and data written to the flash memory cell array; a randomization circuit for de-randomizing data read from the flash memory cell array; and a control circuit 'for controlling the flash memory cell The random sequence data generator is activated by the array access and the memory access mode, wherein the random circuit and the de-random circuit are disposed between a page buffer and an input/output pin. 25. The memory device of claim 24, wherein a portion of the memory address is used as the first seed in a mode and a second seed is randomized in a second mode The sequence data generator is generated. 26. The memory device of claim 24, wherein the random sequence data generator is operative to generate random sequence data satisfying a polynomial l+xK-i+xk, where K is a positive integer. 27. The memory device of claim 24, wherein the random sequence data generator is configured to output at least one predetermined random sequence data according to a response of an acceleration signal. 28. A memory system comprising: a memory device comprising: a flash memory cell array; a sequence of circuits for generating random sequence data; and 48 201232261 a mixer for mixing random sequence data with Data written to the flash memory cell and de-randomized data read from the flash memory cell array, and a memory controller including a control circuit for controlling writing and transmitting the mixture The device reads data from the flash memory cell array. 29. The memory system as claimed in claim 28, further comprising at least - recording a Wei, placing a less-recording cage device comprising a flash memory cell array; and a random sequence f-way '(four) mixed random sequence The data and the data to be written into the array and the solution are randomized from the flash memory cell 30. The memory (4) as described in the scope of the patent application includes the error control circuit for the memory cell array. Perform error correction when reading data. Flash 31. As described in the scope of patent application 帛 28, the fast memory cell array is a multi-level cell type. Ί, 中32. If the application mentioned in the scope of claim 28 (4) _ Gans the memory device shouted in the "solid state hard disk ^ money body system, of which 33. As claimed in the scope of claim 28 Remember the memory «set and the record _ body ° H4 ' which card. (4) The controllers are all embedded in the solid state hard disk. 34. The processing device of claim 33 includes a processing device for controlling the solid state hard disk card. The memory system described in the & item, the more packaged hard disk card and at least one remaining solid 49 2012322 team - fine,; === = body system 'more package, two: == controller, control -^^ The memory system described in item % of the range is used to communicate with the solid state hard disk cards. Included / Scope 34th to find the title pure, more package =: pass: to provide the host processing device and the solid state hard disk extension a fine / u profit & the memory system described in item 34, including - Lin, connecting multiple processing devices and these solid state hard disk cards. The memory system described in item 3 of the Hi patent scope, further includes a transmitter for communicating with a cellular network. For example, the memory system described in Patent Application No. 33, further includes an image sensor for capturing images. 41. A memory device, comprising: a flash memory cell array; a random sequence data generator for generating at least one random sequence data string according to a first seed; a mixer for de-randomizing from the fast a data read by the flash memory cell array; and a control circuit for controlling access to the flash memory cell array and activating the random sequence data generator according to the memory access mode, wherein the memory address is in a mode A portion is used as the first seed at 50 201232261 and a second seed in a second mode is generated by the random sequence data generator. 42. The memory device of claim 41, wherein the mixer is further configured to randomize data to be written to the flash memory cell array with random sequence data. 43. The memory device of claim 41, wherein the mixer is configured to receive data read from the flash memory cell array through a page buffer, and the de-randomized data is transmitted through an input/ Output pin output. 44. The memory device of claim 41, wherein the control circuit is operative to generate an intermediate seed based on the first seed and to generate random sequence data based on the intermediate seed. 45. The memory device of claim 41, wherein the flash memory cell array comprises a flash of a multi-layered cell type. 46. The memory device of claim 45, wherein the mixer is configured to perform multi-value data transmission through a bitwise XOR operation. 51