KR20120116022A - Gate shielding for liquid crystal displays - Google Patents

Abstract

Systems and methods are provided for preventing parasitic capacitance in liquid crystal displays. The display panel according to an exemplary embodiment may include, for example, a pixel 42 having a pixel electrode 50 and a transistor 48 connected to the gate line 44. In addition, the pixel 42 may include a shielding conductor 76 interposed between the pixel electrode 50 and the gate line 44. Instead of between the gate line 44 and the pixel electrode 50, the parasitic capacitance 78 is formed between the gate line 44 and the shielding conductor 76 so that the shielding conductor 76 is connected to the gate line 44. Together, the pixel electrode 50 can be shielded from the parasitic capacitance.

Description

Gate shielding for liquid crystal displays {GATE SHIELDING FOR LIQUID CRYSTAL DISPLAYS}

TECHNICAL FIELD This disclosure relates generally to electronic displays and, more particularly, to techniques for reducing parasitic capacitance in electronic displays.

This section is intended to introduce the reader to various aspects of the technology that may be related to various aspects of the present disclosure, described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, these statements should be read in light of the above, and are not intended to admit the prior art.

Flat panel displays, such as liquid crystal displays (LCDs), are used in a wide variety of electronic devices, including consumer electronics such as televisions, computers and handheld devices (eg, mobile phones, audio and video players, gaming systems, etc.). Often used. Such display panels typically provide flat panel displays in relatively thin packages suitable for use in a variety of electronic products. In addition, such devices typically use less power than comparable display technologies, making them suitable for use in battery-powered devices or other contexts where it is desirable to minimize power usage. do.

LCD devices typically include a plurality of pixels (pixels) arranged in a matrix to display an image recognizable by a user. Individual pixels of the LCD device may variably allow light to pass when an electric field is applied to the liquid crystal material of each pixel, which may be generated by the voltage difference between the pixel electrode and the common electrode. When an activation voltage is applied to the gate and a data signal voltage is applied to the source, the thin film transistor TFT may transfer the voltage difference to the pixel electrode. However, parasitic capacitance between the gate line and the pixel electrode providing the gate activation voltage can interfere with the operation of the LCD device, creating visual artifacts or otherwise reducing the accuracy of the display. This problem may become more apparent as the resolution of the LCD is increased and more densely packaged.

SUMMARY OF THE INVENTION [

A summary of the specific embodiments disclosed herein is set out below. These aspects are presented merely to provide the reader with a brief summary of these specific embodiments, and it should be understood that these aspects are not intended to limit the scope of this disclosure. In fact, this disclosure may include various aspects that may not be specified below.

Embodiments of the present disclosure relate to systems and methods for preventing parasitic capacitance in liquid crystal displays. For example, the display panel according to an embodiment may include, for example, a pixel including a transistor and a pixel electrode connected to a gate line. In addition, the pixel may include a shielding conductor interposed between the pixel electrode and the gate line. The shielding conductor can shield the pixel electrode from the parasitic capacitance with the gate line by allowing a parasitic capacitance to be formed between the gate line and the shielding conductor instead of between the gate line and the pixel electrode.

Various aspects of this disclosure may be better understood upon reading the following detailed description and referring to the drawings.
1 is a block diagram of components of an electronic device, according to one embodiment.
2 is a front view of a handheld electronic device, according to one embodiment.
3 is a perspective view of a notebook computer, according to one embodiment.
4 is a circuit diagram illustrating a structure of unit pixels of a display of the device of FIG. 1, according to an embodiment.
5 is a circuit diagram of a gate-shielded unit pixel of the display of the device of FIG. 1, according to one embodiment.
6 is a flow chart illustrating one embodiment of a method for displaying images on a display of the device of FIG. 1 with reduced visual artifacts.

One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, the specification does not describe all the features of an actual implementation. In the development of any such actual implementation, as in any engineering or design project, a number of implementations may be used to achieve compliance with the developer's specific goals, such as system-related and business-related constraints that may vary from implementation to implementation. It should be understood that certain decisions must be made. In addition, while such development efforts may be complex and time consuming, it should be understood that it will nevertheless be a routine business of design, fabrication, and manufacture for those skilled in the art having the benefit of this disclosure.

The present embodiments are directed to a technique for preventing parasitic capacitance between electrical components within a display panel. In particular, an LCD display can activate rows of pixels by providing an activation voltage to the gates of the pixel transistors through the gate lines, and an inactive voltage (eg, ground) to the gates of the pixel transistors through the gate lines. By providing, we can deactivate the rows of pixels. As rows of pixels can be activated and deactivated very quickly, parasitic capacitance can become more dominant and more sensitive between gate lines and other components within the display panel (eg, more first order). )). In order to reduce the parasitic capacitance between the gate lines and the image signal storage components (e.g. pixel electrodes) of the display, shielding conductors complementary to the gate lines may be disposed between the gate lines and those components. Can be. The parasitic capacitance can then occur primarily between the gate lines and the shielding conductors, instead of the image signal storage components of the display.

As considered above, FIG. 1 shows a block diagram of an electronic device 10 employing a display 18 with gate shielding pixels. Among other things, electronic device 10 may include processor (s) 12, memory 14, nonvolatile storage 16, display 18, input structures 20, input / output (I / O) Interface 22, network interface (s) 24, and / or power source 26. In alternative embodiments, electronic device 10 may include more or fewer components.

In general, processor (s) 12 may control the operation of electronic device 10. In some embodiments, based on instructions loaded from nonvolatile storage 16 into memory 14, processor (s) 12 may respond to a user touch gesture input via display 18. In addition to these instructions, nonvolatile storage 16 may also store various data. By way of example, non-volatile storage 16 may include a hard disk drive and / or solid state storage, such as flash memory.

Display 18 may be a flat panel display, such as a liquid crystal display (LCD). As discussed in more detail below, certain image data storage components (eg, pixel electrodes) of the display 18 may include parasitic capacitance between certain other components (eg, gate lines) of the display 18. It can be shielded to reduce it. As a result, the image data storage components of the display 18 may be less likely to experience visual artifacts or reduced accuracy.

Display 18 may also represent one of input structures 20. Other input structures 20 may include, for example, a key, a button, and / or a switch. The I / O port 22 of the electronic device 10 enables the electronic device 10 to transmit data and allows other electronic devices 10 and / or various peripheral devices, such as an external keyboard or mouse. It may be possible to receive data from. Network interface (s) 24 may include personal area network (PAN) integration (eg, Bluetooth), local area network (LAN) (eg, Wi-Fi), and / or wide area network (WAN) integration (eg, 3G). ) Can be enabled. The power source 26 of the electronic device 10 may be any suitable power source, such as a rechargeable Li-poly battery and / or an alternating current (AC) power converter.

2 shows an electronic device 10 in the form of a handheld device 30, here a cellular telephone. Portable device 30 is provided in the context of a mobile phone and may include other types of portable devices (such as media players for playing music and / or video, personal data organizers, portable gaming platforms, and / or the like). Or combinations of such devices) may also be suitably provided as the electronic device 10. In addition, portable device 30 may integrate functionality of one or more types of devices, such as media players, mobile phones, gaming platforms, personal data organizers, and the like.

For example, in the illustrated embodiment, portable device 30 is in the form of a mobile phone capable of providing various additional functions (such as the ability to shoot, audio and / or video record, listen to music, play games, etc.). to be. As discussed with respect to the general electronic device of FIG. 1, portable device 30 may allow a user to connect to and communicate over the Internet or other networks, such as local or wide area networks. Portable device 30 may also communicate with other devices using short-range connections, such as Bluetooth and near field communication (NFC). By way of example, portable device 30 may be a model of an iPad® or iPhone® available from Apple, Cupertino, California.

The portable device 30 can include an enclosure 32 or body that protects internal components from physical damage and shields them from electromagnetic interference. Enclosure 32 may be formed of any suitable material, such as plastic, metal or composite material, and may allow certain frequencies of electromagnetic radiation to pass through wireless communication circuitry within portable device 30 to allow wireless communication. To facilitate. Enclosure 32 may also include user input structures 20 through which a user can interface with the device. Each user input structure 20 may be configured to help control device functionality when it is activated. For example, in a mobile phone implementation, one or more input structures 20 may toggle between sleep and wake modes, quiet ringers for mobile phone applications, volume It may be configured to invoke a "home" screen or menu to be displayed, such as to increase or decrease output.

Display 18 may display a graphical user interface (GUI) that allows a user to interact with portable device 30. The icons of the GUI may be selected via a touch screen included in the display 18, or may be selected by one or more input structures 20, such as a wheel or a button. Portable device 30 may also include various I / O ports 22 to allow connection of portable device 30 to external devices. For example, one I / O port 22 may be a port that allows for the transmission and reception of data or commands between the portable device 30 and another electronic device, such as a computer. This I / O port 22 may be Apple's proprietary port, or may be an open standard I / O port. Another I / O port 22 may include a headphone jack to allow the headset 34 to be connected to the portable device 30.

In addition to the portable device 30 of FIG. 2, the electronic device 10 may also take the form of a computer or other type of electronic device. Such computers are generally portable computers (such as laptops, laptops and / or tablet computers) and / or computers typically used in one place (such as conventional desktop computers, workstations and / or servers). It may include. In some embodiments, the electronic device 10 in the form of a computer is a MacBook®, MacBook® Pro, MacBook Air®, iMac®, available from Apple. It may be a model of a Mac® mini, or a Mac Pro®. In another embodiment, the electronic device 10 may be a tablet computing device, such as an iPad® available from Apple. By way of example, laptop computer 36 is shown in FIG. 3, which represents one embodiment of electronic device 10 in accordance with one embodiment of the present disclosure. Among other things, the computer 36 includes a housing 38, a display 18, input structures 20, and I / O ports 22.

In one embodiment, input structures 22 (such as a keyboard and / or touch pad) are used to start, control, or manipulate interactions with computer 36, such as a GUI or applications running on computer 36. Can make it possible to do. For example, the keyboard and / or touch pad can allow the user to navigate the user interface or application interface displayed on the display 18. As shown, computer 36 may also include various I / O ports 22 to allow connection of additional devices. For example, computer 36 may include one or more I / O ports 22, such as a USB port or other port, suitable for connecting to another electronic device, projector, supplemental display, or the like. have. In addition, computer 36 may include network connectivity, memory, and storage capabilities, as described in connection with FIG. 1.

As briefly mentioned above, the display 18 shown in the embodiments of FIGS. 1-3 may be a liquid crystal display (LCD). 4 shows a circuit diagram of such a display 18, according to one embodiment. As shown, the display 18 may include an LCD display panel 40 that includes unit pixels 42 arranged in a pixel array or matrix. In this array, each unit pixel 42 is shown with gate lines 44 (also referred to as "scanning lines") and source lines 46 (also referred to as "data lines"). It can be defined by the intersection of the rows and columns shown here respectively. For simplicity, only six unit pixels, each individually referred to by reference numerals 42a-42f, are shown, but in practical implementations, each source line 46 and gate line 44 may be hundreds or thousands of such units. It should be understood that it can include pixels 42.

As shown in this embodiment, each unit pixel 42 includes a thin film transistor (TFT) 48 for switching a data signal stored in each pixel electrode 50. In the illustrated embodiment, the source 52 of each TFT 48 may be electrically connected to the source line 46, and the gate 54 of each TFT 48 may be electrically connected to the gate line 44. Can be connected to. The drain 56 of each TFT 48 can be electrically connected to each pixel electrode 50. Each TFT 48 is a switching element that can be activated and deactivated (eg, turned on and turned off) for a predetermined period based on the presence or absence of each of the scan signals at the gate 54 of the TFT 48. Play a role.

When activated, the TFT 48 can store image signals received through each source line 46 as a charge on its corresponding pixel electrode 50. Image signals stored by the pixel electrode 50 may be used to generate an electric field between each pixel electrode 50 and a common electrode (not shown in FIG. 5). The electric field between each pixel electrode 50 and the common electrode may change the polarity of the liquid crystal layer on the unit pixel 42. The electric field can align the liquid crystal molecules within the liquid crystal layer to regulate light transmission. As the electric field changes, the amount of light may increase or decrease. In general, light may pass through unit pixel 42 at an intensity corresponding to an applied voltage (eg, from its source line 46).

The display 18 also controls the display panel 40 by receiving image data 60 from the processor (s) 12 and transmitting the corresponding image signals to the unit pixels 42 of the panel 40. Source driver integrated circuit (IC) 58, which may include a processor or chip, such as an ASIC. Source driver IC 58 may also be coupled to gate driver IC 62, which may activate or deactivate rows of unit pixels 42 via gate lines 44. As such, the source driver IC 58 sends timing information, indicated here by reference numeral 64, to the gate driver IC 62 to facilitate activation / deactivation of the individual rows of pixels 42. Can transmit In other embodiments, timing information may be provided to gate driver IC 62 in some other manner.

In operation, source driver IC 58 receives image data 60 from processor (s) 12 or a separate display controller, and outputs signals to control pixel 42 based on the received data. . For example, to display the image data 60, the source driver IC 58 may adjust the voltage of the pixel electrode 50 one row at a time. To access an individual row of pixels 42, gate driver IC 62 may send an activation signal (eg, an activation voltage) to TFTs 48 associated with the row of pixels 42, thereby addressing the address. The TFTs 48 in a row are made conductive. The source driver IC 58 may transmit certain data signals to the unit pixels 42 of the row addressed through the respective source lines 86. Thereafter, the gate driver IC 62 may deactivate the TFTs 48 in the addressed row by applying an inactivation signal (eg, a voltage lower than the activation voltage, such as ground), whereby the next they are addressed. It may delay the change of state of the pixels 42 in the row by time. The process described above may be repeated for each row of pixels 42 in panel 40 to reproduce image data 60 as an image seen on display 18. If an activation signal is sent across the gate line 44 to activate a row of pixels 42, or if the activation signal is withdrawn to deactivate a row of pixels, a rapid change in voltage may occur within the row. Parasitic capacitance may be made more dominant and more sensitive (eg, higher priority) between the gate lines 44 of the pixels 42 and the pixel electrodes 50. As such, display panel 40 may include some shielding to reduce this parasitic capacitance.

5 shows a circuit diagram of one embodiment of a pixel 42 in more detail. As shown, the TFT 48 is connected to the source line 46 (D _x ) and the gate line 44 (G _y ). The pixel electrode 50 and the common electrode 68 may form a liquid crystal capacitor 70. The common electrode 68 is connected to a common voltage line 72 which provides a common voltage V _COM . V _COM line 72 may be formed substantially in parallel to gate lines 44, or in other embodiments, substantially parallel to source lines 46.

In the present embodiment, the pixel 42 also includes a storage capacitor 74 having a first electrode connected to the drain 56 of the TFT 48 and a second electrode connected to the storage electrode line providing the storage voltage V _ST . Include. In other embodiments, the second electrode of the storage capacitor 74 may instead be connected to the previous gate line 44 (eg, G _{y −1} ) or ground. The storage capacitor 74 can sustain the pixel electrode voltage for holding periods (eg, until the next time gate line 44 (G _y ) is activated by gate driver IC 62).

Gate line 44 (G _y ) is generally a complementary gate shield of the same or similar conductive material, which may be located between gate line 44 (G _y ) and pixel electrode 50. It may have line 76 (G _{shield_y} ). The dominant parasitic capacitance is parasitic capacitance 78 between gate line 44 (G _y ) and gate shield line 76 (G _{shield_y} ) rather than between gate line 44 (G _y ) and pixel electrode 50. May be). Thus, when the voltage of the gate line 44 (G _y ) changes rapidly (eg, during activation or deactivation of the unit pixel 42), the voltage is equal to the gate line 44 (G _y ) and the pixel electrode 50. Parasitic doses in between can be much less affected. In some embodiments, gate shield line 76 may cause pixel electrode 50 to have significantly reduced parasitic capacitance with gate line 44.

One embodiment of a method for operating display panel 40 in a manner that reduces parasitic capacitance is shown in flow chart 90 of FIG. 6. In general, the gate line 44 may be provided with a variable voltage (eg, an activation voltage or an inactivation voltage at any point in time), but the gate shield line 76 may be provided with a constant voltage (block 92). ). In particular, in some embodiments, such a gate shield line 76 has a current lower than the activation voltage, higher than the activation voltage, equal to the activation voltage, or present in the display panel 18 or in the row of currently addressed pixels in the display panel. The same constant voltage may be provided to the average value of the provided data signals. In some embodiments, such gate shield line 76 may be grounded.

Thereafter, gate driver IC 60 may activate and deactivate rows of pixels 42 (block 94). Some parasitic capacitance (eg, parasitic capacitance 78) may exist between gate lines 44 and corresponding gate shield lines 76, so that pixel electrodes 50 and gate lines of pixels 42 are present. Parasitic doses between 44 can be significantly reduced. Thus, when the rows of pixels 42 are activated and deactivated, the voltages of the pixel electrodes 50 will experience much less variation due to the parasitic capacitance between the pixel electrodes 50 and the gate lines 44. Can be.

In alternative embodiments, the gate shield lines 76 may have ground and another voltage (eg, activation voltage in some embodiments) at a frequency less than the frequency at which the activation voltage is switched on or switched off. Voltages that vary between lower voltages) may be provided. For these embodiments, the frequency of the voltage change in the gate shield lines 76 may be sufficiently low such that despite any parasitic capacitance between the gate shield lines 76 and the pixel electrodes 50, the pixel The voltages 50 are not greatly affected. That is, the varying voltages of the gate shield lines 76 cannot significantly alter the pixel electrode 50 performance due to this parasitic capacitance between the gate shield lines 76 and the pixel electrodes 50 (eg, The accuracy of the pixel electrodes 50 is substantially invisible to the naked eye). In general, for these embodiments, gate shield line 76 may be grounded to reduce power consumption if the gate line 44 does not attempt to activate a row of pixels 42. Thereafter, the gate shield line 76 is lower than the desired voltage (eg, the activation voltage) at the time when the gate line 44 activates and deactivates the row of pixels 42 before gradually decreasing back to ground. Voltage) to increase gradually.

It is to be understood that the specific embodiments described above are shown by way of example, and that such embodiments may be sensitive to various modifications and alternative forms. It is to be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

Claims (20)

As a display panel,
pixel
Including,
The pixel is,
Pixel electrodes;
A transistor having a drain connected to the pixel electrode, a source connected to a data line, and a gate connected to a gate line, wherein the transistor, upon receiving an activation signal from the gate line, passes the data signal from the data line to the pixel electrode. Configured to cause; And
A shielding conductor interposed between the pixel electrode and the gate line—the shielding conductor, along with the gate line, causes parasitic capacitance between the gate line and the shielding conductor, instead of between the gate line and the pixel electrode. Configured to shield the pixel electrode from parasitic capacitance-
Display panel comprising a. The display panel of claim 1, wherein the shielding conductor is configured to carry a constant voltage. The display panel of claim 1, wherein the shielding conductor is configured to carry a voltage equal to an activation voltage provided by the gate line. The display panel of claim 1, wherein the shielding conductor is configured to carry a voltage lower than an activation voltage provided by the gate line. The display panel of claim 1, wherein the shielding conductor is configured to carry a voltage higher than an activation voltage provided by the gate line. The display panel of claim 1, wherein the shielding conductor is grounded. The display panel of claim 1, wherein the shielding conductor is configured to carry a voltage that varies more slowly than an activation voltage provided by the gate line. As a system,
A processor configured to generate display signals; And
A display configured to generate pixel activation signals and pixel data signals based on the display signals
Including,
The display is configured to provide the pixel activation signals and pixel data signals to pixels of the display via signal conductors,
The pixels of the display shield the voltage changes of the pixel electrodes due to parasitic capacitance between the signal conductors and the pixel electrodes when the pixel activation signals or the pixel data signals are provided to the pixels. And shielding conductors interposed between the pixel electrodes of the pixels and the subset of signal conductors. The system of claim 8, wherein the shielding conductors are substantially parallel to a subset of the signal conductors. The system of claim 8, wherein the shielding conductors are substantially equidistant between the subset of the signal conductors and the pixel electrodes. As a display panel,
A plurality of pixel electrodes configured to store data signals;
A plurality of data signal carriers configured to carry the data signals;
A plurality of transistors corresponding to and connected to the plurality of pixel electrodes, wherein the plurality of transistors are configured such that the activation signals are applied to the gates of the plurality of transistors from the plurality of data signal carriers to the plurality of pixel electrodes. Configured to pass data signals;
A plurality of gate lines configured to provide the activation signals to the gates of the plurality of transistors; And
A plurality of shielding lines corresponding to the plurality of gate lines, wherein the plurality of shielding lines are interposed between subsets of the plurality of pixel electrodes and the gate lines, the plurality of shielding lines being the plurality of gate lines Configured to shield the plurality of pixel electrodes from parasitic capacitance from
Display panel comprising a. The display panel of claim 11, wherein each of the plurality of shield lines is configured to shield one of the subsets of the plurality of pixel electrodes from parasitic capacitance from one of the plurality of gate lines. The display panel of claim 11, wherein the plurality of shielding lines are configured to carry substantially constant voltage. The display panel of claim 11, wherein the plurality of shielding lines are configured to carry a voltage approximately equal to an average value of the data signals. The display panel of claim 11, wherein the plurality of shielding lines are configured to carry a first voltage that varies less often than a second voltage carried by the plurality of gate lines. Providing an activation signal to the plurality of pixels through the gate line;
Providing an inactivation signal to the plurality of pixels through the gate line; And
In the case where the activation signal and the deactivation signal are provided using a shielding conductor configured to cause parasitic capacitance between the gate line and the shielding conductor, instead of between the gate line and the pixel electrodes of the plurality of pixels, Shielding pixel electrodes of the plurality of pixels from parasitic capacitance between the pixel electrodes and the gate line
≪ / RTI > 17. The method of claim 16, wherein the pixel electrodes of the plurality of pixels are shielded by the shielding conductor, wherein the shielding conductor is substantially parallel to the gate line. 17. The method of claim 16 including providing a constant voltage to the shielding conductor. 17. The method of claim 16 including providing a voltage to said shield conductor that is less than said activation signal and greater than said deactivation signal. 17. The method of claim 16, comprising providing a low frequency voltage to the shield conductor, wherein the low frequency voltage is a parasitic that significantly alters pixel electrode performance between the shield conductors of the plurality of pixels and the pixel electrodes. Having a frequency low enough to substantially prevent a dose.

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