KR20120104845A - Solar cell and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A solar battery and a manufacturing method thereof are provided to increase mobility of a carrier by applying a conductive layer. CONSTITUTION: A first semiconductor layer(200) is formed on one side of a semiconductor wafer. A first conductive layer(300) is formed on the first semiconductor layer. A first electrode(400) is formed on the first conductive layer. A second semiconductor layer is formed on the other side of the semiconductor wafer. The second semiconductor layer has different polarity with the first semiconductor layer. A second conductive layer(600) is formed on the second semiconductor layer. A second electrode(700) is formed on the second conductive layer.

Description

Solar cell and method of manufacturing the same {Solar Cell and method of manufacturing the same}

The present invention relates to a solar cell, and more particularly, to a solar cell in which a substrate-type solar cell and a thin film-type solar cell are combined.

Solar cells are devices that convert light energy into electrical energy using the properties of semiconductors.

The solar cell has a PN junction structure in which a P (positive) type semiconductor and an N (negative) type semiconductor are bonded together. Holes and electrons are generated therein. At this time, the holes (+) move toward the P-type semiconductor and the electrons (-) move toward the N-type semiconductor due to the electric field generated in the PN junction. Can be generated to produce power.

Such solar cells are generally classified into substrate type solar cells and thin film type solar cells.

The substrate type solar cell is a solar cell manufactured using a semiconductor material such as silicon as a substrate, and the thin film type solar cell is a solar cell manufactured by forming a semiconductor in the form of a thin film on a substrate such as glass.

The substrate-type solar cell has an advantage that the efficiency is somewhat superior to the thin-film solar cell, the thin-film solar cell has the advantage that the manufacturing cost is reduced compared to the substrate-type solar cell.

Thus, a solar cell combining the substrate type solar cell and the thin film type solar cell has been proposed. Hereinafter, a conventional solar cell will be described with reference to the drawings.

1 is a schematic cross-sectional view of a solar cell according to an exemplary embodiment in which a substrate type solar cell and a thin film type solar cell are combined.

As can be seen in Figure 1, the solar cell according to a conventional embodiment, the semiconductor wafer 10, the first semiconductor layer 20, the first electrode 40, the second semiconductor layer 50, and the second It comprises an electrode 70.

The first semiconductor layer 20 is formed in the form of a thin film on the upper surface of the semiconductor wafer 10, the second semiconductor layer 50 is formed in the form of a thin film on the lower surface of the semiconductor wafer 10, such as The PN junction structure is formed by the combination of the semiconductor wafer 10, the first semiconductor layer 20, and the second semiconductor layer 50.

The first electrode 40 is formed on the first semiconductor layer 20, and the second electrode 70 is formed on the second semiconductor layer 50, and each of the (+) electrodes of the solar cell. Or (-) electrode.

When sunlight is incident on the solar cell according to the related art, a carrier such as a hole or an electron is generated in the semiconductor wafer 10, and the carrier is the first carrier. The first electrode 40 is moved through the semiconductor layer 20, and the second electrode 70 is moved through the second semiconductor layer 50.

However, the solar cell according to the related art has a low mobility in which carriers such as holes or electrons generated in the semiconductor wafer 10 move to the first electrode 40 or the second electrode 70. There is a limit to the efficiency of solar cells.

Therefore, the solar cell to which the conductive layer is further applied to improve the mobility of the carrier such as holes or electrons generated in the semiconductor wafer 10 to the first electrode 40 or the second electrode 70. Has been proposed.

2A to 2G are schematic cross-sectional views of a solar cell according to another exemplary embodiment in which a substrate type solar cell and a thin film type solar cell are combined, which is formed between the first semiconductor layer 20 and the first electrode 40. And by further forming a conductive layer between the second semiconductor layer 50 and the second electrode 70.

First, as shown in FIG. 2A, the first semiconductor layer 20 is formed on the upper surface of the semiconductor wafer 10.

Next, as shown in FIG. 2B, a first conductive layer 30 is formed on the first semiconductor layer 20.

The first conductive layer 30 is formed of a transparent conductive material such as indium tin oxide (ITO) by sputtering.

In this case, as shown in FIG. 2B, the first conductive layer 30 is formed not only on the upper surface of the first semiconductor layer 20 but also on the side surface of the semiconductor wafer 10 along its side.

Next, as shown in FIG. 2C, a first electrode 40 is formed on the first conductive layer 30.

Next, as shown in FIG. 2D, the second semiconductor layer 50 is formed on the bottom surface of the semiconductor wafer 10.

Next, as shown in FIG. 2E, a second conductive layer 60 is formed on the second semiconductor layer 50.

The second conductive layer 60 is formed of a transparent conductive material such as indium tin oxide (ITO) by sputtering.

As shown in FIG. 2E, the second conductive layer 60 is formed not only on the bottom surface of the second semiconductor layer 50 but also on the side surface of the semiconductor wafer 10 along the side surface thereof.

Next, as shown in FIG. 2F, a second electrode 70 is formed on the second conductive layer 60.

Next, as shown in FIG. 2G, the separation region 80 is formed by removing edge regions of the first conductive layer 30, the first semiconductor layer 20, and the semiconductor wafer 10.

The separation part 80 may be formed because the first conductive layer 30 and the second conductive layer 60 extend along side surfaces of the semiconductor wafer 10 due to process characteristics, so that the short may occur. This is to prevent such a short.

However, when the edge portions of the first conductive layer 30, the first semiconductor layer 20, and the semiconductor wafer 10 are removed to form the separator 80, electrons are formed in the separator 80. Alternatively, there is a problem in that the efficiency of the solar cell is lowered by trapping a carrier such as a hole.

In addition, since the laser process is added to form the separation unit 80, there is a problem in that the process is added and the cost is increased.

In addition, FIG. 14 is a schematic diagram of a conventional solar cell panel. As shown in FIG. 14, in the conventional solar cell panel, a plurality of unit solar cells are disposed on the support 1, and the above-described operation is performed on an edge region of each unit solar cell. As described above, the separation part 80 is formed, and the appearance may be rough.

The present invention has been devised to solve the above-described problems of the conventional solar cell, and the present invention provides a solar cell and its manufacture, which do not need to form a separator in an edge region of a semiconductor wafer while improving the mobility of a carrier by applying a conductive layer. It is an object to provide a method.

In order to achieve the above object, the present invention provides a semiconductor wafer having a predetermined conductivity polarity: a first semiconductor layer formed on one surface of the semiconductor wafer; A first conductive layer formed on the first semiconductor layer; A first electrode formed on the first conductive layer; A second semiconductor layer formed on the other surface of the semiconductor wafer and having a different polarity than that of the first semiconductor layer; A second conductive layer formed on the second semiconductor layer; And a second electrode formed on the second conductive layer, wherein at least one of the first conductive layer and the second conductive layer includes a central portion and a peripheral portion extending from the central portion. The electrical conductivity of the peripheral portion is lower than the electrical conductivity of the central portion provides a solar cell.

The first conductive layer and the second conductive layer are in contact with each other at the side portions of the semiconductor wafer. In this case, no separation portion is formed in the edge regions of the first conductive layer and the second conductive layer.

The peripheral portion may have a lower dopant concentration than the central portion.

The peripheral portion may have a greater number of crystals than the central portion.

The periphery may be distributed in a variety of crystal angles than the central portion. In this case, the crystals formed in the periphery may have three or more crystal growth angles having a count value in a range of 150 to 400.

Deposition thickness of the conductive layer consisting of the central portion and the peripheral portion may range from 50 to 500 nm.

The resistance between two points of the peripheral portion may range from 100 to 150 kΩ, and the resistance between two points of the central portion may range from 6 to 10 kΩ.

The peripheral portion includes a portion formed at a corner portion of the semiconductor wafer and a portion formed at a side portion of the semiconductor wafer, and a portion formed at a side portion of the semiconductor wafer is formed at a corner portion of the semiconductor wafer. In comparison, the electrical conductivity may be low.

An intrinsic semiconductor layer may be further formed between at least one of the semiconductor wafer and the first semiconductor layer and between the semiconductor wafer and the second semiconductor layer.

At least one semiconductor layer of the first semiconductor layer and the second semiconductor layer may be formed of a lightly doped semiconductor layer formed on the semiconductor wafer and a heavily doped semiconductor layer formed on the lightly doped semiconductor layer.

At least one of the first semiconductor layer and the first conductive layer and between the second semiconductor layer and the second conductive layer has an auxiliary layer having a predetermined polarity capable of enhancing mobility of a carrier generated in the semiconductor wafer. And a second auxiliary layer having a negative polarity, wherein the auxiliary layer includes an oxygen-rich oxide to attract holes generated in the semiconductor wafer, and the semiconductor layer. It may include at least one of the (+) polar second auxiliary layer made of an oxygen-deficient oxide to attract electrons generated in the wafer.

The present invention also provides a method for forming a first semiconductor layer on one surface of a semiconductor wafer having a predetermined electrical conductivity polarity and forming a second semiconductor layer having a different polarity than the first semiconductor layer on the other surface of the semiconductor wafer. fair; Forming a first conductive layer on the first semiconductor layer and forming a second conductive layer on the second semiconductor layer; And forming a first electrode on the first conductive layer and forming a second electrode on the second conductive layer, wherein at least one of the first conductive layer and the second conductive layer is formed. The conductive layer is formed of a central portion formed by the MOCVD process and a peripheral portion extending from the central portion, the electrical conductivity of the peripheral portion provides a method of manufacturing a solar cell, characterized in that lower than the electrical conductivity of the central portion.

The process of forming the conductive layer including the central portion and the peripheral portion may be performed such that the dopant concentration of the peripheral portion is smaller than the dopant concentration of the central portion.

The process of forming the conductive layer formed of the central portion and the peripheral portion may be performed in a state in which the temperature of the peripheral portion of the wafer is higher than the temperature of the center portion of the wafer. Silver may be performed using a tray that contacts the peripheral portion of the wafer and does not contact the central portion of the wafer, or may be performed by contacting a pin with the peripheral portion of the wafer.

The process of forming the conductive layer including the central portion and the peripheral portion may be performed in a range of 160 to 350 ° C.

The method may further include forming an intrinsic semiconductor layer between at least one of the semiconductor wafer and the first semiconductor layer and between the semiconductor wafer and the second semiconductor layer.

The process of forming at least one semiconductor layer of the first semiconductor layer and the second semiconductor layer may include forming a lightly doped semiconductor layer on the semiconductor wafer and a heavily doped semiconductor layer on the lightly doped semiconductor layer. It may be made of a forming process.

An auxiliary layer having a predetermined polarity capable of enhancing mobility of carriers generated in the semiconductor wafer between at least one of the first semiconductor layer and the first conductive layer and between the second semiconductor layer and the second conductive layer. And a step of forming the auxiliary layer, wherein the step of forming the auxiliary layer includes a negative polarity agent including an oxygen-rich oxide to attract holes generated in the semiconductor wafer. A process of forming an auxiliary layer having a positive polarity including an oxygen-deficient oxide so as to attract electrons generated from the semiconductor wafer; Can be done.

The present invention also provides a support; And a plurality of unit solar cells fixed to the support and electrically connected to each other, wherein each of the plurality of unit solar cells is provided with a solar cell.

According to the present invention by the above configuration has the following effects.

According to the present invention, since the electrical conductivity of the periphery of at least one of the first conductive layer and the second conductive layer is poor, the first conductive layer and the second conductive layer are in contact with each other on the side of the semiconductor wafer. Even if, the operation of the solar cell does not occur.

Therefore, as in the prior art, it is not necessary to form a separator in the edge region of the first conductive layer or the second conductive layer in order to cut off the connection between the first conductive layer and the second conductive layer. The problem that the process is added and the cost is increased is solved, and the problem that the carrier is trapped in the separator to reduce the efficiency of the solar cell.

1 is a schematic cross-sectional view of a solar cell according to an exemplary embodiment in which a substrate type solar cell and a thin film type solar cell are combined.
2A to 2G are schematic cross-sectional views of a solar cell according to another exemplary embodiment in which a substrate type solar cell and a thin film type solar cell are combined.
3 is a schematic cross-sectional view of a solar cell according to a first embodiment of the present invention.
4 is a view showing a change in crystal growth form of ZnO with temperature changes.
5 is a view showing a change in crystal growth form of ZnO according to the thickness change.
6 is a schematic cross-sectional view of a solar cell according to a second embodiment of the present invention.
7 is a schematic cross-sectional view of a solar cell according to a third embodiment of the present invention.
8 is a schematic cross-sectional view of a solar cell according to a fourth embodiment of the present invention.
9A to 9C are schematic process cross-sectional views illustrating a manufacturing process of a solar cell according to an embodiment of the present invention.
10A is a schematic cross-sectional view illustrating a tray supporting a wafer to form a second conductive layer according to an embodiment of the present invention.
FIG. 10B is a schematic cross-sectional view illustrating contact of a predetermined pin with a wafer to form a second conductive layer according to an embodiment of the present invention.
11A to 11C are schematic cross-sectional views illustrating a manufacturing process of a solar cell according to another embodiment of the present invention.
12A to 12C are schematic cross-sectional views illustrating a manufacturing process of a solar cell according to still another embodiment of the present invention.
13A to 13C are schematic cross-sectional views illustrating a manufacturing process of a solar cell according to still another embodiment of the present invention.
14 is a schematic diagram of a conventional solar cell panel.
15 is a schematic view of a solar cell panel according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

Solar cell

3 is a schematic cross-sectional view of a solar cell according to a first embodiment of the present invention.

As can be seen in Figure 3, the solar cell according to the first embodiment of the present invention, the semiconductor wafer 100, the first semiconductor layer 200, the first conductive layer 300, the first electrode 400, And a second semiconductor layer 500, a second conductive layer 600, and a second electrode 700.

The semiconductor wafer 100 may have a predetermined conductivity polarity. The semiconductor wafer 100 may be made of a silicon wafer, and specifically, may be made of an N-type silicon wafer or a P-type silicon wafer. The semiconductor wafer 100 has the same polarity as that of any one of the first semiconductor layer 200 and the second semiconductor layer 500.

On the other hand, although not shown, one surface, preferably, both the upper surface and the lower surface of the semiconductor wafer 100 can be formed in a concave-convex structure to enhance the absorption of sunlight, in this case, the semiconductor wafer 100 in turn The surface of the first semiconductor layer 200, the first conductive layer 300, the second semiconductor layer 500, the second conductive layer 600, and the like, which are formed, has a concave-convex structure.

The first semiconductor layer 200 is formed in the form of a thin film on the upper surface of the semiconductor wafer 100. The first semiconductor layer 200 may form a PN junction with the semiconductor wafer 100. Therefore, when the semiconductor wafer 100 is made of an N-type silicon wafer, the first semiconductor layer 200 may be formed. It may be made of a P-type semiconductor layer. In particular, the first semiconductor layer 200 may be made of P-type amorphous silicon doped with a Group III element such as boron (B).

In general, since the drift mobility of holes is lower than the drift mobility of electrons, it is preferable to form a P-type semiconductor layer close to the light-receiving surface in order to maximize hole collection efficiency due to incident light. It is preferable that the first semiconductor layer 200 close to the surface is made of a P-type semiconductor layer.

The first conductive layer 300 collects carriers, for example, holes, generated in the semiconductor wafer 100 and moves the collected carriers to the first electrode 400.

The first conductive layer 300 may be made of a transparent conductive material such as indium tin oxide (ITO), ZnOH, ZnO: B, ZnO: Al, SnO ₂ , SnO ₂ : F, and the like, and preferably ITO (Indium) Tin Oxide).

The first conductive layer 300 may be formed not only on the upper surface of the first semiconductor layer 200 but also on the side surface of the semiconductor wafer 100 along its side in view of its formation process characteristics.

The first electrode 400 is formed on the first conductive layer 300 to form a front surface of the solar cell. Therefore, the first electrode 400 is preferably formed in a predetermined pattern so that sunlight can pass through the solar cell.

The first electrode 400 is Ag, Al, Ag + Al, Ag + Mg, Ag + Mn, Ag + Sb, Ag + Zn, Ag + Mo, Ag + Ni, Ag + Cu, or Ag + Al + Zn It may be made of a metal material with excellent conductivity such as.

The second semiconductor layer 500 is formed in the form of a thin film on the lower surface of the semiconductor wafer 100. The second semiconductor layer 500 is formed to have a different polarity from the first semiconductor layer 200. The first semiconductor layer 200 is a P-type semiconductor layer doped with a Group III element such as boron (B). In this case, the second semiconductor layer 500 is formed of an N-type semiconductor layer doped with a Group 5 element such as phosphorus (P). In particular, the second semiconductor layer 500 may be made of N-type amorphous silicon.

The second conductive layer 600 collects carriers, eg, electrons, generated in the semiconductor wafer 100 and moves the collected carriers to the second electrode 700.

The second conductive layer 600 may be made of a transparent conductive material such as indium tin oxide (ITO), ZnOH, ZnO: B, ZnO: Al, SnO ₂ , SnO ₂ : F, and the like, and preferably ZnO: B It may be made of.

The second conductive layer 600 may be formed not only on the bottom surface of the second semiconductor layer 500 but also on the side surface of the semiconductor wafer 100 along its side in view of its formation process characteristics.

In this case, the second conductive layer 600 includes a central portion 600a and a peripheral portion 600b having different characteristics from each other. More specifically, the central portion 600a has excellent electrical conductivity, while the peripheral portion 600b has poor electrical conductivity.

In addition, the peripheral portion 600b may be divided into a portion formed at a corner portion of the semiconductor wafer 100 and a portion formed at a side portion of the semiconductor wafer 100. In this case, the peripheral portion 600b may be formed at a corner portion of the semiconductor wafer 100. Compared to the portion to be formed, the electrical conductivity of the portion formed on the side portion of the semiconductor wafer 100 may be more poorly formed.

Thus, although the first conductive layer 300 and the second conductive layer 600 contact each other at the side portion of the semiconductor wafer 100, the peripheral portion 600a of the second conductive layer 600 may be formed. Since the electrical conductivity is poor, there is no problem in the operation of the solar cell. As a result, as in the related art, in order to cut off the connection between the first conductive layer 300 and the second conductive layer 600, the first conductive layer 300 or the second conductive layer 600 is separated from the edge region. There is no need to form wealth.

The second conductive layer 600 may be formed through a metal organic chemical vapor deposition (MOCVD) process. In this case, the second conductive layer 600 may include a central portion 600a and a peripheral portion 600b having different electrical conductivity characteristics through the control of the MOCVD process. The second conductive layer 600 may be formed. This will be described in more detail as follows.

First, when the second conductive layer 600 is formed of a material such as ZnO: B through the MOCVD process, the dopant B concentration of the central portion 600a is increased and the dopant B of the peripheral portion 600b is formed during the MOCVD process. By decreasing the concentration, the second conductive layer 600 can be obtained in which the electrical conductivity of the central portion 600a is large and the electrical conductivity of the peripheral portion 600b is small. In order to obtain the second conductive layer 600, the amount of the dopant B supplied in the direction of the peripheral portion 600b may be smaller than that of the dopant B supplied in the direction of the central portion 600a when the raw material gas is supplied. In some cases, the dopant B may not be supplied in the direction of the peripheral part 600b.

Next, when forming the second conductive layer 600, by controlling the process so that the crystal growth form of the central portion 600a and the crystal growth form of the peripheral portion 600b are different, the electrical conductivity of the central portion 600a is large and the peripheral portion ( The second conductivity layer 600 having a small electrical conductivity of 600b can be obtained.

In more detail, the peripheral portion of the wafer 100 is wafers such as the tray supporting the wafer 100 is in contact with the peripheral portion of the wafer 100 but not in contact with the central portion of the wafer 100. When the second conductive layer 600 is deposited at a temperature higher than that of the center portion of the substrate 100, the crystal growth pattern of the central portion 600a may be different from that of the peripheral portion 600b. In particular, in this case, the crystals formed in the peripheral portion 600b, which is a high temperature region, may have a larger number of crystals and may have various growth angles than the crystals formed in the central portion 600a, which is a low temperature region. have. As such, when the number of crystals increases and the growth angles of the crystals are varied, the interface between the crystals may increase and the resistance may increase. Accordingly, the second conductive layer 600 having a smaller electrical conductivity of the peripheral portion 600b than the central portion 600a can be obtained.

On the other hand, in order to deposit the second conductive layer 600 in a state where the periphery of the wafer 100 is higher than the center of the wafer 100, as described above, the wafer 100 is in contact with the periphery of the wafer 100. The tray which is not in contact with the center portion of the wafer) may be used, and the peripheral temperature of the wafer 100 may be raised by bringing a pin in a high temperature state into the peripheral portion of the wafer 100.

4 is a diagram showing a change in crystal growth form of ZnO with temperature change. In general, as the temperature increases, the crystal grows and the number of crystals increases, thus the boundary between the crystal and the crystal acting as a resistive component. The number can also increase. In particular, as can be seen in Figure 4, it can be seen that as the temperature increases the number of angles representing the peak (peak) increases. Here, the angle refers to the angle at which the crystal grows, and the large number of angles representing the peak means that the crystal grows at various angles and the interface between the crystal and the crystal acting as a resistance component increases. In short, it can be seen that the resistance increases with increasing temperature.

In the present invention, the crystal formed in the peripheral portion 600b of the second conductive layer 600, it is preferable that the number of angles representing the peak is three or more, the central portion 600a of the second conductive layer 600 It is advantageous that the crystals formed at have two or less, more preferably one, angles representing peaks.

In addition, in FIG. 4, counts indicate a degree of crystallization. A small count value means that crystallization is not performed well, and a large count value means that crystallization is well performed. In the present invention, the crystal formed in the peripheral portion (600b) of the second conductive layer 600, it is preferable that the count value representing the peak is about 150 ~ 400, the reason is, the crystallization when the count value is less than 150 If the count value exceeds 400, the crystallization is too great, and the size of the crystal is increased so that the number of the interface between the crystal and the crystal acting as a resistive component may be reduced.

As described above, the second conductive layer 600 having a high electrical conductivity at the central portion 600a and a small electrical conductivity at the peripheral portion 600b is formed so that the crystal growth form of the central portion 600a is different from that of the peripheral portion 600b. As one of methods for obtaining the method, a method of depositing the second conductive layer 600 in a state in which the periphery of the wafer 100 is higher than the center of the wafer 100 may be used, wherein the process temperature is generally The temperature of the wafer 100 is preferably in the range of 160 ° C to 350 ° C. If the process temperature is less than 160 ° C., crystallization may not be performed well. If the process temperature exceeds 350 ° C., crystallization may not be performed due to excessively excessive temperature increase.

In addition, in order to obtain the second conductive layer 600 having a high electrical conductivity at the center portion 600a and a small electrical conductivity at the peripheral portion 600b, it is necessary to optimize the deposition thickness of the second conductive layer 600. In other words, if the deposition thickness of the second conductive layer 600 is too small, crystallization may not be performed well. If the deposition thickness of the second conductive layer 600 is too large, the size of the crystal is increased so that the peripheral portion 600b is formed. This is because the number of interfaces between the crystals and the crystals that should act as a resistive component decreases.

5 is a view showing a change in the crystal growth form of ZnO according to the thickness change, as can be seen in Figure 5, it can be seen that as the thickness increases in general, the number of angles representing the peak decreases. In other words, it can be seen that as the thickness increases, the crystal grows at a certain angle, thereby reducing the interface between the crystal acting as a resistance component and the crystal.

In consideration of such a point, the deposition thickness of the second conductive layer 600 is preferably in the range of 50 to 500 nm.

As described above, in the second conductive layer 600 according to the present invention, the electrical conductivity of the central portion 600a is large and the electrical conductivity of the peripheral portion 600b is small. In other words, the resistance of the central portion 600a is small and the resistance of the peripheral portion 600b is large. Specifically, the resistance between two points of the peripheral portion 600b is in a range of 100 to 150 kΩ, and the two of the central portion 600a are The resistance between the points is in the range of 6 to 10 kΩ.

As a result, the resistance between one point of the first conductive layer 300 and one point of the central portion 600a of the second conductive layer 600 is in a range of 200 to 300 kΩ, although the first conductive layer 300 ) And the second conductive layer 600 are in contact with each other on the side of the semiconductor wafer 100 does not cause a problem in the operation of the solar cell.

The second electrode 700 is formed on the second conductive layer 600. The second electrode 700 may be formed on the entire surface of the second conductive layer 600 because the second electrode 700 is formed on the rear surface of the solar cell. However, in order to allow the reflected sunlight to be incident through the rear surface of the solar cell, the second electrode 700 may also be formed in a pattern.

Like the first electrode 400, the second electrode 700 may include Ag, Al, Ag + Al, Ag + Mg, Ag + Mn, Ag + Sb, Ag + Zn, Ag + Mo, Ag + Ni, It may be made of a metal material such as Ag + Cu, or Ag + Al + Zn.

FIG. 6 is a schematic cross-sectional view of a solar cell according to a second embodiment of the present invention, in which a first intrinsic semiconductor layer 150 is additionally formed between the semiconductor wafer 100 and the first semiconductor layer 200. The second intrinsic semiconductor layer 450 is additionally formed between the semiconductor wafer 100 and the second semiconductor layer 500, and is the same as the solar cell according to the first embodiment illustrated in FIG. 3. Therefore, the same reference numerals are assigned to the same components, and repeated descriptions of the same components will be omitted.

When the first semiconductor layer 200 or the second semiconductor layer 500 is formed on the surface of the semiconductor wafer 100 using a high concentration of dopant gas, the surface of the semiconductor wafer 100 is formed by the high concentration of dopant gas. Defects may occur.

Therefore, in the second embodiment of the present invention illustrated in FIG. 6, the first intrinsic semiconductor layer 150 is formed on the upper surface of the semiconductor wafer 100, and then the first intrinsic semiconductor layer 150 is formed on the first intrinsic semiconductor layer 150. The semiconductor layer 200 is formed to prevent defects from occurring on the upper surface of the semiconductor wafer 100. In addition, the semiconductor wafer 100 may be formed by forming a second intrinsic semiconductor layer 450 on a lower surface of the semiconductor wafer 100 and then forming a second semiconductor layer 500 on the second intrinsic semiconductor layer 450. ) Is to prevent the occurrence of defects.

Meanwhile, although FIG. 6 illustrates a state in which both the first intrinsic semiconductor layer 150 and the second intrinsic semiconductor layer 450 are formed, any one of the first intrinsic semiconductor layer 150 and the second intrinsic semiconductor layer 450 is shown. It is also possible to form only intrinsic semiconductor layers.

FIG. 7 is a schematic cross-sectional view of a solar cell according to a third embodiment of the present invention, which is illustrated in FIG. 3 except that the structures of the first semiconductor layer 200 and the second semiconductor layer 500 are changed. The same as that of the solar cell according to the first embodiment. Therefore, the same reference numerals are assigned to the same components, and repeated descriptions of the same components will be omitted.

As can be seen in FIG. 7, according to the third embodiment of the present invention, the first semiconductor layer 200 is a lightly doped first semiconductor layer 200a and the lightly doped concentration formed on the upper surface of the semiconductor wafer 100. And a heavily doped first semiconductor layer 200b formed on the first semiconductor layer 200a.

In addition, the second semiconductor layer 500 may be a lightly doped second semiconductor layer 500a formed on the bottom surface of the semiconductor wafer 100 and a heavily doped second semiconductor layer 500a. It may be made of two semiconductor layers (500b).

In the present specification, the low concentration and the high concentration are relative concepts, and the low concentration doped first semiconductor layer 200a means that the concentration of the dopant is relatively smaller than the high concentration doped first semiconductor layer 200b.

The lightly doped first semiconductor layer 200a and the lightly doped second semiconductor layer 500a are respectively the first intrinsic semiconductor layer 150 and the second intrinsic in the second embodiment shown in FIG. It may play a role similar to that of the semiconductor layer 450.

In other words, by first forming a lightly doped first semiconductor layer 200a on the top surface of the semiconductor wafer 100 and then forming the first heavily doped semiconductor layer 200b, the top surface of the semiconductor wafer 100 is formed. Defects can be prevented, and a second lightly doped second semiconductor layer 500a is first formed on a bottom surface of the semiconductor wafer 100, and then the second lightly doped second semiconductor layer 500b is formed. Defects can be prevented from occurring on the lower surface of the semiconductor wafer 100 by forming the semiconductor layer 100.

Therefore, the dopant concentrations of the lightly doped first semiconductor layer 200a and the lightly doped second semiconductor layer 500a may be controlled to prevent defects on the surface of the semiconductor wafer 100.

The solar cell according to the third embodiment of the present invention shown in FIG. 7 has an advantage of superior productivity compared to the solar cell according to the second embodiment of the present invention shown in FIG. 6 described above.

That is, in the solar cell according to the second embodiment of the present invention shown in FIG. 6 described above, deposition equipment is added and the process is complicated to form the first intrinsic semiconductor layer 150 and the second intrinsic semiconductor layer 450. Although the productivity may be reduced, the solar cell according to the third exemplary embodiment of the present invention shown in FIG. 7 includes a chamber in which the lightly doped first semiconductor layer 200a and the heavily doped first semiconductor layer 200b are formed in one chamber. It can be carried out in a continuous process in the inside, and the low concentration doped second semiconductor layer (500a) and the high concentration doped second semiconductor layer (500b) can be carried out in a continuous process in one chamber to separate deposition The advantage is that no equipment or process is added.

Meanwhile, in FIG. 7, the first semiconductor layer 200 includes a lightly doped first semiconductor layer 200a and a heavily doped first semiconductor layer 200b, and the second semiconductor layer 500 is lightly doped. Although the second semiconductor layer 500a and the heavily doped second semiconductor layer 500b are illustrated, only one of the semiconductor layers may be formed of a lightly doped semiconductor layer and a heavily doped semiconductor layer.

8 is a schematic cross-sectional view of a solar cell according to a fourth exemplary embodiment of the present invention, in which a first auxiliary layer 250 is further formed between the first semiconductor layer 200 and the first conductive layer 300. In addition, except that the second auxiliary layer 550 is further formed between the second semiconductor layer 500 and the second conductive layer 600, the same as that of the solar cell according to the first embodiment of FIG. 3. Do. Therefore, the same reference numerals are assigned to the same components, and repeated descriptions of the same components will be omitted.

The first auxiliary layer 250 is formed between the first semiconductor layer 200 and the first conductive layer 300 so that a carrier, eg, a hole, generated in the semiconductor wafer 100 is formed in the first auxiliary layer 250. 1 serves to easily move to the conductive layer (300).

More specifically, when the first semiconductor layer 200 is formed of a P-type semiconductor layer, the first auxiliary layer 250 has a negative polarity so as to attract holes generated in the semiconductor wafer 100. In particular, the material layer having a (-) polarity may include an oxygen-rich oxide, specifically, Al ₂ O ₃ , Ga ₂ O ₃ Or an oxide containing a Group 3 element such as In ₂ O ₃ .

The second auxiliary layer 550 is formed between the second semiconductor layer 500 and the second conductive layer 600 so that a carrier, eg, an electron, generated in the semiconductor wafer 100 is formed of the second auxiliary layer 550. 2 serves to easily move to the conductive layer 600.

More specifically, when the second semiconductor layer 500 is formed of an N-type semiconductor layer, the second auxiliary layer 550 has a positive polarity so as to attract electrons generated from the semiconductor wafer 100. Preferably, the material layer having a positive polarity may be formed of an oxygen-deficient oxide, specifically, SiOx, TiOx, ZrOx, or HfOx. And oxides containing the same Group 4 elements.

Although FIG. 8 illustrates that both the first auxiliary layer 250 and the second auxiliary layer 550 are formed, only one of the first auxiliary layer 250 and the second auxiliary layer 550 may be formed. It may be.

On the other hand, in the preferred embodiment of the present invention described above, the second conductive layer 600 formed on the lower side of the semiconductor wafer 100 is not configured to extend to the side surface of the semiconductor wafer 100 is not incident to sunlight However, the present invention is not limited thereto, and the first conductive layer 300 formed on the upper side of the semiconductor wafer 100 into which the sunlight is incident may be formed so as not to extend to the side surface of the semiconductor wafer 100. That is, the first conductive layer 300 may be formed only on the upper surface of the first semiconductor layer 200 and may not extend to the side surface of the semiconductor wafer 100.

On the other hand, the second conductive layer 600 has been described in the form of the central portion (600a) and the peripheral portion (600b) with different electrical conductivity characteristics, but the present invention is not necessarily limited thereto, the first conductive The layer 300 may be formed of a central portion and a peripheral portion having different electrical conductivity properties. In some cases, the first conductive layer 300 and the second conductive layer 600 may be formed at the central portion and the peripheral portion having different electrical conductivity characteristics. Can be done.

Manufacturing method of solar cell

9A to 9C are schematic cross-sectional views illustrating a manufacturing process of a solar cell according to an embodiment of the present invention, which relates to the manufacturing method of the solar cell according to the first embodiment shown in FIG. .

First, as shown in FIG. 9A, a first semiconductor layer 200 is formed on an upper surface of a semiconductor wafer 100 having a predetermined conductivity polarity, and a second semiconductor layer is formed on a lower surface of the semiconductor wafer 100. Form 500.

The semiconductor wafer 100 may be made of an N-type silicon wafer.

In the process of forming the first semiconductor layer 200, a P-type semiconductor layer, for example, a P-type amorphous silicon layer, is formed on the upper surface of the semiconductor wafer 100 by using plasma enhanced chemical vapor deposition (PECVD). It can be made to the process.

In the process of forming the second semiconductor layer 500, an N-type semiconductor layer, for example, an N-type amorphous silicon layer is formed on the bottom surface of the semiconductor wafer 100 by using plasma enhanced chemical vapor deposition (PECVD). It can be made to the process.

There is no particular order between the process of forming the first semiconductor layer 200 and the process of forming the second semiconductor layer 500.

Next, as shown in FIG. 9B, a first conductive layer 300 is formed on the first semiconductor layer 200, and a second conductive layer 600 is formed on the second semiconductor layer 500. .

The process of forming the first conductive layer 300 is a transparent conductive material layer such as indium tin oxide (ITO), ZnOH, ZnO: B, ZnO: Al, SnO ₂ , or SnO ₂ : F, etc. by using a sputtering method, Preferably, it may be made of a process of forming indium tin oxide (ITO). The first conductive layer 300 may be formed to not only the upper surface of the first semiconductor layer 200 but also side surfaces of the semiconductor wafer 100 along the side surface thereof.

The process of forming the second conductive layer 600 is a transparent conductive material layer, such as ZnOH, ZnO: B, ZnO: Al, SnO ₂ , SnO ₂ : F, etc. by using a metal organic chemical vapor deposition (MOCVD) method, preferably It may be made of a process for forming ZnO: B.

As described above, the second conductive layer 600 may be formed to have excellent electrical conductivity at the center portion 600a and poorly at the peripheral portion 600b by various methods.

That is, in order to increase the concentration of the dopant B in the center portion 600a and decrease the concentration of the dopant B in the peripheral portion 600b during the MOCVD process, the peripheral portion is compared with the dopant B supplied in the direction of the central portion 600a during gas supply. The amount of the dopant B supplied in the (600b) direction can be reduced, and in some cases, the dopant B may not be supplied in the direction of the peripheral portion 600b.

In addition, in order to make the crystal growth form of the central portion 600a and the crystal growth form of the peripheral portion 600b different from each other, the second conductive layer 600 in the state where the peripheral portion of the wafer 100 is higher in temperature than the central portion of the wafer 100. And a tray 800 for supporting the wafer 100 as shown in FIG. 10A, in contact with the periphery of the wafer 100, but not in contact with the center of the wafer 100. A predetermined protrusion pattern may be formed on the tray 800.

In addition, as shown in FIG. 10B, the peripheral temperature of the wafer 100 may be increased by contacting the pin 900 in a high temperature state with the peripheral portion of the wafer 100 supported by the tray 800.

In addition, specific process conditions such as process temperature, deposition thickness, and the like are the same as described above, and thus repeated descriptions thereof will be omitted.

There is no special order between the process of forming the first conductive layer 300 and the process of forming the second conductive layer 600.

Next, as shown in FIG. 9C, a first electrode 400 is formed on the first conductive layer 300, and a second electrode 700 is formed on the second conductive layer 600.

The first electrode 400 may be formed in a pattern so that sunlight can be transmitted into the solar cell.

The first electrode 400 may include Ag, Al, Ag + Al, Ag + Mg, Ag + Mn, Ag + Sb, Ag + Zn, Ag + Mo, Ag + Ni, Ag + Cu, Ag + Al + Zn, or the like. It may be formed by a printing process using a paste of the same metal material. In this case, the printing process may include screen printing, inkjet printing, gravure printing, gravure offset printing, reverse printing, flexo printing, Alternatively, the method may be a micro contact printing method. As such, when the printing process is used, the first electrode 400 may be patterned to be spaced at predetermined intervals in one process.

The second electrode 700 includes Ag, Al, Ag + Al, Ag + Mg, Ag + Mn, Ag + Sb, Ag + Zn, Ag + Mo, Ag + Ni, Ag + Cu, Ag + Al + Zn, or the like. The same metal material may be formed using a sputtering method or the like, or a paste of the metal material may be formed using the above-described printing process.

As shown in the drawing, the second electrode 700 may be formed on the entire surface of the second conductive layer 600, but may also be patterned to allow sunlight to be incident thereon.

11A to 11C are schematic cross-sectional views illustrating a manufacturing process of a solar cell according to another embodiment of the present invention, which relates to the manufacturing method of the solar cell according to the second embodiment shown in FIG. . Detailed description of the same process as described above will be omitted.

First, as shown in FIG. 11A, a first intrinsic semiconductor layer 150 is formed on an upper surface of a semiconductor wafer 100 having a predetermined conductivity polarity, and a first semiconductor is formed on the first intrinsic semiconductor layer 150. A layer 200 is formed, together with a second intrinsic semiconductor layer 450 on the bottom surface of the semiconductor wafer 100 and a second semiconductor layer 500 on the second intrinsic semiconductor layer 450. To form.

The first intrinsic semiconductor layer 150 may be formed by forming an intrinsic (I) -type amorphous silicon layer on the upper surface of the semiconductor wafer 100 by using plasma enhanced chemical vapor deposition (PECVD).

The second intrinsic semiconductor layer 450 may be formed by forming an intrinsic (I) -type amorphous silicon layer on the bottom surface of the semiconductor wafer 100 by using plasma enhanced chemical vapor deposition (PECVD).

In the process of FIG. 11A, the first intrinsic semiconductor layer 150 is formed on the upper surface of the semiconductor wafer 100, and then the first semiconductor layer 200 is formed on the first intrinsic semiconductor layer 150. After that, a second intrinsic semiconductor layer 450 is formed on the bottom surface of the semiconductor wafer 100, and thereafter, a second semiconductor layer 500 is formed on the second intrinsic semiconductor layer 450. It may be made of a step of forming, but is not necessarily limited thereto.

For example, in the process of FIG. 11A, the first intrinsic semiconductor layer 150 is formed on the upper surface of the semiconductor wafer 100, and thereafter, the second intrinsic semiconductor layer ( 450, and thereafter, a first semiconductor layer 200 is formed on the first intrinsic semiconductor layer 150, and thereafter, a second semiconductor layer () is formed on the second intrinsic semiconductor layer 450. 500 may be formed.

Meanwhile, any one of the steps of forming the first intrinsic semiconductor layer 150 and the step of forming the second intrinsic semiconductor layer 450 may be omitted.

Next, as shown in FIG. 11B, a first conductive layer 300 is formed on the first semiconductor layer 200, and a second conductive layer 600 is formed on the second semiconductor layer 500. .

Next, as shown in FIG. 11C, a first electrode 400 is formed on the first conductive layer 300, and a second electrode 700 is formed on the second conductive layer 600.

12A to 12C are schematic cross-sectional views illustrating a manufacturing process of a solar cell according to still another embodiment of the present invention, which relates to a manufacturing method of the solar cell according to the third embodiment shown in FIG. will be. Detailed description of the same process as described above will be omitted.

First, as shown in FIG. 12A, a lightly doped first semiconductor layer 200a is formed on an upper surface of a semiconductor wafer 100 having a predetermined conductivity polarity, and the lightly doped first semiconductor layer 200a is formed. A high concentration doped first semiconductor layer 200b is formed thereon, and a lightly doped second semiconductor layer 500a is formed on the bottom surface of the semiconductor wafer 100, and the lightly doped second semiconductor is formed. A heavily doped second semiconductor layer 500b is formed on the layer 500a.

The lightly doped first semiconductor layer 200a and the heavily doped first semiconductor layer 200b may be performed in a continuous process in one chamber. That is, the doped P-type semiconductor layer 200a and the highly doped P-type semiconductor layer, such as boron (B), are controlled in a plasma enhanced chemical vapor deposition (PECVD) chamber. The P-type first semiconductor layer 200b may be continuously formed.

Specifically, in a process for producing the first solar cell under mass production, a predetermined amount of B ₂ H ₆ gas is introduced into the chamber to form a P-type dopant atmosphere in the chamber, and then SiH ₄ and H ₂ gases are formed. Supplying to form the lightly doped P-type semiconductor layer 200a, specifically, the lightly doped P-type amorphous silicon layer. Subsequently, B ₂ H ₆ gas is supplied as a dopant gas together with SiH ₄ and H ₂ gases to form the first heavily doped P-type semiconductor layer 200b, specifically, the heavily doped P-type amorphous silicon layer. .

Meanwhile, after the process of forming the heavily doped P-type first semiconductor layer 200b is completed, a predetermined amount of B ₂ H ₆ gas remains in the chamber. Therefore, since the production of the second solar cell after the production of the first solar cell, since the inside of the chamber is already formed in a P-type dopant atmosphere, SiH ₄ and H ₂ do not supply additional dopant gas, that is, B ₂ H ₆ gas into the chamber. By supplying only gas, the lightly doped P-type semiconductor layer 200a may be formed, followed by supplying B ₂ H ₆ gas together with SiH ₄ and H ₂ gas to supply the first heavily doped P-type. The semiconductor layer 200b is formed.

As described above, in another exemplary embodiment of the present invention, the lightly doped P-type semiconductor layer 200a and the heavily doped P-type semiconductor layer 200b are controlled by controlling only the supply amount of the reaction gas in one chamber. ) Can be formed continuously, there is an advantage that productivity is improved because no equipment or additional process is added.

The lightly doped second semiconductor layer 500a and the heavily doped second semiconductor layer 500b are similar to the above-described lightly doped first semiconductor layer 200a and heavily doped first semiconductor layer 200b. It can be carried out in a continuous process in the chamber of. That is, the low-doped N-type second semiconductor layer 500a and the high-doped semiconductor layer may be controlled in a single PECVD chamber using a dopant gas of a Group 5 element such as phosphorus (P). The N-type second semiconductor layer 500b may be continuously formed, and a detailed description thereof will be omitted.

Meanwhile, any one of the lightly doped first semiconductor layer 200a and the lightly doped second semiconductor layer 500a may be omitted.

Next, as shown in FIG. 12B, a first conductive layer 300 is formed on the first semiconductor layer 200, and a second conductive layer 600 is formed on the second semiconductor layer 500. .

Next, as shown in FIG. 12C, a first electrode 400 is formed on the first conductive layer 300, and a second electrode 700 is formed on the second conductive layer 600.

13A to 13C are schematic cross-sectional views illustrating a manufacturing process of a solar cell according to still another embodiment of the present invention, which relates to the manufacturing method of the solar cell according to the fourth embodiment shown in FIG. will be. Detailed description of the same process as described above will be omitted.

First, as shown in FIG. 13A, a first semiconductor layer 200 is formed on an upper surface of a semiconductor wafer 100 having a predetermined conductivity polarity, and a first auxiliary layer (eg, on the first semiconductor layer 200) is formed. 250, a second semiconductor layer 500 is formed on the bottom surface of the semiconductor wafer 100, and a second auxiliary layer 550 is formed on the second semiconductor layer 500. .

The process of forming the first auxiliary layer 250 may include a material layer having a negative polarity (eg, Al) on the first semiconductor layer 200 by using a metal organic chemical vapor deposition (MOCVD) method. _It may be made of a process of forming an oxygen-rich oxide layer containing a Group 3 element, such as ₂ O ₃ , Ga ₂ O ₃ , or In ₂ O ₃ .

The process of forming the second auxiliary layer 550 may include a material layer having positive polarity (eg, SiOx) on the second semiconductor layer 500 by using a metal organic chemical vapor deposition (MOCVD) method. , TiOx, ZrOx, or HfOx may be formed of a process for forming an oxygen-deficient oxide layer containing a group 4 element.

Meanwhile, the process of any one of the first auxiliary layer 250 and the second auxiliary layer 550 may be omitted.

Next, as shown in FIG. 13B, a first conductive layer 300 is formed on the first auxiliary layer 250, and a second conductive layer 600 is formed on the second auxiliary layer 550. .

Next, as shown in FIG. 13C, a first electrode 400 is formed on the first conductive layer 300, and a second electrode 700 is formed on the second conductive layer 600.

On the other hand, the second conductive layer 600 has been described in the form of the central portion (600a) and the peripheral portion (600b) with different electrical conductivity characteristics, but the present invention is not necessarily limited thereto, the first conductive The layer 300 may be formed of a central portion and a peripheral portion having different electrical conductivity properties. In some cases, the first conductive layer 300 and the second conductive layer 600 may be formed at the central portion and the peripheral portion having different electrical conductivity characteristics. Can be done.

In the above, the N-type semiconductor wafer is used as the semiconductor wafer 100, the first semiconductor layer 200 is formed of a P-type semiconductor layer, and the second semiconductor layer 500 is an N-type semiconductor layer. Although the present invention has been mainly described, the present invention is not necessarily limited thereto, and the present invention may be variously modified as long as it is a method of manufacturing a solar cell including a semiconductor wafer and a thin film semiconductor layer while forming a PN junction structure. will be. For example, in the present invention, a P-type semiconductor wafer is used as the semiconductor wafer 100, the first semiconductor layer 200 is formed of an N-type semiconductor layer, and the second semiconductor layer 500 is of a P-type. It also includes the case of forming with a semiconductor layer.

15 is a schematic view of a solar cell panel according to an embodiment of the present invention, as can be seen in Figure 15, the solar cell panel according to an embodiment of the present invention is fixed on the support (1) and the support (1) It comprises a plurality of unit solar cells (unit solar cell).

The unit solar cell may be applied to various types of solar cells manufactured by the above-described various methods, and in particular, each solar cell does not have a separator in its edge region, and thus the conventional solar cell shown in FIG. Compared to the solar cell panel, the appearance can be simple.

Each unit solar cell is electrically connected to each other, and the electrical connection between such unit solar cells may be applied in various ways known in the art.

100 semiconductor wafer 150 first intrinsic semiconductor layer
200: first semiconductor layer 200a: lightly doped first semiconductor layer
200b: heavily doped first semiconductor layer 250: first auxiliary layer
300: first conductive layer 400: first electrode
450: second intrinsic semiconductor layer 500: second semiconductor layer
500a: lightly doped second semiconductor layer 500b: lightly doped second semiconductor layer
550: second auxiliary layer 600: second conductive layer
600a: center portion of second conductive layer 600b: peripheral portion of second conductive layer
700: second electrode 800: tray
900: pin 1: support

Claims (22)

A semiconductor wafer having a predetermined conductivity polarity:
A first semiconductor layer formed on one surface of the semiconductor wafer;
A first conductive layer formed on the first semiconductor layer;
A first electrode formed on the first conductive layer;
A second semiconductor layer formed on the other surface of the semiconductor wafer and having a different polarity than that of the first semiconductor layer;
A second conductive layer formed on the second semiconductor layer; And
It comprises a second electrode formed on the second conductive layer,
In this case, at least one conductive layer of the first conductive layer and the second conductive layer is composed of a central portion and a peripheral portion extending from the central portion, the electrical conductivity of the peripheral portion is characterized in that the lower than the electrical conductivity of the central portion . The method of claim 1,
The first conductive layer and the second conductive layer are in contact with each other at the side portion of the semiconductor wafer, the solar cell, characterized in that no separation portion is formed in the edge region of the first conductive layer and the second conductive layer. The method of claim 1,
The peripheral portion of the solar cell, characterized in that the dopant concentration is lower than the central portion. The method of claim 1,
The peripheral portion is a solar cell, characterized in that the number of crystals more than the central portion. The method of claim 1,
The peripheral portion of the solar cell, characterized in that the growth angle of the crystal is distributed more than the central portion. The method of claim 5,
The crystal formed in the periphery of the solar cell, characterized in that the count value is three or more crystal growth angle of 150 to 400 range. The method of claim 1,
Solar cell, characterized in that the deposition thickness of the conductive layer consisting of the central portion and the peripheral portion range from 50 to 500 nm. The method of claim 1,
The resistance between the two points of the periphery is in the range of 100 ~ 150kΩ, the resistance between the two points of the central region is characterized in that the range of 6 ~ 10kΩ. The method of claim 1,
The peripheral portion includes a portion formed at a corner portion of the semiconductor wafer and a portion formed at a side portion of the semiconductor wafer, and a portion formed at a side portion of the semiconductor wafer is formed at a corner portion of the semiconductor wafer. Solar cell, characterized in that the electrical conductivity is lower than. The method of claim 1,
An intrinsic semiconductor layer is further formed between at least one of the semiconductor wafer and the first semiconductor layer and between the semiconductor wafer and the second semiconductor layer. The method of claim 1,
At least one semiconductor layer of the first semiconductor layer and the second semiconductor layer is characterized by consisting of a lightly doped semiconductor layer formed on the semiconductor wafer and a lightly doped semiconductor layer formed on the lightly doped semiconductor layer. battery. The method of claim 1,
At least one of the first semiconductor layer and the first conductive layer and between the second semiconductor layer and the second conductive layer has an auxiliary layer having a predetermined polarity capable of enhancing mobility of a carrier generated in the semiconductor wafer. Is further formed,
The auxiliary layer attracts the first auxiliary layer having a negative polarity including an oxygen-rich oxide to attract holes generated in the semiconductor wafer, and an electron generated in the semiconductor wafer. A solar cell comprising at least one of a second auxiliary layer having a positive polarity comprising an oxygen-deficient oxide to be pulled. Forming a first semiconductor layer on one surface of the semiconductor wafer having a predetermined conductivity polarity, and forming a second semiconductor layer having a different polarity from the first semiconductor layer on the other surface of the semiconductor wafer;
Forming a first conductive layer on the first semiconductor layer and forming a second conductive layer on the second semiconductor layer; And
Forming a first electrode on the first conductive layer, and forming a second electrode on the second conductive layer,
In this case, at least one of the first conductive layer and the second conductive layer may be formed of a central portion formed by a MOCVD process and a peripheral portion extending from the central portion, and the electrical conductivity of the peripheral portion is lower than that of the central portion. Method for manufacturing a solar cell characterized in that. The method of claim 13,
Forming the conductive layer consisting of the central portion and the peripheral portion, the manufacturing method of the solar cell, characterized in that the concentration of the dopant of the peripheral portion is less than the concentration of the dopant of the central portion. The method of claim 13,
The process of forming the conductive layer consisting of the central portion and the peripheral portion, the manufacturing method of the solar cell, characterized in that performed in a state where the temperature of the peripheral portion of the wafer is higher than the temperature of the central portion of the wafer. 16. The method of claim 15,
The process of forming a conductive layer consisting of the central portion and the peripheral portion is performed using a tray which is in contact with the peripheral portion of the wafer and not in contact with the central portion of the wafer. 16. The method of claim 15,
Forming a conductive layer consisting of the central portion and the peripheral portion, the manufacturing method of the solar cell, characterized in that performed by contacting the pin to the peripheral portion of the wafer. The method of claim 13,
Process for forming a conductive layer consisting of the central portion and the peripheral portion, manufacturing method of a solar cell, characterized in that performed in the range of 160 ~ 350 ℃. The method of claim 13,
And forming an intrinsic semiconductor layer between at least one of the semiconductor wafer and the first semiconductor layer and between the semiconductor wafer and the second semiconductor layer. The method of claim 13,
The process of forming at least one semiconductor layer of the first semiconductor layer and the second semiconductor layer may include forming a lightly doped semiconductor layer on the semiconductor wafer and a heavily doped semiconductor layer on the lightly doped semiconductor layer. Method for producing a solar cell, characterized in that consisting of a step of forming. The method of claim 13,
An auxiliary layer having a predetermined polarity capable of enhancing mobility of carriers generated in the semiconductor wafer between at least one of the first semiconductor layer and the first conductive layer and between the second semiconductor layer and the second conductive layer. Further comprising the step of forming a,
The forming of the auxiliary layer may include forming a first auxiliary layer having a negative polarity including an oxygen-rich oxide to attract holes generated in the semiconductor wafer and the semiconductor. Forming a second auxiliary layer having a positive polarity containing an oxygen-deficient oxide so as to attract electrons generated from the wafer. . support fixture; And
It comprises a plurality of unit solar cells fixed to the support and electrically connected to each other,
The solar cell panel, characterized in that each of the plurality of unit solar cells made of any one of the solar cells of claim 1 to claim 12.

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